The const accessors are OK (and arguably more correct) for most callers
to use. The _M_swap functions that use the non-const overloads can just
directly use the _S_get members of the EBO helpers.
* include/bits/hashtable_policy.h (_Hash_code_base::_M_swap): Use
_S_get accessors for members in EBO helpers.
(_Hash_code_base::_M_extract(), _Hash_code_base::_M_ranged_hash())
(_Hash_code_base::_M_h1(), _Hash_code_base::_M_h2()): Remove non-const
overloads.
(_Hashtable_base::_M_swap): Use _S_get accessors for members in EBO
helpers.
(_Hashtable_base::_M_eq()): Remove non-const overload.
From-SVN: r271286
PR fortran/90329
* tree-core.h (struct tree_decl_common): Document
decl_nonshareable_flag for PARM_DECLs.
* tree.h (DECL_HIDDEN_STRING_LENGTH): Define.
* calls.c (expand_call): Don't try tail call if caller
has any DECL_HIDDEN_STRING_LENGTH PARM_DECLs that are or might be
passed on the stack and callee needs to pass any arguments on the
stack.
* tree-streamer-in.c (unpack_ts_decl_common_value_fields): Use
else if instead of series of mutually exclusive ifs. Handle
DECL_HIDDEN_STRING_LENGTH for PARM_DECLs.
* tree-streamer-out.c (pack_ts_decl_common_value_fields): Likewise.
* trans-decl.c (create_function_arglist): Set
DECL_HIDDEN_STRING_LENGTH on hidden string length PARM_DECLs if
len is constant.
From-SVN: r271285
2019-05-16 Richard Biener <rguenther@suse.de>
PR testsuite/90502
* gcc.dg/tree-ssa/vector-6.c: Adjust for half of the
transforms happening earlier now.
From-SVN: r271283
In some cases the test using setssbsy was not enough to
detemine support for the CET insns. Adding -fcf-protection
explicitly causes other insns to be emitted (e.g. endbr32/64)
which are a more complete check.
2019-05-16 Iain Sandoe <iain@sandoe.co.uk>
* lib/target-supports.exp (check_effective_target_cet): Add the
-fcf-protection flag to the build conditions.
From-SVN: r271282
PR tree-optimization/90106
* tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Add
new parameter as new internal function call, also move it to new
basic block.
(use_internal_fn): Pass internal function call to
shrink_wrap_one_built_in_call_with_conds.
gcc/testsuite
* gcc.dg/cdce1.c: Check tailcall code generation after cdce pass.
* gcc.dg/cdce2.c: Likewise.
From-SVN: r271281
Account for Cortex-M3 Errata 602117. The -mfix-cortex-m3-ldrd option is
enabled by default, if -mcpu=cortex-m3 is used.
gcc/
* config/arm/t-rtems: Replace ARMv7-M multilibs with Cortex-M
multilibs.
From-SVN: r271280
If an interface does not escape, it doesn't need a heap
allocation to hold the data (for non-direct interface type).
This CL improves the escape analysis to track interface
conversions, and reduces these allocations.
Implicit interface conversions were mostly added late in the
compilation pipeline, after the escape analysis. For the escape
analysis to see them, we move the introduction of these
conversions earlier, right before the escape analysis.
Now that the compiler can generate interface conversions inlined,
gcc/testsuite/go.test/test/nilptr2.go needs to be adjusted as in
golang.org/cl/176579, so the use function does an actual use.
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/176459
* go.test/test/nilptr2.go: Change use function to actually do
something.
From-SVN: r271276
* omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set
max_vf to 1.
* omp-expand.c (expand_omp_simd): For if (0) or simdlen (1) clear
safelen_int and set loop->dont_vectorize.
* c-c++-common/gomp/simd8.c: New test.
From-SVN: r271270
PR debug/90197
* cp-gimplify.c (genericize_cp_loop): Emit a DEBUG_BEGIN_STMT
before the condition (or if missing or constant non-zero at the end
of the loop. Emit a DEBUG_BEGIN_STMT before the increment expression
if any. Don't call protected_set_expr_location on incr if it already
has a location.
From-SVN: r271269
* class.c (check_field_decls): Initialize booleans directly. A union
is literal if at least one of its non-static data members is of
non-volatile literal type.
* g++.dg/cpp0x/literal-type1.C: New test.
From-SVN: r271267
C preprocessor definitions should not be translated.
2019-05-15 Janne Blomqvist <jb@gcc.gnu.org>
* parse.c (gfc_parse_file): Remove translation string markers.
From-SVN: r271261
As of Fortran 2018 it's allowed to open the same file on multiple
units.
libgfortran/ChangeLog:
2019-05-15 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/90461
* io/open.c (new_unit): Don't check if the file is already open
for F2018.
testsuite/ChangeLog:
2019-05-15 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/90461
* gfortran.dg/open_errors_2.f90: Add -std=f2008, adjust line number.
* gfortran.dg/open_errors_3.f90: New test.
From-SVN: r271260
* config/i386/i386-expand.c (ix86_split_idivmod): Rename
signed_p argument to unsigned_p. Update all uses for changed polarity.
* config/i386/i386.md (u_bool): Handle DIV and UDIV RTXes.
(divmod splitters): Use u_bool macro in the call to ix86_split_idivmod.
From-SVN: r271259
2019-05-15 Paolo Carlini <paolo.carlini@oracle.com>
* cp-tree.h (REFERENCE_VLA_OK): Remove.
* lambda.c (build_capture_proxy): Remove use of the above.
From-SVN: r271258
This patch enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386-builtins.c (bdesc_tm): Enable MMX intrinsics
with SSE2.
From-SVN: r271253
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.def: Enable MMX intrinsics with
SSE/SSE2/SSSE3.
* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
Likewise.
* config/i386/i386-expand.c (ix86_expand_builtin): Allow
SSE/SSE2/SSSE3 to emulate MMX intrinsics with TARGET_MMX_WITH_SSE.
* config/i386/mmintrin.h: Only require SSE2 if __MMX_WITH_SSE__
is defined.
gcc/testsuite/
PR target/89021
* gcc.target/i386/pr82483-1.c: Error only on ia32.
* gcc.target/i386/pr82483-2.c: Likewise.
From-SVN: r271252
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_and_split to support SSE emulation.
From-SVN: r271247
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
SSE emulation.
From-SVN: r271245
Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):
Changed to define_insn_and_split to support SSE emulation.
From-SVN: r271242
Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
Changed to define_insn_and_split to support SSE emulation.
From-SVN: r271241
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.
PR target/89021
* config/i386/mmx.md (mmx_<emms>): Renamed to ...
(*mmx_<emms>): This.
(mmx_<emms>): New expander.
From-SVN: r271240
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2
maskmovdqu for __MMX_WITH_SSE__.
From-SVN: r271234
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
From-SVN: r271232
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split and also allow
TARGET_MMX_WITH_SSE to support SSE emulation.
From-SVN: r271226
Jonathan Wakely
Jakub Jelinek
Richard Biener
Iain Sandoe
Jun Ma
Sebastian Huber
Cherry Zhang
GCC Administrator
Marek Polacek
Janne Blomqvist
Uros Bizjak
Paolo Carlini
H.J. Lu
Uros Bizjak