2015-07-09 Steve Ellcey <sellcey@imgtec.com>
* config/mips/mti-linux.h (MIPS_SYSVERSION_SPEC): Update
to handle mips[32|64]r3 and mips[32|64]r5.
From-SVN: r225643
PR middle-end/66633
* tree-nested.c (get_static_chain): Or in a flag into
info->static_chain_added.
(get_frame_field, get_nonlocal_debug_decl): Likewise.
(convert_nonlocal_omp_clauses, convert_local_omp_clauses): Revert
2015-07-01 changes.
(convert_tramp_reference_stmt): If a frame_decl or chain_decl
is needed newly inside of GIMPLE_OMP_{PARALLEL,TASK,TARGET} body,
add it to clauses.
* gcc.dg/gomp/pr66633-1.c: New test.
* gcc.dg/gomp/pr66633-2.c: New test.
* gcc.dg/gomp/pr66633-3.c: New test.
* gcc.dg/gomp/pr66633-4.c: New test.
From-SVN: r225638
PR tree-optimization/66718
* tree-vect-stmts.c (struct simd_call_arg_info): Add simd_lane_linear
field.
(vect_simd_lane_linear): New function.
(vectorizable_simd_clone_call): Support using linear arguments for
addresses of arrays elements indexed by GOMP_SIMD_LANE result.
From-SVN: r225637
We reduce code size for IA MCU by adjusting variable shift costs for IA
MCU
PR target/66821
* config/i386/i386.c (iamcu_cost): Adjust variable shift costs.
From-SVN: r225635
2015-07-09 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory):
Use machine mode, not enum machine_mode in the prototype.
* config/rs6000/rs6000.h (FLOAT128_IEEE_P): New helper macros to
classify 128-bit floating point support.
(FLOAT128_IBM_P): Likewise.
(FLOAT128_VECTOR_P): Likewise.
(FLOAT128_2REG_P): Likewise.
(SCALAR_FLOAT_MODE_NOT_VECTOR_P): Likewise.
(SLOW_UNALIGNED_ACCESS): Add IEEE 128-bit floating point support.
(HARD_REGNO_CALLER_SAVE_MODE): Likewise.
(HARD_REGNO_CALL_PART_CLOBBERED): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Drop
tests against TFmode/TDmode, since those modes do not use VSX
addresses.
(rs6000_hard_regno_mode_ok): Add IEEE 128-bit floating point
support.
(rs6000_init_hard_regno_mode_ok): Use new helper macros instead of
tests against TFmode, etc.
(invalid_e500_subreg): Add tests against IFmode/KFmode.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Clean up tests against TFmode and
TDmode to use the new helper macros, which will include IFmode and
KFmode.
(rs6000_emit_move): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(print_operand): Likewise.
(rs6000_member_type_forces_blk): Treat IEEE 128-bit floating point
that uses a single vector register as a vector and not as a
floating point register in terms of the calling sequence.
(rs6000_discover_homogeneous_aggregate): Likewise.
(rs6000_return_in_memory): Likewise.
(init_cumulative_args): Likewise.
(rs6000_function_arg_boundary): Likewise.
(rs6000_function_arg_advance_1): Likewise.
(rs6000_function_arg): Likewise.
(rs6000_pass_by_reference): Likewise.
(rs6000_gimplify_va_arg): Likewise.
(rs6000_secondary_reload_memory): Use machine_mode not enum
machine mode.
(rs6000_split_multireg_move): Use new helper macros.
(spe_func_has_64bit_regs_p): Likewise.
(rs6000_output_function_epilogue): Add IFmode/KFmode support.
(output_toc): Use new helper macros.
(rs6000_register_move_cost): Likewise.
(rs6000_function_value): Add IEEE 128-bit floating point calling
sequence support.
(rs6000_libcall_value): Likewise.
(rs6000_scalar_mode_supported_p): Add support for IEEE 128-bit
floating point support.
(rs6000_vector_mode_supported_p): Likewise.
From-SVN: r225632
2015-07-09 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory):
Use machine mode, not enum machine_mode in the prototype.
* config/rs6000/rs6000.h (FLOAT128_IEEE_P): New helper macros to
classify 128-bit floating point support.
(FLOAT128_IBM_P): Likewise.
(FLOAT128_VECTOR_P): Likewise.
(FLOAT128_2REG_P): Likewise.
(SCALAR_FLOAT_MODE_NOT_VECTOR_P): Likewise.
(SLOW_UNALIGNED_ACCESS): Add IEEE 128-bit floating point support.
(HARD_REGNO_CALLER_SAVE_MODE): Likewise.
(HARD_REGNO_CALL_PART_CLOBBERED): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Drop
tests against TFmode/TDmode, since those modes do not use VSX
addresses.
(rs6000_hard_regno_mode_ok): Add IEEE 128-bit floating point
support.
(rs6000_init_hard_regno_mode_ok): Use new helper macros instead of
tests against TFmode, etc.
(invalid_e500_subreg): Add tests against IFmode/KFmode.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Clean up tests against TFmode and
TDmode to use the new helper macros, which will include IFmode and
KFmode.
(rs6000_emit_move): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(print_operand): Likewise.
(rs6000_member_type_forces_blk): Treat IEEE 128-bit floating point
that uses a single vector register as a vector and not as a
floating point register in terms of the calling sequence.
(rs6000_discover_homogeneous_aggregate): Likewise.
(rs6000_return_in_memory): Likewise.
(init_cumulative_args): Likewise.
(rs6000_function_arg_boundary): Likewise.
(rs6000_function_arg_advance_1): Likewise.
(rs6000_function_arg): Likewise.
(rs6000_pass_by_reference): Likewise.
(rs6000_gimplify_va_arg): Likewise.
(rs6000_secondary_reload_memory): Use machine_mode not enum
machine mode.
(rs6000_split_multireg_move): Use new helper macros.
(spe_func_has_64bit_regs_p): Likewise.
(rs6000_output_function_epilogue): Add IFmode/KFmode support.
(output_toc): Use new helper macros.
(rs6000_register_move_cost): Likewise.
(rs6000_function_value): Add IEEE 128-bit floating point calling
sequence support.
(rs6000_libcall_value): Likewise.
(rs6000_scalar_mode_supported_p): Add support for IEEE 128-bit
floating point support.
(rs6000_vector_mode_supported_p): Likewise.
From-SVN: r225631
2015-07-09 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/66782
* lra-int.h (struct lra_insn_recog_data): Add comment about
clobbered hard regs for arg_hard_regs.
* lra.c (lra_set_insn_recog_data): Add clobbered hard regs.
* lra-lives.c (process_bb_lives): Process clobbered hard regs.
Add condition for processing used hard regs.
* lra-constraints.c (update_ebb_live_info, inherit_in_ebb):
Process clobbered hard regs.
From-SVN: r225618
2015-07-09 Richard Biener <rguenther@suse.de>
* genmatch.c (struct expr): Add force_single_use flag.
(expr::expr): Add copy constructor.
(capture_info::walk_match): Gather force_single_use captures.
(expr::gen_transform): Use possibly NULLified sequence.
(dt_simplify::gen): Apply single-use restrictions by NULLifying
seq if any constrained expr is not single-use.
(parser::parse_expr): Refactor to allow multiple flags. Handle
's' flag to force an expression have a single-use if the pattern
simplifies to more than one statement.
* match.pd: Convert most single_use conditionals to :s flags.
From-SVN: r225610
attribute ((aligned)) should align to the minimum of BIGGEST_ALIGNMENT,
which is 4 bytes for -miamcu.
gcc/
PR target/66818
* config/i386/i386.h (ATTRIBUTE_ALIGNED_VALUE): Defined to 32
for IA MCU.
gcc/testsuite/
PR target/66818
* gcc.target/i386/pr66818.c: New test.
From-SVN: r225606
ix86_return_in_memory should check negative return from int_size_in_bytes,
similar to other ports.
gcc/
PR target/66817
* config/i386/i386.c (ix86_return_in_memory): Return true
if int_size_in_bytes returns negative for IA MCU.
gcc/testsuite/
PR target/66817
* gcc.target/i386/pr66817.c: New test.
From-SVN: r225605
2015-07-08 Kito Cheng <kito.cheng@gmail.com>
* function.c (stack_protect_epilogue): Use if rather than switch for
check targetm.have_stack_protect_test.
From-SVN: r225599
Provide a default in files where that is possible, so that everything
else there can be unconditionally compiled. However rtlanal.c and
reload.c do tricky things that break providing a global default, so we
can't do that yet.
gcc/ChangeLog:
2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (try_combine): Don't check if LOAD_EXTEND_OP is
defined.
(simplify_set): Likewise.
* cse.c (cse_insn): Likewise.
* fold-const.c (fold_single_bit_test): Likewise.
(fold_unary_loc): Likewise.
* postreload.c (reload_cse_simplify_set): Likewise.
(reload_cse_simplify_operands): Likewise.
From-SVN: r225591
* c-omp.c (c_omp_declare_simd_clauses_to_numbers): If all clauses
are to be removed, return NULL rather than original clauses list.
* decl.c (grokfndecl): Handle flag_openmp_simd like flag_openmp.
* pt.c (apply_late_template_attributes): Likewise.
* g++.dg/vect/vect.exp: Run also simd* tests.
* gcc.dg/vect/tree-vect.h (abort, exit): For C++ use extern "C".
(check_vect): Fix up get_cpuid call for C++.
* g++.dg/vect/simd-clone-1.cc: New test.
From-SVN: r225583
It is OK to include <adxintrin.h> for IA MCU since GCC can generate ADX
intrinsics with alternative instuctions if ADX isn't enabled.
PR target/66746
* config/i386/x86intrin.h: Include <adxintrin.h> even if
__iamcu__ is defined.
From-SVN: r225580
On x86, the "long double" type is platforma specific, which may be the
same as double or __float128. Since pr37870.c requires 80-bit floating
point type, it should be compiled with -mlong-double-80.
* gcc.target/i386/pr37870.c (dg-options): Add -mlong-double-80.
From-SVN: r225578
Vectors should be passed in memory for IAMCU. No warning for vector ABI
change for IAMCU since IAMCU ABI won't change.
gcc/
PR target/66806
* config/i386/i386.c (type_natural_mode): Don't warn vector ABI
change for IAMCU.
(function_arg_advance_32): Don't pass vectors in registers for
IAMCU.
(function_arg_32): Likewise.
(ix86_return_in_memory): Don't return vectors in registers for
IAMCU.
gcc/testsuite/
PR target/66806
* gcc.target/i386/pr66806.c: New test.
From-SVN: r225564
libtool: compile: [...]/build-gcc/./gcc/xg++ [...] -c [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp [...]
In file included from [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp:40:0:
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '192' from 'int' to 'char' inside { } [-Wnarrowing]
};
^
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '192' from 'int' to 'char' inside { } [-Wnarrowing]
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '164' from 'int' to 'char' inside { } [-Wnarrowing]
[many more]
liboffloadmic/
* plugin/Makefile.am (main_target_image.h): Change type of data
member in struct MainTargetImage to uint8_t.
* plugin/Makefile.in: Regenerate.
From-SVN: r225562
2015-07-08 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/66334
* ira-lives.c (process_bb_node_lives): Make conflicts with PIC
hard regno live at the start of BB with incoming abnormal edges.
* lra-lives.c (process_bb_lives): Ditto.
2015-07-08 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/66334
* gcc.target/i386/pr66334.c: New.
From-SVN: r225561
PR libgomp/65099
gcc/
* config/nvptx/mkoffload.c (main): Create an offload image only in
64-bit configurations.
libgomp/
* plugin/plugin-nvptx.c (nvptx_get_num_devices): Return 0 if not
in a 64-bit configuration.
* testsuite/libgomp.oacc-c++/c++.exp: Don't attempt nvidia
offloading testing if no such device is available.
* testsuite/libgomp.oacc-c/c.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.
From-SVN: r225560
