2013-03-22 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (struct mem_ref_locs): Remove.
(struct mem_ref): Make accesses_in_loop a vec of a vec of
aggregate mem_ref_loc.
(free_mem_ref_locs): Inline into ...
(memref_free): ... this and adjust.
(mem_ref_alloc): Adjust.
(mem_ref_locs_alloc): Remove.
(record_mem_ref_loc): Adjust.
(get_all_locs_in_loop): Rewrite into ...
(for_all_locs_in_loop): ... this iterator.
(rewrite_mem_ref_loc): New functor.
(rewrite_mem_refs): Use for_all_locs_in_loop.
(sm_set_flag_if_changed): New functor.
(execute_sm_if_changed_flag_set): Use for_all_locs_in_loop.
(ref_always_accessed): New functor.
(ref_always_accessed_p): Use for_all_locs_in_loop.
From-SVN: r196899
* config/i386/i386.md (*movdi_internal): Disparage slightly
all MMX moves to/from memory. Use Yi instead of x for SSE-MMX
conversion alternatives.
From-SVN: r196888
PR middle-end/48087
* diagnostic.def (DK_WERROR): New kind.
* diagnostic.h (werrorcount): Define.
* diagnostic.c (diagnostic_report_diagnostic): For DK_WARNING
promoted to DK_ERROR, increment DK_WERROR counter instead of
DK_ERROR counter.
* toplev.c (toplev_main): Call print_ignored_options even if
just werrorcount is non-zero. Exit with FATAL_EXIT_CODE
even if just werrorcount is non-zero.
* pt.c (convert_nontype_argument): Count werrorcount as warnings.
* call.c (build_temp): Likewise.
* method.c (synthesize_method): Likewise.
* typeck.c (convert_for_initialization): Likewise.
From-SVN: r196887
PR debug/55608
* dwarf2out.c (tree_add_const_value_attribute): Call ggc_free (array)
on failure.
(resolve_one_addr): Fail if referenced STRING_CST hasn't been written.
(string_cst_pool_decl): New function.
(optimize_one_addr_into_implicit_ptr): New function.
(resolve_addr_in_expr): Optimize DWARF location expression
DW_OP_addr DW_OP_stack_value where DW_OP_addr refers to some variable
which doesn't live in memory, but has DW_AT_location or
DW_AT_const_value, or refers to a string literal, into
DW_OP_GNU_implicit_pointer.
(optimize_location_into_implicit_ptr): New function.
(resolve_addr): If removing DW_AT_location of a variable because
it was DW_OP_addr of address of the variable, but the variable doesn't
live in memory, try to emit const value attribute for the initializer.
From-SVN: r196886
2013-03-21 Marc Glisse <marc.glisse@inria.fr>
gcc/
* tree.h (VECTOR_TYPE_P): New macro.
(VECTOR_INTEGER_TYPE_P, VECTOR_FLOAT_TYPE_P, FLOAT_TYPE_P,
TYPE_MODE): Use it.
* fold-const.c (fold_cond_expr_with_comparison): Use build_zero_cst.
VEC_COND_EXPR cannot be lvalues.
(fold_ternary_loc) <VEC_COND_EXPR>: Merge with the COND_EXPR case.
gcc/cp/
* call.c (build_conditional_expr_1): Fold VEC_COND_EXPR.
gcc/testsuite/
* g++.dg/ext/vector21.C: New testcase.
From-SVN: r196884
2013-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/39326
* tree-ssa-loop-im.c (UNANALYZABLE_MEM_ID): New define.
(MEM_ANALYZABLE): Adjust.
(record_mem_ref_loc): Move bitmap ops ...
(gather_mem_refs_stmt): ... here. Use the shared mem-ref for
unanalyzable refs, do not record locations for it.
(analyze_memory_references): Allocate ref zero as shared
unanalyzable ref.
(refs_independent_p): Do not test for unanalyzed mems here.
(ref_indep_loop_p_1): Special-case disambiguation against
the unanalyzed ref.
(ref_indep_loop_p): Assert we are not queried for the
unanalyzed mem.
From-SVN: r196878
2013-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/39326
* tree-ssa-loop-im.c (bb_loop_postorder): New global static.
(sort_bbs_in_loop_postorder_cmp): New function.
(gather_mem_refs_in_loops): Assign mem-ref IDs in loop
postorder.
From-SVN: r196874
2013-03-21 Richard Biener <rguenther@suse.de>
* tree-vect-data-refs.c (vect_update_interleaving_chain): Remove.
(vect_insert_into_interleaving_chain): Likewise.
(vect_drs_dependent_in_basic_block): Inline ...
(vect_slp_analyze_data_ref_dependence): ... here. New function,
split out from ...
(vect_analyze_data_ref_dependence): ... here. Simplify.
(vect_check_interleaving): Simplify.
(vect_analyze_data_ref_dependences): Likewise. Split out ...
(vect_slp_analyze_data_ref_dependences): ... this new function.
(dr_group_sort_cmp): New function.
(vect_analyze_data_ref_accesses): Compute data-reference groups
here instead of in vect_analyze_data_ref_dependence. Use
a more efficient algorithm.
* tree-vect-slp.c (vect_slp_analyze_bb_1): Use
vect_slp_analyze_data_ref_dependences. Call
vect_analyze_data_ref_accesses earlier.
* tree-vect-loop.c (vect_analyze_loop_2): Likewise.
* tree-vectorizer.h (vect_analyze_data_ref_dependences): Adjust.
(vect_slp_analyze_data_ref_dependences): New prototype.
* gcc.dg/vect/vect-outer-3a-big-array.c: Adjust.
* gcc.dg/vect/vect-outer-3a.c: Likewise.
From-SVN: r196872
2013-03-21 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (can_sm_ref_p): Do not test whether
ref is stored in the loop.
(find_refs_for_sm): Walk only over all stores.
(store_motion_loop): Allocate from lim_bitmap_obstack.
(store_motion): Likewise.
From-SVN: r196870
2013-03-21 Richard Biener <rguenther@suse.de>
* tree-cfg.c (verify_expr_no_block): New function.
(verify_expr_location_1): Verify that neither DECL_DEBUG_EXPR
nor DECL_VALUE_EXPR have locations with associated blocks.
* tree-ssa-live.c (clear_unused_block_pointer_1): Remove.
(clear_unused_block_pointer): Remove code dealing with
blocks in DECL_DEBUG_EXPR locations.
From-SVN: r196865
2013-03-21 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64-simd.md (simd_fabd): New Attribute.
(abd<mode>_3): New pattern.
(aba<mode>_3): New pattern.
(fabd<mode>_3): New pattern.
2013-03-21 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gcc.target/aarch64/vect.c: Test and result vector added
for sabd and saba instructions.
* gcc.target/aarch64/vect-compile.c: Check for sabd and saba
instructions in assembly.
* gcc.target/aarch64/vect.x: Add sabd and saba test functions.
* gcc.target/aarch64/vect-fp.c: Test and result vector added
for fabd instruction.
* gcc.target/aarch64/vect-fp-compile.c: Check for fabd
instruction in assembly.
* gcc.target/aarch64/vect-fp.x: Add fabd test function.
From-SVN: r196858
* tree-ssa-dom.c (record_equivalences_from_incoming_edge): Record
addititional equivalences for equality comparisons between an SSA_NAME
and a constant where the SSA_NAME was set from a widening conversion.
* g++.dg/tree-ssa/ssa-dom.C: New test.
From-SVN: r196855
* config/i386/i386.md (*movti_internal): Set prefix attribute to
maybe_vex for sselog1 and ssemov types.
(*movdi_internal): Reorder operand constraints.
(*movsi_internal): Ditto. Set prefix attribute to
maybe_vex for sselog1 and ssemov types.
(*movtf_internal): Set prefix attribute to maybe_vex
for sselog1 and ssemov types.
(*movdf_internal): Ditto. Set prefix_data16 attribute for
DImode ssemov types. Reorder operand constraints.
(*movsf_internal): Set type of alternatives 3,4 to imov. Set prefix
attribute to maybe_vex for sselog1 and ssemov types. Set prefix_data16
attribute for SImode ssemov types. Reorder operand constraints.
From-SVN: r196834
2013-03-20 Martin Jambor <mjambor@suse.cz>
* params.def (PARAM_IPA_CP_ARRAY_INDEX_HINT_BONUS): New parameter.
* ipa-cp.c (hint_time_bonus): Add abonus for known array indices.
From-SVN: r196832
[gcc]
2013-03-20 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/predicates.md (indexed_address, update_address_mem
update_indexed_address_mem): New predicates.
* config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"
attribute for load/store instructions.
* config/rs6000/dfp.md (movsd_store): Likewise.
(movsd_load): Likewise.
* config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.
(unnamed HI->DI extend define_insn): Likewise.
(unnamed SI->DI extend define_insn): Likewise.
(unnamed QI->SI extend define_insn): Likewise.
(unnamed QI->HI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(extendsfdf2_fpr): Likewise.
(movsi_internal1): Likewise.
(movsi_internal1_single): Likewise.
(movhi_internal): Likewise.
(movqi_internal): Likewise.
(movcc_internal1): Correct mnemonic for stw insn. Set correct "type"
attribute for load/store instructions.
(mov<mode>_hardfloat): Set correct "type" attribute for load/store
instructions.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat64): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(probe_stack_<mode>): Likewise.
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
floating point, and decimal floating point to reload iterator.
* config/rs6000/constraints.md (wl constraint): New constraints to
return FLOAT_REGS if certain options are used to reduce the number
of separate patterns that exist in the file.
(wx constraint): Likewise.
(wz constraint): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro,
define as 1 if we are running on a power7 or newer.
(enum r6000_reg_class_enum): Add new constraints.
* config/rs6000/dfp.md (movsd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7. Use xxlxor to create
0.0f.
(movsd splitter): Likewise.
(movsd_hardfloat): Likewise.
(movsd_softfloat): Likewise.
* config/rs6000/rs6000.md (FMOVE32): New iterators to combine
binary and decimal floating point moves.
(fmove_ok): New attributes to combine binary and decimal floating
point moves, and to combine power6x (mfpgpr) moves along normal
floating moves.
(real_value_to_target): Likewise.
(f32_lr): Likewise.
(f32_lm): Likewise.
(f32_li): Likewise.
(f32_sr): Likewise.
(f32_sm): Likewise.
(f32_si): Likewise.
(movsf): Combine binary and decimal floating point moves. Combine
power6x (mfpgpr) moves with other moves by using conditional
constraits (wg). Use LFIWZX and STFIWX for loading SDmode on
power7.
(mov<mode> for SFmode/SDmode); Likewise.
(SFmode/SDmode splitters): Likewise.
(movsf_hardfloat): Likewise.
(mov<mode>_hardfloat for SFmode/SDmode): Likewise.
(movsf_softfloat): Likewise.
(mov<mode>_softfloat for SFmode/SDmode): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl,
wx and wz constraints.
* config/rs6000/constraints.md (wg constraint): New constraint to
return FLOAT_REGS if -mmfpgpr (power6x) was used.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/dfp.md (movdd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7.
(movdd splitters): Likewise.
(movdd_hardfloat32): Likewise.
(movdd_softfloat32): Likewise.
(movdd_hardfloat64_mfpgpr): Likewise.
(movdd_hardfloat64): Likewise.
(movdd_softfloat64): Likewise.
* config/rs6000/rs6000.md (FMOVE64): New iterators to combine
64-bit binary and decimal floating point moves.
(FMOVE64X): Likewise.
(movdf): Combine 64-bit binary and decimal floating point moves.
Combine power6x (mfpgpr) moves with other moves by using
conditional constraits (wg).
(mov<mode> for DFmode/DDmode): Likewise.
(DFmode/DDmode splitters): Likewise.
(movdf_hardfloat32): Likewise.
(mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
(movdf_softfloat32): Likewise.
(movdf_hardfloat64_mfpgpr): Likewise.
(movdf_hardfloat64): Likewise.
(mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
(movdf_softfloat64): Likewise.
(mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
(reload_<mode>_load): Move to later in the file so they aren't in
the middle of the floating point move insns.
(reload_<mode>_store): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
constraint if -mdebug=reg.
(rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
-mfpgpr. Enable using dd reload support if needed.
* config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
binary and decimal floating point moves in rs6000.md.
(movtd_internal): Likewise.
* config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and
decimal floating point moves.
(movtf): Likewise.
(movtf_internal): Likewise.
(mov<mode>_internal, TDmode/TFmode): Likewise.
(movtf_softfloat): Likewise.
(mov<mode>_softfloat, TDmode/TFmode): Likewise.
* config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
movdi_internal64, using wg constraint for move direct operations.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
MODES_TIEABLE_P for selected modes. Print the numerical value of
the various virtual registers. Use GPR/FPR first/last values,
instead of hard coding the register numbers. Print which modes
have reload functions registered.
(rs6000_option_override_internal): If -mdebug=reg, trace the
options settings before/after setting cpu, target and subtarget
settings.
(rs6000_secondary_reload_trace): Improve the RTL dump for
-mdebug=addr and for secondary reload failures in
rs6000_secondary_reload_inner.
(rs6000_secondary_reload_fail): Likewise.
(rs6000_secondary_reload_inner): Likewise.
* config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
macros for first/last GPR and FPR registers.
(LAST_GPR_REGNO): Likewise.
(FIRST_FPR_REGNO): Likewise.
(LAST_FPR_REGNO): Likewise.
* config/rs6000/vector.md (mul<mode>3): Use the combined macro
VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
(vcond<mode><mode>): Likewise.
(vcondu<mode><mode>): Likewise.
(vector_gtu<mode>): Likewise.
(vector_gte<mode>): Likewise.
(xor<mode>3): Don't allow logical operations on TImode in 32-bit
to prevent the compiler from converting DImode operations to
TImode.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(nor<mode>3): Likewise.
(andc<mode>3): Likewise.
* config/rs6000/constraints.md (wt constraint): New constraint
that returns VSX_REGS if TImode is allowed in VSX registers.
* config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
constant under VSX.
* config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
similar to TImode, but it is restricted to being in the GPRs.
* config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
TImode to occupy a single VSX register.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
-mvsx-timode for power7/power8.
(power7 cpu): Likewise.
(power8 cpu): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
sure that TFmode/TDmode take up two registers if they are ever
allowed in the upper VSX registers.
(rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
registers.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_debug_reg_global): Add debugging for PTImode and wt
constraint. Print if LRA is turned on.
(rs6000_option_override_internal): Give an error if -mvsx-timode
and VSX is not enabled.
(invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If
-mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
to reg+offset addressing. Use PTImode when checking offset
addresses for validity.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_eliminate_indexed_memrefs): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit
reloads to fpr registers to continue to use reg+offset addressing,
but 64-bit reloads to altivec registers need reg+reg addressing.
Drop test for PRE_MODIFY, since VSX loads/stores no longer support
it. Treat LO_SUM like a PLUS operation.
(rs6000_secondary_reload_class): If type is 64-bit, prefer to use
FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
addressing.
(rs6000_cannot_change_mode_class): Do not allow TImode in VSX
registers to share a register with a smaller sized type, since VSX
puts scalars in the upper 64-bits.
(print_operand): Add support for PTImode.
(rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
registers, but don't have arithmetic support.
(rs6000_memory_move_cost): Add test for VSX.
(rs6000_opt_masks): Add -mvsx-timode.
* config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
for TImode.
(VSs): Likewise.
(VSr): Use wt constraint for TImode.
(VSv): Drop TImode support.
(vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
(vec_store_<mode>): Use VSX iterator instead of vector iterator.
(vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
one '?' on the appropriate output constraint. Do not allow TImode
logical operations on 32-bit systems.
(vsx_ior<mode>3): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_concat_<mode>): Likewise.
(vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.
* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
OPTION_MASK_VSX_TIMODE.
(enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(STACK_SAVEAREA_MODE): Use PTImode instead of TImode.
* config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
(TI2 iterator): New iterator for TImode, PTImode.
(wd mode attribute): Add values for vector types.
(movti_string): Replace TI move operations with operations for
TImode and PTImode. Add support for TImode being allowed in VSX
registers.
(mov<mode>_string, TImode/PTImode): Likewise.
(movti_ppc64): Likewise.
(mov<mode>_ppc64, TImode/PTImode): Likewise.
(TI mode splitters): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
constraint.
[gcc/testsuite]
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/mmfpgpr.c: New test.
* gcc.target/powerpc/sd-vsx.c: Likewise.
* gcc.target/powerpc/sd-pwr6.c: Likewise.
* gcc.target/powerpc/vsx-float0.c: Likewise.
From-SVN: r196831
2013-03-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/56661
* tree-ssa-sccvn.c (visit_use): Only value-number calls if
the result does not have to be distinct.
* gcc.dg/torture/pr56661.c: New testcase.
From-SVN: r196825
2013-03-20 Tobias Burnus <burnus@net-b.de>
* i-fortra.ads: Update comment, add Ada 2012's optional
Star and Kind data types for enhanced interoperability.
From-SVN: r196814
2013-03-20 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.c (struct variable_info): Add pointer
to the first field of an aggregate with sub-vars. Make
this and the pointer to the next subfield its ID.
(vi_next): New function.
(nothing_id, anything_id, readonly_id, escaped_id, nonlocal_id,
storedanything_id, integer_id): Increment by one.
(new_var_info, get_call_vi, lookup_call_clobber_vi,
get_call_clobber_vi): Adjust.
(solution_set_expand): Simplify and speedup.
(solution_set_add): Inline into ...
(set_union_with_increment): ... this. Adjust accordingly.
(do_sd_constraint): Likewise.
(do_ds_constraint): Likewise.
(do_complex_constraint): Simplify.
(build_pred_graph): Adjust.
(solve_graph): Likewise. Simplify and speedup.
(get_constraint_for_ssa_var, get_constraint_for_ptr_offset,
get_constraint_for_component_ref, get_constraint_for_1,
first_vi_for_offset, first_or_preceding_vi_for_offset,
create_function_info_for, create_variable_info_for_1,
create_variable_info_for, intra_create_variable_infos): Adjust.
(init_base_vars): Push NULL for ID zero.
(compute_points_to_sets): Adjust.
From-SVN: r196812
Jakub Jelinek
Kai Tietz
Richard Biener
Gabriel Dos Reis
GCC Administrator
Marc Glisse
Mark Wielaard
Uros Bizjak
Jakub Jelinek
Jason Merrill
Christophe Lyon
Christophe Lyon
Rainer Orth
Uros Bizjak
Naveen H.S
Jeff Law
Jason Merrill
Walter Lee
Robert Mason
Martin Jambor
Michael Meissner
Catherine Moore
Bill Schmidt
Tobias Burnus