PR rtl-optimization/81803
* lra-constraints.c (curr_insn_transform): Also reload the whole
register for a strict subreg no wider than a word if this is for
a WORD_REGISTER_OPERATIONS target.
From-SVN: r254488
2017-10-18 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/82556
* lra-constraints.c (curr_insn_transform): Use non-input operand
instead of output one for matched reload.
2017-10-18 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/82556
* gcc.target/i386/pr82556.c: New.
From-SVN: r253863
2017-04-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/70478
* lra-constraints.c (curr_small_class_check): New.
(update_and_check_small_class_inputs): New.
(process_alt_operands): Update curr_small_class_check. Disfavor
alternative insn memory operands. Check available regs for small
class operands.
From-SVN: r246808
2017-03-09 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/79949
* lra-constraints.c (process_alt_operands): Check memory when
trying to predict a cycle. Print about the overall increase.
From-SVN: r246003
2017-03-06 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/79571
* lra-constraints.c (process_alt_operands): Claculate static
reject and subtract it from overal when there will be only address
reloads.
2017-03-06 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/79571
* gcc.target/i386/pr79571.c: New.
From-SVN: r245928
PR rtl-optimization/79584
* lra-constraints.c (base_to_reg): Reload ad->base, the entire
base, not ad->base_term, the reg within base. Remove assertion
that ad->base == ad->base_term. Replace gen_int_mode using
bogus mode with const0_rtx.
From-SVN: r245741
2017-01-26 Vladimir Makarov <vmakarov@redhat.com>
PR target/79131
* lra-assigns.c (setup_live_pseudos_and_spill_after_risky): Take
endianess for subregs into account.
* lra-constraints.c (lra_constraints): Do risky transformations
always on the first iteration.
* lra-lives.c (check_pseudos_live_through_calls): Add arg
last_call_used_reg_set.
(process_bb_lives): Define and use last_call_used_reg_set.
* lra.c (lra): Always continue after lra_constraints on the first
iteration.
2017-01-26 Vladimir Makarov <vmakarov@redhat.com>
PR target/79131
* gcc.target/arm/pr79131.c: New.
From-SVN: r244942
PR rtl-optimization/79032
* lra-constraints.c (simplify_operand_subreg): In the MEM case, test
the alignment of the adjusted memory reference against that of MODE,
instead of the alignment of the original memory reference.
From-SVN: r244311
* lra-constraints.c (process_address): Add forward declaration.
(simplify_operand_subreg): In the MEM case, if the adjusted memory
reference is not sufficient aligned and the address was invalid,
reload the address before reloading the original memory reference.
Fix long lines and add a final return for the sake of clarity.
From-SVN: r243782
2016-11-30 Vladimir Makarov <vmakarov@redhat.com>
PR tree-optimization/77856
* lra-constraints.c (inherit_in_ebb): Check original regno for
invalid invariant regs too. Set only clobbered hard regs for the
invalid invariant regs.
2016-11-30 Vladimir Makarov <vmakarov@redhat.com>
PR tree-optimization/77856
* gcc.target/i386.c (pr77856.c): New.
From-SVN: r243038
* lra-constraints.c (check_and_process_move): Constrain the
range of DCLASS and SCLASS to avoid false positive out of bounds
array index warning.
From-SVN: r242993
2016-11-24 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/77541
* lra-constraints.c (struct input_reload): Add field match_p.
(get_reload_reg): Check modes of input reloads to generate unique
value reload pseudo.
(match_reload): Add input reload pseudo for the current insn.
2016-11-24 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/77541
* gcc.target/i386/pr77541.c: New.
From-SVN: r242848
PR rtl-optimization/78355
* doc/tm.texi.in (SLOW_UNALIGNED_ACCESS): Document that the macro only
needs to deal with unaligned accesses.
* doc/tm.texi: Regenerate.
* lra-constraints.c (simplify_operand_subreg): Only invoke
SLOW_UNALIGNED_ACCESS on innermode if the MEM is not aligned enough.
Co-Authored-By: Eric Botcazou <ebotcazou@adacore.com>
From-SVN: r242554
While changing LABEL_REF_LABEL it might as well become an inline
function, so that its clearer what types are involved. Unfortunately
because it is still possible to use XEXP and related macros on a
LABEL_REF rtx you can still set the field to be a non insn rtx. The
other unfortunate thing is that the generators actually create LABEL_REF
rtx that refer to MATCH_x rtx, so there we actually need to use XEXP to
bypass the checking this patch adds.
gcc/ChangeLog:
2016-10-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* rtl.h (label_ref_label): New function.
(set_label_ref_label): New function.
(LABEL_REF_LABEL): Delete.
* alias.c (rtx_equal_for_memref_p): Adjust.
* cfgbuild.c (make_edges): Likewise.
(purge_dead_tablejump_edges): Likewise.
* cfgexpand.c (convert_debug_memory_address): Likewise.
* cfgrtl.c (patch_jump_insn): Likewise.
* combine.c (distribute_notes): Likewise.
* cse.c (hash_rtx_cb): Likewise.
(exp_equiv_p): Likewise.
(fold_rtx): Likewise.
(check_for_label_ref): Likewise.
* cselib.c (rtx_equal_for_cselib_1): Likewise.
(cselib_hash_rtx): Likewise.
* emit-rtl.c (mark_label_nuses): Likewise.
* explow.c (convert_memory_address_addr_space_1): Likewise.
* final.c (output_asm_label): Likewise.
(output_addr_const): Likewise.
* gcse.c (add_label_notes): Likewise.
* genconfig.c (walk_insn_part): Likewise.
* genrecog.c (validate_pattern): Likewise.
* ifcvt.c (cond_exec_get_condition): Likewise.
(noce_emit_store_flag): Likewise.
(noce_get_alt_condition): Likewise.
(noce_get_condition): Likewise.
* jump.c (maybe_propagate_label_ref): Likewise.
(mark_jump_label_1): Likewise.
(redirect_exp_1): Likewise.
(rtx_renumbered_equal_p): Likewise.
* lra-constraints.c (operands_match_p): Likewise.
* print-rtl.c (print_value): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (set_label_offsets): Likewise.
* reorg.c (get_branch_condition): Likewise.
* rtl-tests.c (test_uncond_jump): Likewise.
* rtl.c (rtx_equal_p_cb): Likewise.
(rtx_equal_p): Likewise.
* rtlanal.c (reg_mentioned_p): Likewise.
(rtx_referenced_p): Likewise.
(get_condition): Likewise.
* varasm.c (const_hash_1): Likewise.
(compare_constant): Likewise.
(const_rtx_hash_1): Likewise.
(output_constant_pool_1): Likewise.
From-SVN: r241401
gcc/
PR rtl-optimization/77289
* lra-constraints.c (get_final_hard_regno): Add support for non hard
register numbers. Remove support for subregs.
(get_hard_regno): Use SUBREG_P. Don't call get_final_hard_regno().
(get_reg_class): Delete removed get_final_hard_regno() argument.
(uses_hard_regs_p): Call get_final_hard_regno().
gcc/testsuite/
PR rtl-optimization/77289
* gcc.target/powerpc/pr77289.c: New test.
From-SVN: r240065
In the PR we have a PARALLEL of a move and a compare (a "mr." instruction).
The compare is dead, so single_set on it returns just the move. Then,
simple_move_p returns true; but the instruction does need reloads in this
case. This patch solves this by making simple_move_p return false for
every multiple_sets instruction.
PR rtl-optimization/73650
* lra-constraints.c (simple_move_p): If the insn is multiple_sets
it is not a simple move.
From-SVN: r239483
pr71680.c -m64 -O1 -mlra, ira output showing two problem insns.
(insn 7 5 26 3 (set (reg:SI 159 [ a ])
(mem/c:SI (reg/f:DI 158) [1 a+0 S4 A8])) pr71680.c:13 464 {*movsi_internal1}
(expr_list:REG_EQUIV (mem/c:SI (reg/f:DI 158) [1 a+0 S4 A8])
(nil)))
(insn 26 7 27 3 (set (reg:DI 162)
(unspec:DI [
(fix:SI (subreg:SF (reg:SI 159 [ a ]) 0))
] UNSPEC_FCTIWZ)) pr71680.c:13 372 {fctiwz_sf}
(expr_list:REG_DEAD (reg:SI 159 [ a ])
(nil)))
Insn 26 requires that reg 159 be of class FLOAT_REGS.
first lra action:
deleting insn with uid = 7.
Changing pseudo 159 in operand 1 of insn 26 on equiv [r158:DI]
Creating newreg=164, assigning class ALL_REGS to subreg reg r164
26: r162:DI=unspec[fix(r164:SI#0)] 7
REG_DEAD r159:SI
Inserting subreg reload before:
30: r164:SI=[r158:DI]
[snip]
Change to class FLOAT_REGS for r164
Well, that didn't do much. lra tried the equiv mem, found that didn't
work, and had to reload. Effectively getting back to the two original
insns but r159 replaced with r164. simplify_operand_subreg did not do
anything in this case because SLOW_UNALIGNED_ACCESS was true (wrongly
for power8, but that's beside the point). So now we have, using
abbreviated rtl notation:
r164:SI=[r158:DI]
r162:DI=unspec[fix(r164:SI)]
The problem here is that the first insn isn't valid, due to the rs6000
backend not supporting SImode in fprs, and r164 must be an fpr to make
the second insn valid.
next lra action:
Creating newreg=165 from oldreg=164, assigning class GENERAL_REGS to r165
30: r165:SI=[r158:DI]
Inserting insn reload after:
31: r164:SI=r165:SI
so now we have
r165:SI=[r158:DI]
r164:SI=r165:SI
r162:DI=unspec[fix(r164:SI)]
This ought to be good on power8, except for one little thing.
r165 is GENERAL_REGS so the first insn is good, a gpr load from mem.
r164 is FLOAT_REGS, making the last insn good, a fctiwz.
The second insn ought to be a sldi, mtvsrd, xscvspdpn combination, but
that is only supported for SFmode. So lra continue on reloading the
second insn, but in vain because it never tries anything other than
SImode and as noted above, SImode is not valid in fprs.
What this patch does is arrange to emit the two reloads needed for the
SLOW_UNALIGNED_ACCESS case at once, moving the subreg to the second
insn in order to switch modes, producing:
r164:SI=[r158:DI]
r165:SF=r164:SI#0
r162:DI=unspec[fix(r165:SF)]
I've also tidied a couple of other things:
1) "old" is unnecessary as it duplicated "operand".
2) Rejecting mem subregs due to SLOW_UNALIGNED_ACCESS only makes sense
if the original mode was not slow.
PR target/71680
* lra-constraints.c (simplify_operand_subreg): Allow subreg
mode for mem when SLOW_UNALIGNED_ACCESS if inner mode is also
slow. Emit two reloads for slow mem case, first loading in
fast innermode, then converting to required mode.
testsuite/
* gcc.target/powerpc/pr71680.c: New.
From-SVN: r239342
2016-08-05 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/69847
* lra-constraints.c (process_invariant_for_inheritance): Save
pattern instead of src.
(remove_inheritance_pseudos): Use the pattern. Add assert.
From-SVN: r239180
2016-08-02 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/69847
* lra-int.h (struct lra-reg): Use restore_rtx instead of
restore_regno.
(lra_rtx_hash): New.
* lra.c (initialize_lra_reg_info_element): Use restore_rtx instead
of restore_regno.
(lra_rtx_hash): Rename and move lra-remat.c::rtx_hash.
* lra-remat.c (rtx_hash): Rename and Move to lra.c.
* lra-spills.c (lra_final_code_change): Don't delete insn when the
next insn is USE with the same reg as the current insn source.
* lra-constraints.c (curr_insn_transform): Use restore_rtx instead
of restore_regno.
(lra_constraints_init): Call initiate_invariants.
(lra_constraints_finish): Call finish_invariants.
(struct invariant, invariant_t, invariant_ptr_t): New.
(const_invariant_ptr_t, invariants, invariants_pool): New.
(invariant_table, invariant_hash, invariant_eq_p): New.
(insert_invariant, initiate_invariants, finish_invariants): New.
(clear_invariants, invalid_invariant_regs): New.
(inherit_reload_reg, split_reg, fix_bb_live_info): Use restore_rtx
instead of restore_regno.
(invariant_p, process_invariant_for_inheritance): New.
(inherit_in_ebb): Implement invariant inheritance.
(lra_inheritance): Initialize and finalize invalid_invariant_regs.
(remove_inheritance_pseudos): Implement undoing invariant
inheritance.
(undo_optional_reloads, lra_undo_inheritance): Use restore_rtx
instead of restore_regno.
* lra-assigns.c (regno_live_length): New.
(reload_pseudo_compare_func): Use regno_live_length.
(assign_by_spills): Use restore_rtx instead of restore_regno.
(lra_assign): Ditto. Initiate regno_live_length.
From-SVN: r238991
2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
PR rtl-optimization/71878
* lra-constraints.c (match_reload): Pass information about other
output operands. Create new unique register value if matching input
operand shares same register value as output operand being considered.
(curr_insn_transform): Record output operands already processed.
From-SVN: r238346
2016-04-18 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/70689
* lra-constraints.c (equiv_substition_p): New.
(process_alt_operands): Use it.
(swap_operands): Swap it.
(curr_insn_transform): Update it.
2016-04-18 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/70689
* testsuite/gcc.target/i386/pr70689.c: New.
From-SVN: r235184
2016-04-06 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/70398
* lra-constraints.c (process_address_1): Check zero scale and code
for reloading with zero scale.
2016-04-06 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/70398
* testsuite/gcc.target/aarch64/pr70398.c: New.
From-SVN: r234792
PR rtl-optimization/70278
* lra-constraints.c (split_reg): Handle the case where biggest_mode is
VOIDmode.
testsuite/
* gcc.dg/torture/pr70278.c: New test.
* gcc.target/arm/pr70278.c: New test.
From-SVN: r234342
PR target/70083
* lra-lives.c (process_bb_lives): Also update biggest mode for hard
regs.
(lra_create_live_ranges_1): initialize hard register biggest_mode to
VOIDmode.
* lra-constraints.c (split_reg): For hard regs, try to find the
biggest single-register mode used in the function.
testsuite/
PR target/70083
* gcc.dg/torture/pr70083.c: New test.
* gcc.target/i386/pr70083.c: New test.
From-SVN: r234184
Eric Botcazou
Vladimir Makarov
Alan Modra
Matthew Fortune
Jakub Jelinek
Martin Liska
Jakub Jelinek
Jeff Law
Pip Cet
Trevor Saunders
Thomas Preud'homme
Bernd Edlinger
Peter Bergner
Segher Boessenkool
Jiong Wang
Bernd Schmidt