2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-05-15 Martin Liska <mliska@suse.cz>
PR driver/31468
* gcc.c (process_command): Do not allow empty argument of -o option.
From-SVN: r249546
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-05-02 Martin Liska <mliska@suse.cz>
* doc/gcov.texi: Add missing preposition.
* gcov.c (function_info::function_info): Properly fill up
all member variables.
From-SVN: r249545
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-04-28 Martin Liska <mliska@suse.cz>
* doc/gcov.texi: Enhance documentation of gcov.
From-SVN: r249543
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-04-28 Martin Liska <mliska@suse.cz>
PR gcov-profile/53915
* gcov.c (format_gcov): Print 'NAN %' when top > bottom.
From-SVN: r249541
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-04-28 Martin Liska <mliska@suse.cz>
PR driver/56469
* coverage.c (coverage_remove_note_file): New function.
* coverage.h: Declare the function.
* toplev.c (finalize): Clean if an error has been seen.
From-SVN: r249540
PR target/81151
* config/i386/sse.md (round<mode>2): Renumber match_dup and
operands indexes to avoid gap between operands and match_dups.
From-SVN: r249484
PR c++/81130
* gimplify.c (omp_add_variable): Don't force GOVD_SEEN for types
with ctors/dtors if GOVD_SHARED is set.
* testsuite/libgomp.c++/pr81130.C: New test.
From-SVN: r249482
Backported from mainline
2017-06-20 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/81125
* ubsan.h (ubsan_encode_value): Workaround buggy clang++ parser
by removing enum keyword.
(ubsan_type_descriptor): Likewise. Formatting fix.
2017-06-19 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/81125
* ubsan.h (enum ubsan_encode_value_phase): New.
(ubsan_encode_value): Change second argument to
enum ubsan_encode_value_phase with default value of
UBSAN_ENCODE_VALUE_GENERIC.
* ubsan.c (ubsan_encode_value): Change second argument to
enum ubsan_encode_value_phase PHASE from bool IN_EXPAND_P,
adjust uses, for UBSAN_ENCODE_VALUE_GENERIC use just
create_tmp_var_raw instead of create_tmp_var and use a
TARGET_EXPR.
(ubsan_expand_bounds_ifn, ubsan_build_overflow_builtin,
instrument_bool_enum_load, ubsan_instrument_float_cast): Adjust
ubsan_encode_value callers.
PR sanitizer/81111
* ubsan.c (ubsan_encode_value): If current_function_decl is NULL,
use create_tmp_var_raw instead of create_tmp_var, mark it addressable
just by setting TREE_ADDRESSABLE on the result and use a TARGET_EXPR.
PR sanitizer/81125
* g++.dg/ubsan/pr81125.C: New test.
PR sanitizer/81111
* g++.dg/ubsan/pr81111.C: New test.
From-SVN: r249480
gcc/
PR target/71778
* config/arm/arm-builtins.c (arm_expand_builtin_args): Return TARGET
if given a non-constant argument for an intrinsic which requires a
constant.
gcc/testsuite/
PR target/71778
* gcc.target/arm/pr71778.c: New.
From-SVN: r249379
* config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3.
(MASK_FEATURES): New macro.
* config/sparc/sparc.c (sparc_option_override): Remove the special
handling of -mfpu and generalize it to all MASK_FEATURES switches.
From-SVN: r249190
Backport from mainline
2017-06-02 David Edelsohn <dje.gcc@gmail.com>
* dwarf2out.c (DWARF_INITIAL_LENGTH_SIZE_STR): New.
(dl_section_ref): New.
(dwarf2out_finish): Copy debug_line_section_label to dl_section_ref.
On AIX, append an expression to subtract the size of the
section length to dl_section_ref.
From-SVN: r249014
2017-06-07 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-05-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/80549
* tree-cfgcleanup.c (mfb_keep_latches): New helper.
(cleanup_tree_cfg_noloop): Create forwarders to known loop
headers if they do not have a preheader.
* gcc.dg/torture/pr80549.c: New testcase.
2017-05-19 Richard Biener <rguenther@suse.de>
PR c++/80593
* c-warn.c (strict_aliasing_warning): Do not warn for accesses
to alias-set zero memory.
* g++.dg/warn/Wstrict-aliasing-bogus-char-2.C: New testcase.
* g++.dg/warn/Wstrict-aliasing-6.C: Adjust expected outcome.
2017-05-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/80842
* tree-ssa-ccp.c (set_lattice_value): Always meet with the old
value.
* gcc.dg/torture/pr80842.c: New testcase.
2017-05-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/80906
* graphite-isl-ast-to-gimple.c (copy_loop_close_phi_nodes): Get
and pass through iv_map.
(copy_bb_and_scalar_dependences): Adjust.
(translate_pending_phi_nodes): Likewise.
(copy_loop_close_phi_args): Handle code-generating IVs instead
of ICEing.
* gcc.dg/graphite/pr80906.c: New testcase.
2017-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/80705
* tree-vect-data-refs.c (vect_analyze_data_refs): DECL_NONALIASED
bases are not vectorizable.
* gcc.dg/vect/bb-slp-pr80705.c: New testcase.
From-SVN: r248970
Back port from mainline
[gcc]
2017-05-19 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Prefer
VSX registers over GPRs, particularly on ISA 2.07 which does not
have the MTVSRDD instruction.
[gcc/testsuite]
2017-05-19 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* gcc.target/powerpc/pr80718.c: New test.
From-SVN: r248936
2017-05-31 Martin Jambor <mjambor@suse.cz>
Backport from mainline
2017-04-24 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/80293
* tree-sra.c (scalarizable_type_p): New parameter const_decl, make
char arrays not totally scalarizable if it is false.
(analyze_all_variable_accesses): Pass correct value in the new
parameter. Add a statistics counter.
testsuite/
* g++.dg/tree-ssa/pr80293.C: New test.
From-SVN: r248724
HOST_WIDE_INT may not be long as assumed in print_operand and
xtensa_emit_call. Use HOST_WIDE_INT_PRINT_DEC/HOST_WIDE_INT_PRINT_HEX
format strings instead of %ld/0x%lx. This fixes incorrect assembly code
generation by the compiler running on armhf host.
2017-05-30 Max Filippov <jcmvbkbc@gmail.com>
gcc/
Backport from mainline
2017-05-29 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.c (xtensa_emit_call): Use
HOST_WIDE_INT_PRINT_HEX instead of 0x%lx format string.
(print_operand): Use HOST_WIDE_INT_PRINT_DEC instead of %ld
format string.
From-SVN: r248720
Backported from mainline
2017-05-24 Sheldon Lobo <smlobo@sheldon.us.oracle.com>
* config/sparc/sparc.md (length): Return the correct value for -mflat
sibcalls to match output_sibcall.
From-SVN: r248523
PR sanitizer/80875
* fold-const.c (fold_binary_loc) <case MULT_EXPR>: Check if OP1
can be negated.
* c-c++-common/ubsan/pr80875.c: New test.
From-SVN: r248490
Backported from mainline
2017-05-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/80809
* omp-low.c (finish_taskreg_remap): New function.
(finish_taskreg_scan): If unit size of ctx->record_type
is non-constant, unshare the size expression and replace
decls in it with possible outer var refs.
* testsuite/libgomp.c/pr80809-2.c: New test.
* testsuite/libgomp.c/pr80809-3.c: New test.
From-SVN: r248488
Backported from mainline
2017-05-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/80809
* gimplify.c (omp_add_variable): For GOVD_DEBUG_PRIVATE use
GOVD_SHARED rather than GOVD_PRIVATE with it.
(gimplify_adjust_omp_clauses_1, gimplify_adjust_omp_clauses): Expect
GOVD_SHARED rather than GOVD_PRIVATE with GOVD_DEBUG_PRIVATE.
* testsuite/libgomp.c/pr80809-1.c: New test.
From-SVN: r248487
Backported from mainline
2017-05-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/80853
* omp-low.c (lower_reduction_clauses): Pass OMP_CLAUSE_PRIVATE
as last argument to build_outer_var_ref for pointer bases of array
section reductions.
* testsuite/libgomp.c/pr80853.c: New test.
From-SVN: r248486
[gcc]
2017-05-25 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from trunk
2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* config/rs6000/predicates.md (simple_offsettable_mem_operand):
New predicate.
* config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
(define_peephole2 for Altivec d-form load): Add peepholes to catch
cases where the register allocator uses a move and an offsettable
memory operation to/from a FPR register on ISA 2.06/2.07.
(define_peephole2 for Altivec d-form store): Likewise.
Backport from trunk
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
are now unused after splitting mov{sf,sd}_hardfloat.
(f32_lr2): Likewise.
(f32_lm): Likewise.
(f32_lm2): Likewise.
(f32_li): Likewise.
(f32_li2): Likewise.
(f32_lv): Likewise.
(f32_sr): Likewise.
(f32_sr2): Likewise.
(f32_sm): Likewise.
(f32_sm2): Likewise.
(f32_si): Likewise.
(f32_si2): Likewise.
(f32_sv): Likewise.
(f32_dm): Likewise.
(f32_vsx): Likewise.
(f32_av): Likewise.
(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
For movsf, order stores so the VSX stores occur before the GPR
store which encourages the register allocator to use a traditional
FPR instead of a GPR. For movsd, order the stores so that the GPR
store comes before the VSX stores to allow the power6 to work.
This is due to the power6 not having a 32-bit integer store
instruction from a FPR.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
[gcc/testsuite]
2017-05-25 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from trunk
2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* gcc.target/powerpc/pr80510-1.c: New test.
* gcc.target/powerpc/pr80510-2.c: Likewise.
Backport from trunk
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* gcc.target/powerpc/pr68163.c: New test.
From-SVN: r248480
When lra-remat rematerializes an instruction with a clobber, it checks
that the clobber does not kill live registers. However it fails to check
that the clobber also doesn't overlap with the destination register of the
final rematerialized instruction. As a result it is possible to generate
illegal instructions with the same hard register as the destination and a
clobber. Fix this by also checking for overlaps with the destination
register.
Backport from mainline
PR rtl-optimization/80754
* lra-remat.c (do_remat): Add overlap checks for dst_regno.
From-SVN: r248463
Backport from mainline
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
Backport from mainline
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* gcc.target/sparc/niagara7-align.c: New test.
From-SVN: r248380
[gcc]
2017-05-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2017-05-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_vect_nonmem): New static var.
(rs6000_init_cost): Initialize rs6000_vect_nonmem.
(rs6000_add_stmt_cost): Update rs6000_vect_nonmem.
(rs6000_finish_cost): Avoid vectorizing simple copy loops with
VF=2 that require versioning.
[gcc/testsuite]
2017-05-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2017-05-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/versioned-copy-loop.c: New file.
From-SVN: r248010
[gcc]
2017-05-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2017-05-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (altivec_init_builtins): Define POWER8
built-ins for vec_xl and vec_xst with short and char pointer
arguments.
[gcc/testsuite]
2017-05-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2017-05-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/p8-vec-xl-xst.c: New file.
From-SVN: r247999
[gcc]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from mainline
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79038
PR target/79202
PR target/79203
* config/rs6000/rs6000.md (u code attribute): Add FIX and
UNSIGNED_FIX.
(extendsi<mode>2): Add support for doing sign extension via
VUPKHSW and XXPERMDI if the value is in Altivec registers and we
don't have ISA 3.0 instructions.
(extendsi<mode>2 splitter): Likewise.
(fix_trunc<mode>si2): If we are at ISA 2.07 (VSX small integer),
generate the normal insns since SImode can now go in vector
registers. Disallow the special UNSPECs needed for previous
machines to hide SImode being used. Add new insns
fctiw{,w}_<mode>_smallint if SImode can go in vector registers.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fixuns_trunc<mode>si2): Likewise.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fctiw<u>z_<mode>_smallint): Likewise.
(fctiw<u>z_<mode>_mem): New combiner pattern to prevent conversion
of floating point to 32-bit integer from doing a direct move to
the GPR registers to do a store.
(fctiwz_<mode>): Break long line.
[gcc/testsuite]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from mainline
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79038
PR target/79202
PR target/79203
* gcc.target/powerpc/ppc-round3.c: New test.
* gcc.target/powerpc/ppc-round2.c: Update expected code.
From-SVN: r247820
Martin Liska
Jakub Jelinek
James Greenhalgh
Andreas Schwab
Alexander Monakov
Eric Botcazou
David S. Miller
Uros Bizjak
David Edelsohn
Richard Biener
Michael Meissner
Volker Reichelt
Prakhar Bahuguna
Martin Jambor
Max Filippov
Andreas Krebbel
Uros Bizjak
Sheldon Lobo
Marek Polacek
Wilco Dijkstra
Sheldon Lobo
Bill Schmidt
John David Anglin