The recent patch to convert all thumb1 code in libgcc to unified syntax
ommitted the conditional code that is used only when building the library
for minimal size. This patch fixes this case.
I've also fixed the COND macro so that a single definition is always used
that is for unified syntax. This eliminates a warning that is now being
seen from the assembler when compiling the ieee fp support code.
PR target/94220
* config/arm/lib1funcs.asm (COND): Use a single definition for
unified syntax.
(aeabi_uidivmod): Unified syntax when optimizing Thumb for size.
(aeabi_idivmod): Likewise.
(divsi3_skip_div0_test): Likewise.
This patch adds a new multilib for armv8.1-m.main+mve with hard float abi. For
armv8.1-m.main+mve soft and softfp, the v8-M multilibs will be reused.
The following mappings are also updated:
"-mfloat-abi=hard -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/hard"
"-mfloat-abi=softfp -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/softfp"
"-mfloat-abi=soft -march=armv8.1-m.main+mve.fp -> armv8-m.main/nofp"
gcc/ChangeLog:
2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
* config/arm/t-rmprofile: create new multilib for
armv8.1-m.main+mve hard float and reuse v8-m.main ones for
v8.1-m.main+mve .
gcc/testsuite/ChangeLog:
2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
* gcc.target/arm/multilib.exp: Add new v8.1-M entry.
libgcc/ChangLog:
2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
* config/arm/t-arm: Do not compile cmse_nonsecure_call.S for v8.1-m.
Unified syntax has been the official syntax for thumb1 assembly for
over 10 years now. It's time we made preparations for that becoming
the default in the assembler. But before we can start doing that we
really need to clean up some laggards from the olden days. Libgcc
support for thumb1 is one such example.
This patch converts all of the legacy (disjoint) syntax that I could
find over to unified code. The identification was done by using a
trick version of gas that defaulted to unified mode which then faults
if legacy syntax is encountered. The code produced was then compared
against the old code to check for differences. One such difference
does exist, but that is because in unified syntax 'movs rd, rn' is
encoded as 'lsls rd, rn, #0', rather than 'adds rd, rn, #0'; but that
is a deliberate change that was introduced because the lsls encoding
more closely reflects the behaviour of 'movs' in arm state (where only
some of the condition flags are modified).
* config/arm/bpabi-v6m.S (aeabi_lcmp): Convert thumb1 code to unified
syntax.
(aeabi_ulcmp, aeabi_ldivmod, aeabi_uldivmod): Likewise.
(aeabi_frsub, aeabi_cfcmpeq, aeabi_fcmpeq): Likewise.
(aeabi_fcmp, aeabi_drsub, aeabi_cdrcmple): Likewise.
(aeabi_cdcmpeq, aeabi_dcmpeq, aeabi_dcmp): Likewise.
* config/arm/lib1funcs.S (Lend_fde): Convert thumb1 code to unified
syntax.
(divsi3, modsi3): Likewise.
(clzdi2, ctzsi2): Likewise.
* config/arm/libunwind.S (restore_core_regs): Convert thumb1 code to
unified syntax.
(UNWIND_WRAPPER): Likewise.
As the following testcase shows, unwind.h on ARM can't be (starting with GCC
10) compiled with -std=c* modes, only -std=gnu* modes.
The problem is it uses asm keyword, which isn't a keyword in those modes
(system headers vs. non-system ones don't make a difference here).
glibc and other installed headers use __asm or __asm__ keywords instead that
work fine in both standard and gnu modes.
While there, as it is an installed header, I think it is also wrong to
completely ignore any identifier namespace rules.
The generic unwind.h defines just _Unwind* namespace identifiers plus
_sleb128_t/_uleb128_t (but e.g. unlike libstdc++/glibc headers doesn't
uglify operand names), the ARM unwind.h is much worse here. I've just
changed the gnu_Unwind_Find_got function at least not be in user identifier
namespace, but perhaps it would be good to go further and rename e.g.
or e.g.
typedef _Unwind_Reason_Code (*personality_routine) (_Unwind_State,
_Unwind_Control_Block *, _Unwind_Context *);
in unwind-arm-common.h.
2020-02-07 Jakub Jelinek <jakub@redhat.com>
PR target/93615
* config/arm/unwind-arm.h (gnu_Unwind_Find_got): Rename to ...
(_Unwind_gnu_Find_got): ... this. Use __asm instead of asm. Remove
trailing :s in asm. Formatting fixes.
(_Unwind_decode_typeinfo_ptr): Adjust caller.
* gcc.dg/pr93615.c: New test.
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture.
Code to detect whether cmse.c can be buit with -mcmse checks the output
of host GCC when invoked with -mcmse. However, an error from the
compiler does not prevent some minimal output so this always holds true.
2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/t-arm: Check return value of gcc rather than lack of
output.
2019-11-13 Jerome Lambourg <lambourg@adacore.com>
Doug Rupp <rupp@adacore.com>
Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc: Collapse the arm-vxworks entries into
a single arm-wrs-vxworks7* one, bpabi based. Update
the default cpu from arm8 to armv7-a
* config/arm/vxworks.h (CC1_SPEC): Simplify, knowing that
we always use ARM_UNWIND_INFO.
(DWARF2_UNWIND_INFO): Remove redefinition.
(ARM_TARGET2_DWARF_FORMAT): Likewise.
(VXWORKS_PERSONALITY): Define, to "llvm".
(VXWORKS_EXTRA_LIBS_RTP): Define, to "-lllvm".
libgcc/
* config.host: Collapse the arm-vxworks entries into
a single arm-wrs-vxworks7* one.
* config/arm/unwind-arm-vxworks.c: Update comments. Provide
__gnu_Unwind_Find_exidx and a weak dummy __cxa_type_match for
kernel modules, to be overriden by libstdc++ when we link with
it. Rely on externally provided __exidx_start/end.
Co-Authored-By: Doug Rupp <rupp@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>
From-SVN: r278253
This is causing regressions when mixing with user code compiled in ARM mode.
2019-09-20 Christophe Lyon <christophe.lyon@st.com>
Revert:
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
architecture.
From-SVN: r276001
Without this, when we are unwinding across a signal frame we can jump
to an even address which leads to an exception.
This is needed in __gnu_persnality_sigframe_fdpic() when restoring the
PC from the signal frame since the PC saved by the kernel has the LSB
bit set to zero.
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
libgcc/
* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
architecture.
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
From-SVN: r275575
The main difference with existing support is that function addresses
are function descriptor addresses instead. This means that all code
dealing with function pointers now has to cope with function
descriptors instead.
For the same reason, Linux kernel helpers can no longer be called by
dereferencing their address, so we implement wrappers that directly
call the kernel helpers.
When restoring a function address, we also have to restore the FDPIC
register value (r9).
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
gcc/
* ginclude/unwind-arm-common.h (unwinder_cache): Add reserved5
field.
libgcc/
* config/arm/linux-atomic.c (__kernel_cmpxchg): Add FDPIC support.
(__kernel_dmb): Likewise.
(__fdpic_cmpxchg): New function.
(__fdpic_dmb): New function.
* config/arm/unwind-arm.h (FDPIC_REGNUM): New define.
(gnu_Unwind_Find_got): New function.
(_Unwind_decode_typeinfo_ptr): Add FDPIC support.
* unwind-arm-common.inc (UCB_PR_GOT): New.
(funcdesc_t): New struct.
(get_eit_entry): Add FDPIC support.
(unwind_phase2): Likewise.
(unwind_phase2_forced): Likewise.
(__gnu_Unwind_RaiseException): Likewise.
(__gnu_Unwind_Resume): Likewise.
(__gnu_Unwind_Backtrace): Likewise.
* unwind-pe.h (read_encoded_value_with_base): Likewise.
libstdc++/
* libsupc++/eh_personality.cc (get_ttype_entry): Add FDPIC
support.
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
From-SVN: r275568
At present it is possible to call the CMSE functions for checking
addresses (such as cmse_check_address_range) and forget to check/use
the return value. This patch makes the interfaces more robust against
programmer error by marking these functions with the warn_unused_result
attribute. With this set, any use of these functions that does not use
the result will produce a warning.
This produces a warning on default warn levels when the result of the
cmse functions is not used.
For the following function:
void foo()
{
int *data;
cmse_check_address_range((int*)data, 0, 0);
}
The following warning is emitted:
warning: ignoring return value of 'cmse_check_address_range' declared
with attribute 'warn_unused_result' [-Wunused-result]
6 | cmse_check_address_range((int*)data, 0, 0);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
gcc/ChangeLog:
2019-07-31 Joel Hutton <Joel.Hutton@arm.com>
* config/arm/arm_cmse.h (cmse_nonsecure_caller): Add
warn_unused_result attribute.
(cmse_check_address_range): Add warn_unused_result attribute.
libgcc/ChangeLog:
2019-07-31 Joel Hutton <Joel.Hutton@arm.com>
* config/arm/cmse.c (cmse_check_address_range): Add
warn_unused_result attribute.
2019-07-31 Joel Hutton <Joel.Hutton@arm.com>
* gcc.target/arm/cmse/cmse-17.c: New test.
From-SVN: r273924
This is a roll-up of a set of changes needed to support the Arm EABI on NetBSD.
2019-06-14 Matt Thomas <matt@3am-software.com>
Matthew Green <mrg@eterna.com.au>
Nick Hudson <skrll@netbsd.org>
Maya Rashish <coypu@sdf.org>
Richard Earnshaw <rearnsha@arm.com>
gcc:
* config.gcc (arm*-*-netbsdelf*) Add support for EABI configuration.
* config.host (arm*-*-netbsd*): Use driver-arm.o on native NetBSD.
* config/arm/netbsd-eabi.h: New file.
* config/arm/netbsd-elf.h (TARGET_OS_CPP_BUILTINS): Undefine before
redefining.
(SUBTARGET_EXTRA_ASM_SPEC): Don't pass -matpcs to the assembler.
* config/netbsd-elf.h (NETBSD_LINK_LD_ELF_SO_SPEC): New define.
(NETBSD_SUBTARGET_EXTRA_SPECS): New define.
(SUBTARGET_EXTRA_SPECS): Define to NETBSD_SUBTARGET_EXTRA_SPECS.
libatomic:
* configure.tgt (arm*): Handle NetBSD in the same way as FreeBSD.
libgcc:
* config.host (arm*-*-netbsdelf*): Add support for EABI configurations.
* config/arm/t-netbsd (LIB1ASMFUNCS): Add some additional assembler
functions to build.
* config/arm/t-netbsd-eabi: New file.
Co-Authored-By: Matthew Green <mrg@eterna.com.au>
Co-Authored-By: Maya Rashish <coypu@sdf.org>
Co-Authored-By: Nick Hudson <skrll@netbsd.org>
Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>
From-SVN: r272290
Softfloat single precision and double precision floating-point
multiplication routines in libgcc share some code with the
floating-point division of their corresponding precision. As the code
is structured now, this leads to *all* division code being pulled in an
executable in softfloat mode even if only multiplication is
performed.
This patch create some new LIB1ASMFUNCS macros to also build files with
just the multiplication and shared code as weak symbols. By putting
these earlier in the static library, they can then be picked up when
only multiplication is used and they are overriden by the global
definition in the existing file containing both multiplication and
division code when division is needed.
The patch also removes changes made to the FUNC_START and ARM_FUNC_START
macros in r218124 since the intent was to put multiplication and
division code into their own section in a later patch to achieve the
same size optimization. That approach relied on specific section layout
to ensure multiplication and division were not too far from the shared
bit of code in order to the branches to be within range. Due to lack of
guarantee regarding section layout, in particular with all the
possibility of linker scripts, this approach was chosen instead. This
patch keeps the two testcases that were posted by Tony Wang on the mailing
list to implement this approach and adds a new one.
2018-12-19 Thomas Preud'homme <thomas.preudhomme@linaro.org>
libgcc/
* /config/arm/lib1funcs.S (FUNC_START): Remove unused sp_section
parameter and corresponding code.
(ARM_FUNC_START): Likewise in both definitions.
Also update footer comment about condition that need to match with
gcc/config/arm/elf.h to also include libgcc/config/arm/t-arm.
* config/arm/ieee754-df.S (muldf3): Also build it if L_arm_muldf3 is
defined. Weakly define it in this case.
* config/arm/ieee754-sf.S (mulsf3): Likewise with L_arm_mulsf3.
* config/arm/t-elf (LIB1ASMFUNCS): Build _arm_muldf3.o and
_arm_mulsf3.o before muldiv versions if targeting Thumb-1 only. Add
comment to keep condition in sync with the one in
libgcc/config/arm/lib1funcs.S and gcc/config/arm/elf.h.
gcc/
* config/arm/elf.h: Update comment about condition that need to
match with libgcc/config/arm/lib1funcs.S to also include
libgcc/config/arm/t-arm.
* doc/sourcebuild.texi (output-exists, output-exists-not): Rename
subsubsection these directives are in to "Check for output files".
Move scan-symbol to that section and add to it new scan-symbol-not
directive.
2018-12-19 Tony Wang <tony.wang@arm.com>
Thomas Preud'homme <thomas.preudhomme@linaro.org>
gcc/testsuite/
* lib/lto.exp (lto-execute): Define output_file and testname_with_flags
to same value as execname.
(scan-symbol): Move and rename to ...
* lib/gcc-dg.exp (scan-symbol-common): This. Adapt into a
helper function returning true or false if a symbol is present.
(scan-symbol): New procedure.
(scan-symbol-not): Likewise.
* gcc.target/arm/size-optimization-ieee-1.c: New testcase.
* gcc.target/arm/size-optimization-ieee-2.c: Likewise.
* gcc.target/arm/size-optimization-ieee-3.c: Likewise.
From-SVN: r267282
The AArch32 instruction sets prior to Armv7 do not define the ISB and
DSB instructions that are needed to form a speculation barrier. While
I do not know of any instances of cores based on those instruction
sets being vulnerable to speculative side channel attacks it is
possible to run code built for those ISAs on more recent hardware
where they would become vulnerable.
This patch works around this by using a library call added to libgcc.
That code can then take any platform-specific actions necessary to
ensure safety.
For the moment I've only handled two cases: the library code being
built for armv7 or later anyway and running on Linux.
On Linux we can handle this by calling the kernel function that will
flush a small amount of cache. Such a sequence ends with a ISB+DSB
sequence if running on an Armv7 or later CPU.
gcc:
PR target/86951
* config/arm/arm-protos.h (arm_emit_speculation_barrier): New
prototype.
* config/arm/arm.c (speculation_barrier_libfunc): New static
variable.
(arm_init_libfuncs): Initialize it.
(arm_emit_speculation_barrier): New function.
* config/arm/arm.md (speculation_barrier): Call
arm_emit_speculation_barrier for architectures that do not have
DSB or ISB.
(speculation_barrier_insn): Only match on Armv7 or later.
libgcc:
PR target/86951
* config/arm/lib1funcs.asm (speculation_barrier): New function.
* config/arm/t-arm (LIB1ASMFUNCS): Add it to list of functions
to build.
From-SVN: r263806
The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.
A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.
References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.
* config/arm/arm-cpus.in (armv5, armv5e): Delete features.
(armv5t, armv5te): New features.
(ARMv5, ARMv5e): Delete fgroups.
(ARMv5t, ARMv5te): Adjust for above changes.
(ARMv6m): Likewise.
(armv5, armv5e): Delete arches.
* config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
arm_arch5.
(*call_reg_arm): Likewise.
(*call_value_reg_armv5): Likewise.
(*call_value_reg_arm): Likewise.
(*call_symbol): Likewise.
(*call_value_symbol): Likewise.
(*sibcall_insn): Likewise.
(*sibcall_value_insn): Likewise.
(clzsi2): Likewise.
(prefetch): Likewise.
(define_split and define_peephole2 dependent on arm_arch5):
Likewise.
* config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
arm_arch5e.
(TARGET_ARM_QBIT): Likewise.
(TARGET_DSP_MULTIPLY): Likewise.
(enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
(arm_arch5, arm_arch5e): Delete.
(arm_arch5t, arm_arch5te): Declare.
* config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
(arm_arch5t): Declare.
(arm_option_reconfigure_globals): Update for the above.
(arm_options_perform_arch_sanity_checks): Update comment, replace
use of arm_arch5 with arm_arch5t.
(use_return_insn): Likewise.
(arm_emit_call_insn): Likewise.
(output_return_instruction): Likewise.
(arm_final_prescan_insn): Likewise.
(arm_coproc_builtin_available): Likewise.
* config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
arm_arch5e with arm_arch5t and arm_arch5te.
* config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
(arm_arch5t, arm_arch5te): Declare.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/t-arm-elf: Remove references to armv5, armv5e.
* config/arm/t-multilib: Likewise.
* config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
instead of arm_arch5.
(*call_reg_thumb1): Likewise.
(*call_value_reg_thumb1_v5): Likewise.
(*call_value_reg_thumb1): Likewise.
* config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
unreachable path.
* doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.
* gcc.target/arm/pr40887.c: Update comment.
* lib/target-supports.exp: Don't generate effective target checks
and related helpers for armv5. Update comment.
* gcc.target/arm/armv5_thumb_isa.c: Delete.
* gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
target check and options.
* config/arm/libunwind.S: Update comment relating to armv5.
From-SVN: r260362
2017-08-01 Jerome Lambourg <lambourg@adacore.com>
Doug Rupp <rupp@adacore.com>
Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as
well as arm-wrs-vxworks. Update target_cpu_name from arm6 (arch v3) to
arm8 (arch v4).
* config/arm/vxworks.h (MAYBE_TARGET_BPABI_CPP_BUILTINS): New, helper
for TARGET_OS_CPP_BUILTIN.
(TARGET_OS_CPP_BUILTIN): Invoke MAYBE_TARGET_BPABI_CPP_BUILTINS(),
refine CPU definitions for arm_arch5 and add those for arm_arch6 and
arm_arch7.
(MAYBE_ASM_ABI_SPEC): New, helper for SUBTARGET_EXTRA_ASM_SPEC,
passing required abi options to the assembler for EABI configurations.
(EXTRA_CC1_SPEC): New macro, to help prevent the implicit production
of .text.hot and .text.unlikely sections for kernel modules when
using ARM style exceptions.
(CC1_SPEC): Remove obsolete attempt at mimicking Diab toolchain
options. Add EXTRA_CC1_SPEC.
(VXWORKS_ENDIAN_SPEC): Adjust comment and remove handling of Diab
toolchain options.
(DWARF2_UNWIND_INFO): Redefine to handle the pre/post VxWorks 7
transition.
(ARM_TARGET2_DWARF_FORMAT): Define.
* config/arm/t-vxworks: Adjust multilib control to removal of the
Diab command line options.
libgcc/
* config.host (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7
as well as arm-wrs-vxworks.
* config/arm/t-vxworks7: New file. Add unwind-arm-vxworks.c to
LIB2ADDEH.
* config/arm/unwind-arm-vxworks.c: New file. Provide dummy
__exidx_start and __exidx_end for downloadable modules.
Co-Authored-By: Doug Rupp <rupp@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>
From-SVN: r250781
This file is missing a .fpu directive and was relying on the compiler
driver passing through a -mfpu= command line option. When the FPU is
auto, that will not be passed through correctly, so set something
suitable within the file itself.
libgcc:
* config/arm/cmse_nonsecure_call.S: Explicitly set the FPU.
From-SVN: r249297
2017-05-17 Andreas Tobler <andreast@gcc.gnu.org>
* config/arm/unwind-arm.h: Make _Unwind_GetIP, _Unwind_GetIPInfo and
_Unwind_SetIP available as functions for arm*-*-freebsd*.
* config/arm/unwind-arm.c: Implement the above.
From-SVN: r248173
libgcc/
* config/arm/fp16.c (struct format): New.
(binary32): New.
(__gnu_float2h_internal): New. Body moved from
__gnu_f2h_internal and generalize.
(_gnu_f2h_internal): Move body to function __gnu_float2h_internal.
Call it with binary32.
Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com>
From-SVN: r242781
For Aurelien Jarno <aurelien@aurel32.net>
On ARM soft-float, the float to double conversion doesn't convert a sNaN
to qNaN as the IEEE Std 754 standard mandates:
"Under default exception handling, any operation signaling an invalid
operation exception and for which a floating-point result is to be
delivered shall deliver a quiet NaN."
Given the soft float ARM code ignores exceptions and always provides a
result, a float to double conversion of a signaling NaN should return a
quiet NaN. Fix this in extendsfdf2.
gcc/ChangeLog:
PR target/59833
* config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN.
gcc/testsuite/ChangeLog:
* gcc.dg/pr59833.c: New testcase.
From-SVN: r238584
2016-07-11 Hale Wang <hale.wang@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/lib1funcs.S: Add new wrapper.
Co-Authored-By: Andre Vieira <andre.simoesdiasvieira@arm.com>
From-SVN: r238215
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-arches.def (armv8-m.base): Define new architecture.
(armv8-m.main): Likewise.
(armv8-m.main+dsp): Likewise.
* config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define.
(FL_FOR_ARCH8M_MAIN): Likewise.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and
armv8-m.main+dsp to BE8_LINK_SPEC.
* config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M.
(enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN.
* config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M
Baseline and Mainline.
(arm_option_override_internal): Also disable arm_restrict_it when
!arm_arch_notm. Update comment for -munaligned-access to also cover
ARMv8-M Baseline.
(arm_file_start): Increase buffer size for printing architecture name.
* doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main
and armv8-m.main+dsp.
(mno-unaligned-access): Clarify that this is disabled by default for
ARMv8-M Baseline architectures as well.
gcc/testsuite/
* lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and
check_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and
ARMv8-M Mainline architectures.
libgcc/
* config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M.
From-SVN: r238081
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
libgcc/
* config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later
and ARMv5t* rather than for a fixed list of architectures.
From-SVN: r238080
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to
decide whether to prevent some libgcc routines being included for some
multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the
link between this condition and the one in
libgcc/config/arm/lib1func.S.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_arm_cortex_m): Use
__ARM_ARCH_ISA_ARM to test for Cortex-M devices.
libgcc/
* config/arm/bpabi-v6m.S: Clarify what architectures is the
implementation suitable for.
* config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases
for all Thumb-1 only targets.
(NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets.
(THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than
__ARM_ARCH_6M__.
(EQUIV): Likewise.
(ARM_FUNC_ALIAS): Likewise.
(umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv
version.
(modsi3): Likewise.
(clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__.
(clzdi2): Likewise.
(ctzsi2): Likewise.
(L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than
__ARM_ARCH_6M__ in guard for checking whether it is defined.
(final includes): Test for NOT_ISA_TARGET_32BIT rather than
__ARM_ARCH_6M__ and add comment to indicate the connection between
this condition and the one in gcc/config/arm/elf.h.
* config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and
__ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.
* config/arm/t-softfp: Likewise.
From-SVN: r238079
2015-02-17 Sandra Loosemore <sandra@codesourcery.com>
libgcc/
* config/arm/bpabi.S (test_div_by_zero): Make label names
consistent between thumb2 and arm mode cases. Separate the
signed comparison on the high word of the numerator from the
unsigned comparison on the low word.
* config/arm/bpabi-v6m.S (test_div_by_zero): Similarly separate
signed comparison.
gcc/testsuite/
* gcc.target/arm/divzero.c: New test case.
From-SVN: r220765
2014-11-27 Tony Wang <tony.wang@arm.com>
libgcc/
* config/arm/lib1funcs.S (FUNC_START): Add conditional section
redefine for macro L_arm_muldivsf3 and L_arm_muldivdf3.
(SYM_END, ARM_SYM_START): Add macros used to expose function Symbols.
From-SVN: r218124
