4aa157e8d2
158988 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Richard Sandiford
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4aa157e8d2 |
Allow single-element interleaving for non-power-of-2 strides
This allows LD3 to be used for isolated a[i * 3] accesses, in a similar way to the current a[i * 2] and a[i * 4] for LD2 and LD4 respectively. Given the problems with the cost model underestimating the cost of elementwise accesses, the patch continues to reject the VMAT_ELEMENTWISE cases that are currently rejected. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * tree-vect-data-refs.c (vect_analyze_group_access_1): Allow single-element interleaving even if the size is not a power of 2. * tree-vect-stmts.c (get_load_store_type): Disallow elementwise accesses for single-element interleaving if the group size is not a power of 2. gcc/testsuite/ * gcc.target/aarch64/sve/struct_vect_18.c: New test. * gcc.target/aarch64/sve/struct_vect_18_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_19.c: Likewise. * gcc.target/aarch64/sve/struct_vect_19_run.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256634 |
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Richard Sandiford
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bb6c2b68d6 |
Add support for conditional reductions using SVE CLASTB
This patch uses SVE CLASTB to optimise conditional reductions. It means
that we no longer need to maintain a separate index vector to record
the most recent valid value, and no longer need to worry about overflow
cases.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (fold_extract_last_@var{m}): Document.
* doc/sourcebuild.texi (vect_fold_extract_last): Likewise.
* optabs.def (fold_extract_last_optab): New optab.
* internal-fn.def (FOLD_EXTRACT_LAST): New internal function.
* internal-fn.c (fold_extract_direct): New macro.
(expand_fold_extract_optab_fn): Likewise.
(direct_fold_extract_optab_supported_p): Likewise.
* tree-vectorizer.h (EXTRACT_LAST_REDUCTION): New vect_reduction_type.
* tree-vect-loop.c (vect_model_reduction_cost): Handle
EXTRACT_LAST_REDUCTION.
(get_initial_def_for_reduction): Do not create an initial vector
for EXTRACT_LAST_REDUCTION reductions.
(vectorizable_reduction): Leave the scalar phi in place for
EXTRACT_LAST_REDUCTIONs. Try using EXTRACT_LAST_REDUCTION
ahead of INTEGER_INDUC_COND_REDUCTION. Do not check for an
epilogue code for EXTRACT_LAST_REDUCTION and defer the
transform phase to vectorizable_condition.
* tree-vect-stmts.c (vect_finish_stmt_generation_1): New function,
split out from...
(vect_finish_stmt_generation): ...here.
(vect_finish_replace_stmt): New function.
(vectorizable_condition): Handle EXTRACT_LAST_REDUCTION.
* config/aarch64/aarch64-sve.md (fold_extract_last_<mode>): New
pattern.
* config/aarch64/aarch64.md (UNSPEC_CLASTB): New unspec.
gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_vect_fold_extract_last): New proc.
* gcc.dg/vect/pr65947-1.c: Update dump messages. Add markup
for fold_extract_last.
* gcc.dg/vect/pr65947-2.c: Likewise.
* gcc.dg/vect/pr65947-3.c: Likewise.
* gcc.dg/vect/pr65947-4.c: Likewise.
* gcc.dg/vect/pr65947-5.c: Likewise.
* gcc.dg/vect/pr65947-6.c: Likewise.
* gcc.dg/vect/pr65947-9.c: Likewise.
* gcc.dg/vect/pr65947-10.c: Likewise.
* gcc.dg/vect/pr65947-12.c: Likewise.
* gcc.dg/vect/pr65947-14.c: Likewise.
* gcc.dg/vect/pr80631-1.c: Likewise.
* gcc.target/aarch64/sve/clastb_1.c: New test.
* gcc.target/aarch64/sve/clastb_1_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_2.c: Likewise.
* gcc.target/aarch64/sve/clastb_2_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_3.c: Likewise.
* gcc.target/aarch64/sve/clastb_3_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_4.c: Likewise.
* gcc.target/aarch64/sve/clastb_4_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_5.c: Likewise.
* gcc.target/aarch64/sve/clastb_5_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_6.c: Likewise.
* gcc.target/aarch64/sve/clastb_6_run.c: Likewise.
* gcc.target/aarch64/sve/clastb_7.c: Likewise.
* gcc.target/aarch64/sve/clastb_7_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256633
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Richard Sandiford
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bfe1bb57ba |
Add support for vectorising live-out values using SVE LASTB
This patch uses the SVE LASTB instruction to optimise cases in which
a value produced by the final scalar iteration of a vectorised loop is
live outside the loop. Previously this situation would stop us from
using a fully-masked loop.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (extract_last_@var{m}): Document.
* optabs.def (extract_last_optab): New optab.
* internal-fn.def (EXTRACT_LAST): New internal function.
* internal-fn.c (cond_unary_direct): New macro.
(expand_cond_unary_optab_fn): Likewise.
(direct_cond_unary_optab_supported_p): Likewise.
* tree-vect-loop.c (vectorizable_live_operation): Allow fully-masked
loops using EXTRACT_LAST.
* config/aarch64/aarch64-sve.md (aarch64_sve_lastb<mode>): Rename to...
(extract_last_<mode>): ...this optab.
(vec_extract<mode><Vel>): Update accordingly.
gcc/testsuite/
* gcc.target/aarch64/sve/live_1.c: New test.
* gcc.target/aarch64/sve/live_1_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256632
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Richard Sandiford
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76a34e3f85 |
Add an empty_mask_is_expensive hook
This patch adds a hook to control whether we avoid executing masked (predicated) stores when the mask is all false. We don't want to do that by default for SVE. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * target.def (empty_mask_is_expensive): New hook. * doc/tm.texi.in (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): New hook. * doc/tm.texi: Regenerate. * targhooks.h (default_empty_mask_is_expensive): Declare. * targhooks.c (default_empty_mask_is_expensive): New function. * tree-vectorizer.c (vectorize_loops): Only call optimize_mask_stores if the target says that empty masks are expensive. * config/aarch64/aarch64.c (aarch64_empty_mask_is_expensive): New function. (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Redefine. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256631 |
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Richard Sandiford
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535e7c114a |
Handle peeling for alignment with masking
This patch adds support for aligning vectors by using a partial first iteration. E.g. if the start pointer is 3 elements beyond an aligned address, the first iteration will have a mask in which the first three elements are false. On SVE, the optimisation is only useful for vector-length-specific code. Vector-length-agnostic code doesn't try to align vectors since the vector length might not be a power of 2. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * tree-vectorizer.h (_loop_vec_info::mask_skip_niters): New field. (LOOP_VINFO_MASK_SKIP_NITERS): New macro. (vect_use_loop_mask_for_alignment_p): New function. (vect_prepare_for_masked_peels, vect_gen_while_not): Declare. * tree-vect-loop-manip.c (vect_set_loop_masks_directly): Add an niters_skip argument. Make sure that the first niters_skip elements of the first iteration are inactive. (vect_set_loop_condition_masked): Handle LOOP_VINFO_MASK_SKIP_NITERS. Update call to vect_set_loop_masks_directly. (get_misalign_in_elems): New function, split out from... (vect_gen_prolog_loop_niters): ...here. (vect_update_init_of_dr): Take a code argument that specifies whether the adjustment should be added or subtracted. (vect_update_init_of_drs): Likewise. (vect_prepare_for_masked_peels): New function. (vect_do_peeling): Skip prologue peeling if we're using a mask instead. Update call to vect_update_inits_of_drs. * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize mask_skip_niters. (vect_analyze_loop_2): Allow fully-masked loops with peeling for alignment. Do not include the number of peeled iterations in the minimum threshold in that case. (vectorizable_induction): Adjust the start value down by LOOP_VINFO_MASK_SKIP_NITERS iterations. (vect_transform_loop): Call vect_prepare_for_masked_peels. Take the number of skipped iterations into account when calculating the loop bounds. * tree-vect-stmts.c (vect_gen_while_not): New function. gcc/testsuite/ * gcc.target/aarch64/sve/nopeel_1.c: New test. * gcc.target/aarch64/sve/peel_ind_1.c: Likewise. * gcc.target/aarch64/sve/peel_ind_1_run.c: Likewise. * gcc.target/aarch64/sve/peel_ind_2.c: Likewise. * gcc.target/aarch64/sve/peel_ind_2_run.c: Likewise. * gcc.target/aarch64/sve/peel_ind_3.c: Likewise. * gcc.target/aarch64/sve/peel_ind_3_run.c: Likewise. * gcc.target/aarch64/sve/peel_ind_4.c: Likewise. * gcc.target/aarch64/sve/peel_ind_4_run.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256630 |
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Richard Sandiford
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c2700f7466 |
Allow the number of iterations to be smaller than VF
Fully-masked loops can be profitable even if the iteration count is smaller than the vectorisation factor. In this case we're effectively doing a complete unroll followed by SLP. The documentation for min-vect-loop-bound says that the default value was 0, but actually the default and minimum were 1. We need it to be 0 for this case since the parameter counts a whole number of vector iterations. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * doc/sourcebuild.texi (vect_fully_masked): Document. * params.def (PARAM_MIN_VECT_LOOP_BOUND): Change minimum and default value to 0. * tree-vect-loop.c (vect_analyze_loop_costing): New function, split out from... (vect_analyze_loop_2): ...here. Don't check the vectorization factor against the number of loop iterations if the loop is fully-masked. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_vect_fully_masked): New proc. * gcc.dg/vect/slp-3.c: Expect all loops to be vectorized if vect_fully_masked. * gcc.target/aarch64/sve/loop_add_4.c: New test. * gcc.target/aarch64/sve/loop_add_4_run.c: Likewise. * gcc.target/aarch64/sve/loop_add_5.c: Likewise. * gcc.target/aarch64/sve/loop_add_5_run.c: Likewise. * gcc.target/aarch64/sve/miniloop_1.c: Likewise. * gcc.target/aarch64/sve/miniloop_2.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256629 |
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Richard Sandiford
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8277ddf9ee |
Make ivopts handle calls to internal functions
ivopts previously treated pointer arguments to internal functions like IFN_MASK_LOAD and IFN_MASK_STORE as normal gimple values. This patch makes it treat them as addresses instead. This makes a significant difference to the code quality for SVE loops, since we can then use loads and stores with scaled indices. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * tree-ssa-loop-ivopts.c (USE_ADDRESS): Split into... (USE_REF_ADDRESS, USE_PTR_ADDRESS): ...these new use types. (dump_groups): Update accordingly. (iv_use::mem_type): New member variable. (address_p): New function. (record_use): Add a mem_type argument and initialize the new mem_type field. (record_group_use): Add a mem_type argument. Use address_p. Remove obsolete null checks of base_object. Update call to record_use. (find_interesting_uses_op): Update call to record_group_use. (find_interesting_uses_cond): Likewise. (find_interesting_uses_address): Likewise. (get_mem_type_for_internal_fn): New function. (find_address_like_use): Likewise. (find_interesting_uses_stmt): Try find_address_like_use before calling find_interesting_uses_op. (addr_offset_valid_p): Use the iv mem_type field as the type of the addressed memory. (add_autoinc_candidates): Likewise. (get_address_cost): Likewise. (split_small_address_groups_p): Use address_p. (split_address_groups): Likewise. (add_iv_candidate_for_use): Likewise. (autoinc_possible_for_pair): Likewise. (rewrite_groups): Likewise. (get_use_type): Check for USE_REF_ADDRESS instead of USE_ADDRESS. (determine_group_iv_cost): Update after split of USE_ADDRESS. (get_alias_ptr_type_for_ptr_address): New function. (rewrite_use_address): Rewrite address uses in calls that were identified by find_address_like_use. gcc/testsuite/ * gcc.dg/tree-ssa/scev-9.c: Expected REFERENCE ADDRESS instead of just ADDRESS. * gcc.dg/tree-ssa/scev-10.c: Likewise. * gcc.dg/tree-ssa/scev-11.c: Likewise. * gcc.dg/tree-ssa/scev-12.c: Likewise. * gcc.target/aarch64/sve/index_offset_1.c: New test. * gcc.target/aarch64/sve/index_offset_1_run.c: Likewise. * gcc.target/aarch64/sve/loop_add_2.c: Likewise. * gcc.target/aarch64/sve/loop_add_3.c: Likewise. * gcc.target/aarch64/sve/while_1.c: Check for indexed addressing modes. * gcc.target/aarch64/sve/while_2.c: Likewise. * gcc.target/aarch64/sve/while_3.c: Likewise. * gcc.target/aarch64/sve/while_4.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256628 |
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Richard Sandiford
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65dd134602 |
Allow ADDR_EXPRs of TARGET_MEM_REFs
This patch allows ADDR_EXPR <TARGET_MEM_REF ...>, which is useful when calling internal functions that take pointers to memory that is conditionally loaded or stored. This is a prerequisite to the following ivopts patch. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * expr.c (expand_expr_addr_expr_1): Handle ADDR_EXPRs of TARGET_MEM_REFs. * gimple-expr.h (is_gimple_addressable: Likewise. * gimple-expr.c (is_gimple_address): Likewise. * internal-fn.c (expand_call_mem_ref): New function. (expand_mask_load_optab_fn): Use it. (expand_mask_store_optab_fn): Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256627 |
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Richard Sandiford
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0972596e6d |
Add support for reductions in fully-masked loops
This patch removes the restriction that fully-masked loops cannot
have reductions. The key thing here is to make sure that the
reduction accumulator doesn't include any values associated with
inactive lanes; the patch adds a bunch of conditional binary
operations for doing that.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (cond_add@var{mode}, cond_sub@var{mode})
(cond_and@var{mode}, cond_ior@var{mode}, cond_xor@var{mode})
(cond_smin@var{mode}, cond_smax@var{mode}, cond_umin@var{mode})
(cond_umax@var{mode}): Document.
* optabs.def (cond_add_optab, cond_sub_optab, cond_and_optab)
(cond_ior_optab, cond_xor_optab, cond_smin_optab, cond_smax_optab)
(cond_umin_optab, cond_umax_optab): New optabs.
* internal-fn.def (COND_ADD, COND_SUB, COND_MIN, COND_MAX, COND_AND)
(COND_IOR, COND_XOR): New internal functions.
* internal-fn.h (get_conditional_internal_fn): Declare.
* internal-fn.c (cond_binary_direct): New macro.
(expand_cond_binary_optab_fn): Likewise.
(direct_cond_binary_optab_supported_p): Likewise.
(get_conditional_internal_fn): New function.
* tree-vect-loop.c (vectorizable_reduction): Handle fully-masked loops.
Cope with reduction statements that are vectorized as calls rather
than assignments.
* config/aarch64/aarch64-sve.md (cond_<optab><mode>): New insns.
* config/aarch64/iterators.md (UNSPEC_COND_ADD, UNSPEC_COND_SUB)
(UNSPEC_COND_SMAX, UNSPEC_COND_UMAX, UNSPEC_COND_SMIN)
(UNSPEC_COND_UMIN, UNSPEC_COND_AND, UNSPEC_COND_ORR)
(UNSPEC_COND_EOR): New unspecs.
(optab): Add mappings for them.
(SVE_COND_INT_OP, SVE_COND_FP_OP): New int iterators.
(sve_int_op, sve_fp_op): New int attributes.
gcc/testsuite/
* gcc.dg/vect/pr60482.c: Remove XFAIL for variable-length vectors.
* gcc.target/aarch64/sve/reduc_1.c: Expect the loop operations
to be predicated.
* gcc.target/aarch64/sve/slp_5.c: Check for a fully-masked loop.
* gcc.target/aarch64/sve/slp_7.c: Likewise.
* gcc.target/aarch64/sve/reduc_5.c: New test.
* gcc.target/aarch64/sve/slp_13.c: Likewise.
* gcc.target/aarch64/sve/slp_13_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256626
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Richard Sandiford
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7cfb4d9359 |
Add support for fully-predicated loops
This patch adds support for using a single fully-predicated loop instead
of a vector loop and a scalar tail. An SVE WHILELO instruction generates
the predicate for each iteration of the loop, given the current scalar
iv value and the loop bound. This operation is wrapped up in a new internal
function called WHILE_ULT. E.g.:
WHILE_ULT (0, 3, { 0, 0, 0, 0}) -> { 1, 1, 1, 0 }
WHILE_ULT (UINT_MAX - 1, UINT_MAX, { 0, 0, 0, 0 }) -> { 1, 0, 0, 0 }
The third WHILE_ULT argument is needed to make the operation
unambiguous: without it, WHILE_ULT (0, 3) for one vector type would
seem equivalent to WHILE_ULT (0, 3) for another, even if the types have
different numbers of elements.
Note that the patch uses "mask" and "fully-masked" instead of
"predicate" and "fully-predicated", to follow existing GCC terminology.
This patch just handles the simple cases, punting for things like
reductions and live-out values. Later patches remove most of these
restrictions.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* optabs.def (while_ult_optab): New optab.
* doc/md.texi (while_ult@var{m}@var{n}): Document.
* internal-fn.def (WHILE_ULT): New internal function.
* internal-fn.h (direct_internal_fn_supported_p): New override
that takes two types as argument.
* internal-fn.c (while_direct): New macro.
(expand_while_optab_fn): New function.
(convert_optab_supported_p): Likewise.
(direct_while_optab_supported_p): New macro.
* wide-int.h (wi::udiv_ceil): New function.
* tree-vectorizer.h (rgroup_masks): New structure.
(vec_loop_masks): New typedef.
(_loop_vec_info): Add masks, mask_compare_type, can_fully_mask_p
and fully_masked_p.
(LOOP_VINFO_CAN_FULLY_MASK_P, LOOP_VINFO_FULLY_MASKED_P)
(LOOP_VINFO_MASKS, LOOP_VINFO_MASK_COMPARE_TYPE): New macros.
(vect_max_vf): New function.
(slpeel_make_loop_iterate_ntimes): Delete.
(vect_set_loop_condition, vect_get_loop_mask_type, vect_gen_while)
(vect_halve_mask_nunits, vect_double_mask_nunits): Declare.
(vect_record_loop_mask, vect_get_loop_mask): Likewise.
* tree-vect-loop-manip.c: Include tree-ssa-loop-niter.h,
internal-fn.h, stor-layout.h and optabs-query.h.
(vect_set_loop_mask): New function.
(add_preheader_seq): Likewise.
(add_header_seq): Likewise.
(interleave_supported_p): Likewise.
(vect_maybe_permute_loop_masks): Likewise.
(vect_set_loop_masks_directly): Likewise.
(vect_set_loop_condition_masked): Likewise.
(vect_set_loop_condition_unmasked): New function, split out from
slpeel_make_loop_iterate_ntimes.
(slpeel_make_loop_iterate_ntimes): Rename to..
(vect_set_loop_condition): ...this. Use vect_set_loop_condition_masked
for fully-masked loops and vect_set_loop_condition_unmasked otherwise.
(vect_do_peeling): Update call accordingly.
(vect_gen_vector_loop_niters): Use VF as the step for fully-masked
loops.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
mask_compare_type, can_fully_mask_p and fully_masked_p.
(release_vec_loop_masks): New function.
(_loop_vec_info): Use it to free the loop masks.
(can_produce_all_loop_masks_p): New function.
(vect_get_max_nscalars_per_iter): Likewise.
(vect_verify_full_masking): Likewise.
(vect_analyze_loop_2): Save LOOP_VINFO_CAN_FULLY_MASK_P around
retries, and free the mask rgroups before retrying. Check loop-wide
reasons for disallowing fully-masked loops. Make the final decision
about whether use a fully-masked loop or not.
(vect_estimate_min_profitable_iters): Do not assume that peeling
for the number of iterations will be needed for fully-masked loops.
(vectorizable_reduction): Disable fully-masked loops.
(vectorizable_live_operation): Likewise.
(vect_halve_mask_nunits): New function.
(vect_double_mask_nunits): Likewise.
(vect_record_loop_mask): Likewise.
(vect_get_loop_mask): Likewise.
(vect_transform_loop): Handle the case in which the final loop
iteration might handle a partial vector. Call vect_set_loop_condition
instead of slpeel_make_loop_iterate_ntimes.
* tree-vect-stmts.c: Include tree-ssa-loop-niter.h and gimple-fold.h.
(check_load_store_masking): New function.
(prepare_load_store_mask): Likewise.
(vectorizable_store): Handle fully-masked loops.
(vectorizable_load): Likewise.
(supportable_widening_operation): Use vect_halve_mask_nunits for
booleans.
(supportable_narrowing_operation): Likewise vect_double_mask_nunits.
(vect_gen_while): New function.
* config/aarch64/aarch64.md (umax<mode>3): New expander.
(aarch64_uqdec<mode>): New insn.
gcc/testsuite/
* gcc.dg/tree-ssa/cunroll-10.c: Disable vectorization.
* gcc.dg/tree-ssa/peel1.c: Likewise.
* gcc.dg/vect/vect-load-lanes-peeling-1.c: Remove XFAIL for
variable-length vectors.
* gcc.target/aarch64/sve/vcond_6.c: XFAIL test for AND.
* gcc.target/aarch64/sve/vec_bool_cmp_1.c: Expect BIC instead of NOT.
* gcc.target/aarch64/sve/slp_1.c: Check for a fully-masked loop.
* gcc.target/aarch64/sve/slp_2.c: Likewise.
* gcc.target/aarch64/sve/slp_3.c: Likewise.
* gcc.target/aarch64/sve/slp_4.c: Likewise.
* gcc.target/aarch64/sve/slp_6.c: Likewise.
* gcc.target/aarch64/sve/slp_8.c: New test.
* gcc.target/aarch64/sve/slp_8_run.c: Likewise.
* gcc.target/aarch64/sve/slp_9.c: Likewise.
* gcc.target/aarch64/sve/slp_9_run.c: Likewise.
* gcc.target/aarch64/sve/slp_10.c: Likewise.
* gcc.target/aarch64/sve/slp_10_run.c: Likewise.
* gcc.target/aarch64/sve/slp_11.c: Likewise.
* gcc.target/aarch64/sve/slp_11_run.c: Likewise.
* gcc.target/aarch64/sve/slp_12.c: Likewise.
* gcc.target/aarch64/sve/slp_12_run.c: Likewise.
* gcc.target/aarch64/sve/ld1r_2.c: Likewise.
* gcc.target/aarch64/sve/ld1r_2_run.c: Likewise.
* gcc.target/aarch64/sve/while_1.c: Likewise.
* gcc.target/aarch64/sve/while_2.c: Likewise.
* gcc.target/aarch64/sve/while_3.c: Likewise.
* gcc.target/aarch64/sve/while_4.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256625
|
||
|
Richard Sandiford
|
898f07b045 |
Add support for bitwise reductions
This patch adds support for the SVE bitwise reduction instructions
(ANDV, ORV and EORV). It's a fairly mechanical extension of existing
REDUC_* operators.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
(reduc_xor_scal_optab): New optabs.
* doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
(reduc_xor_scal_@var{m}): Document.
* doc/sourcebuild.texi (vect_logical_reduc): Likewise.
* internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
internal functions.
* fold-const-call.c (fold_const_call): Handle them.
* tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
* config/aarch64/aarch64-sve.md (reduc_<bit_reduc>_scal_<mode>):
(*reduc_<bit_reduc>_scal_<mode>): New patterns.
* config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
(UNSPEC_XORV): New unspecs.
(optab): Add entries for them.
(BITWISEV): New int iterator.
(bit_reduc_op): New int attributes.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_vect_logical_reduc):
New proc.
* gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
and add an associated scan-dump test. Prevent vectorization
of the first two loops.
* gcc.dg/vect/vect-reduc-or_2.c: Likewise.
* gcc.target/aarch64/sve/reduc_1.c: Add AND, IOR and XOR reductions.
* gcc.target/aarch64/sve/reduc_2.c: Likewise.
* gcc.target/aarch64/sve/reduc_1_run.c: Likewise.
(INIT_VECTOR): Tweak initial value so that some bits are always set.
* gcc.target/aarch64/sve/reduc_2_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256624
|
||
|
Richard Sandiford
|
f1739b4829 |
SLP reductions with variable-length vectors
Two things stopped us using SLP reductions with variable-length vectors:
(1) We didn't have a way of constructing the initial vector.
This patch does it by creating a vector full of the neutral
identity value and then using a shift-and-insert function
to insert any non-identity inputs into the low-numbered elements.
(The non-identity values are needed for double reductions.)
Alternatively, for unchained MIN/MAX reductions that have no neutral
value, we instead use the same duplicate-and-interleave approach as
for SLP constant and external definitions (added by a previous
patch).
(2) The epilogue for constant-length vectors would extract the vector
elements associated with each SLP statement and do scalar arithmetic
on these individual elements. For variable-length vectors, the patch
instead creates a reduction vector for each SLP statement, replacing
the elements for other SLP statements with the identity value.
It then uses a hardware reduction instruction on each vector.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (vec_shl_insert_@var{m}): New optab.
* internal-fn.def (VEC_SHL_INSERT): New internal function.
* optabs.def (vec_shl_insert_optab): New optab.
* tree-vectorizer.h (can_duplicate_and_interleave_p): Declare.
(duplicate_and_interleave): Likewise.
* tree-vect-loop.c: Include internal-fn.h.
(neutral_op_for_slp_reduction): New function, split out from
get_initial_defs_for_reduction.
(get_initial_def_for_reduction): Handle option 2 for variable-length
vectors by loading the neutral value into a vector and then shifting
the initial value into element 0.
(get_initial_defs_for_reduction): Replace the code argument with
the neutral value calculated by neutral_op_for_slp_reduction.
Use gimple_build_vector for constant-length vectors.
Use IFN_VEC_SHL_INSERT for variable-length vectors if all
but the first group_size elements have a neutral value.
Use duplicate_and_interleave otherwise.
(vect_create_epilog_for_reduction): Take a neutral_op parameter.
Update call to get_initial_defs_for_reduction. Handle SLP
reductions for variable-length vectors by creating one vector
result for each scalar result, with the elements associated
with other scalar results stubbed out with the neutral value.
(vectorizable_reduction): Call neutral_op_for_slp_reduction.
Require IFN_VEC_SHL_INSERT for double reductions on
variable-length vectors, or SLP reductions that have
a neutral value. Require can_duplicate_and_interleave_p
support for variable-length unchained SLP reductions if there
is no neutral value, such as for MIN/MAX reductions. Also require
the number of vector elements to be a multiple of the number of
SLP statements when doing variable-length unchained SLP reductions.
Update call to vect_create_epilog_for_reduction.
* tree-vect-slp.c (can_duplicate_and_interleave_p): Make public
and remove initial values.
(duplicate_and_interleave): Make public.
* config/aarch64/aarch64.md (UNSPEC_INSR): New unspec.
* config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): New insn.
gcc/testsuite/
* gcc.dg/vect/pr37027.c: Remove XFAIL for variable-length vectors.
* gcc.dg/vect/pr67790.c: Likewise.
* gcc.dg/vect/slp-reduc-1.c: Likewise.
* gcc.dg/vect/slp-reduc-2.c: Likewise.
* gcc.dg/vect/slp-reduc-3.c: Likewise.
* gcc.dg/vect/slp-reduc-5.c: Likewise.
* gcc.target/aarch64/sve/slp_5.c: New test.
* gcc.target/aarch64/sve/slp_5_run.c: Likewise.
* gcc.target/aarch64/sve/slp_6.c: Likewise.
* gcc.target/aarch64/sve/slp_6_run.c: Likewise.
* gcc.target/aarch64/sve/slp_7.c: Likewise.
* gcc.target/aarch64/sve/slp_7_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256623
|
||
|
Richard Sandiford
|
018b2744fc |
Handle more SLP constant and extern definitions for variable VF
This patch adds support for vectorising SLP definitions that are constant or external (i.e. from outside the loop) when the vectorisation factor isn't known at compile time. It can only handle cases where the number of SLP statements is a power of 2. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * tree-vect-slp.c: Include gimple-fold.h and internal-fn.h (can_duplicate_and_interleave_p): New function. (vect_get_and_check_slp_defs): Take the vector of statements rather than just the current one. Remove excess parentheses. Restriction rejectinon of vect_constant_def and vect_external_def for variable-length vectors to boolean types, or types for which can_duplicate_and_interleave_p is false. (vect_build_slp_tree_2): Update call to vect_get_and_check_slp_defs. (duplicate_and_interleave): New function. (vect_get_constant_vectors): Use gimple_build_vector for constant-length vectors and suitable variable-length constant vectors. Use duplicate_and_interleave for other variable-length vectors. Don't defer the update when inserting new statements. gcc/testsuite/ * gcc.dg/vect/no-scevccp-slp-30.c: Don't XFAIL for vect_variable_length && vect_load_lanes * gcc.dg/vect/slp-1.c: Likewise. * gcc.dg/vect/slp-10.c: Likewise. * gcc.dg/vect/slp-12b.c: Likewise. * gcc.dg/vect/slp-12c.c: Likewise. * gcc.dg/vect/slp-17.c: Likewise. * gcc.dg/vect/slp-19b.c: Likewise. * gcc.dg/vect/slp-20.c: Likewise. * gcc.dg/vect/slp-21.c: Likewise. * gcc.dg/vect/slp-22.c: Likewise. * gcc.dg/vect/slp-23.c: Likewise. * gcc.dg/vect/slp-24-big-array.c: Likewise. * gcc.dg/vect/slp-24.c: Likewise. * gcc.dg/vect/slp-28.c: Likewise. * gcc.dg/vect/slp-39.c: Likewise. * gcc.dg/vect/slp-6.c: Likewise. * gcc.dg/vect/slp-7.c: Likewise. * gcc.dg/vect/slp-cond-1.c: Likewise. * gcc.dg/vect/slp-cond-2-big-array.c: Likewise. * gcc.dg/vect/slp-cond-2.c: Likewise. * gcc.dg/vect/slp-multitypes-1.c: Likewise. * gcc.dg/vect/slp-multitypes-8.c: Likewise. * gcc.dg/vect/slp-multitypes-9.c: Likewise. * gcc.dg/vect/slp-multitypes-10.c: Likewise. * gcc.dg/vect/slp-multitypes-12.c: Likewise. * gcc.dg/vect/slp-perm-6.c: Likewise. * gcc.dg/vect/slp-widen-mult-half.c: Likewise. * gcc.dg/vect/vect-live-slp-1.c: Likewise. * gcc.dg/vect/vect-live-slp-2.c: Likewise. * gcc.dg/vect/pr33953.c: Don't XFAIL for vect_variable_length. * gcc.dg/vect/slp-12a.c: Likewise. * gcc.dg/vect/slp-14.c: Likewise. * gcc.dg/vect/slp-15.c: Likewise. * gcc.dg/vect/slp-multitypes-2.c: Likewise. * gcc.dg/vect/slp-multitypes-4.c: Likewise. * gcc.dg/vect/slp-multitypes-5.c: Likewise. * gcc.target/aarch64/sve/slp_1.c: New test. * gcc.target/aarch64/sve/slp_1_run.c: Likewise. * gcc.target/aarch64/sve/slp_2.c: Likewise. * gcc.target/aarch64/sve/slp_2_run.c: Likewise. * gcc.target/aarch64/sve/slp_3.c: Likewise. * gcc.target/aarch64/sve/slp_3_run.c: Likewise. * gcc.target/aarch64/sve/slp_4.c: Likewise. * gcc.target/aarch64/sve/slp_4_run.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256622 |
||
|
Richard Sandiford
|
3ea518f6f6 |
Protect against min_profitable_iters going negative
We had:
if (vec_outside_cost <= 0)
min_profitable_iters = 0;
else
{
min_profitable_iters = ((vec_outside_cost - scalar_outside_cost)
* assumed_vf
- vec_inside_cost * peel_iters_prologue
- vec_inside_cost * peel_iters_epilogue)
/ ((scalar_single_iter_cost * assumed_vf)
- vec_inside_cost);
which can lead to negative min_profitable_iters when the *_outside_costs
are the same and peel_iters_epilogue is nonzero (e.g. if we're peeling
for gaps).
This is tested as part of the patch that adds support for fully-predicated
loops.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vect-loop.c (vect_estimate_min_profitable_iters): Make sure
min_profitable_iters doesn't go negative.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256621
|
||
|
Richard Sandiford
|
7e11fc7f5c |
Add support for masked load/store_lanes
This patch adds support for vectorising groups of IFN_MASK_LOADs
and IFN_MASK_STOREs using conditional load/store-lanes instructions.
This requires new internal functions to represent the result
(IFN_MASK_{LOAD,STORE}_LANES), as well as associated optabs.
The normal IFN_{LOAD,STORE}_LANES functions are const operations
that logically just perform the permute: the load or store is
encoded as a MEM operand to the call statement. In contrast,
the IFN_MASK_{LOAD,STORE}_LANES functions use the same kind of
interface as IFN_MASK_{LOAD,STORE}, since the memory is only
conditionally accessed.
The AArch64 patterns were added as part of the main LD[234]/ST[234] patch.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (vec_mask_load_lanes@var{m}@var{n}): Document.
(vec_mask_store_lanes@var{m}@var{n}): Likewise.
* optabs.def (vec_mask_load_lanes_optab): New optab.
(vec_mask_store_lanes_optab): Likewise.
* internal-fn.def (MASK_LOAD_LANES): New internal function.
(MASK_STORE_LANES): Likewise.
* internal-fn.c (mask_load_lanes_direct): New macro.
(mask_store_lanes_direct): Likewise.
(expand_mask_load_optab_fn): Handle masked operations.
(expand_mask_load_lanes_optab_fn): New macro.
(expand_mask_store_optab_fn): Handle masked operations.
(expand_mask_store_lanes_optab_fn): New macro.
(direct_mask_load_lanes_optab_supported_p): Likewise.
(direct_mask_store_lanes_optab_supported_p): Likewise.
* tree-vectorizer.h (vect_store_lanes_supported): Take a masked_p
parameter.
(vect_load_lanes_supported): Likewise.
* tree-vect-data-refs.c (strip_conversion): New function.
(can_group_stmts_p): Likewise.
(vect_analyze_data_ref_accesses): Use it instead of checking
for a pair of assignments.
(vect_store_lanes_supported): Take a masked_p parameter.
(vect_load_lanes_supported): Likewise.
* tree-vect-loop.c (vect_analyze_loop_2): Update calls to
vect_store_lanes_supported and vect_load_lanes_supported.
* tree-vect-slp.c (vect_analyze_slp_instance): Likewise.
* tree-vect-stmts.c (get_group_load_store_type): Take a masked_p
parameter. Don't allow gaps for masked accesses.
Use vect_get_store_rhs. Update calls to vect_store_lanes_supported
and vect_load_lanes_supported.
(get_load_store_type): Take a masked_p parameter and update
call to get_group_load_store_type.
(vectorizable_store): Update call to get_load_store_type.
Handle IFN_MASK_STORE_LANES.
(vectorizable_load): Update call to get_load_store_type.
Handle IFN_MASK_LOAD_LANES.
gcc/testsuite/
* gcc.dg/vect/vect-ooo-group-1.c: New test.
* gcc.target/aarch64/sve/mask_struct_load_1.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_1_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_2.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_2_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_3.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_3_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_4.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_5.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_6.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_7.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_load_8.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_1.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_1_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_2.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_2_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_3.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_3_run.c: Likewise.
* gcc.target/aarch64/sve/mask_struct_store_4.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256620
|
||
|
Richard Sandiford
|
abc8eb9a45 |
[AArch64] Tests for SVE structure modes
This patch adds tests for the SVE structure mode move patterns and for LD[234] and ST[234] vectorisation. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/testsuite/ * gcc.target/aarch64/sve/struct_move_1.c: New test. * gcc.target/aarch64/sve/struct_move_2.c: Likewise. * gcc.target/aarch64/sve/struct_move_3.c: Likewise. * gcc.target/aarch64/sve/struct_move_4.c: Likewise. * gcc.target/aarch64/sve/struct_move_5.c: Likewise. * gcc.target/aarch64/sve/struct_move_6.c: Likewise. * gcc.target/aarch64/sve/struct_vect_1.c: Likewise. * gcc.target/aarch64/sve/struct_vect_1_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_2.c: Likewise. * gcc.target/aarch64/sve/struct_vect_2_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_3.c: Likewise. * gcc.target/aarch64/sve/struct_vect_3_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_4.c: Likewise. * gcc.target/aarch64/sve/struct_vect_4_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_5.c: Likewise. * gcc.target/aarch64/sve/struct_vect_5_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_6.c: Likewise. * gcc.target/aarch64/sve/struct_vect_6_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_7.c: Likewise. * gcc.target/aarch64/sve/struct_vect_7_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_8.c: Likewise. * gcc.target/aarch64/sve/struct_vect_8_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_9.c: Likewise. * gcc.target/aarch64/sve/struct_vect_9_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_10.c: Likewise. * gcc.target/aarch64/sve/struct_vect_10_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_11.c: Likewise. * gcc.target/aarch64/sve/struct_vect_11_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_12.c: Likewise. * gcc.target/aarch64/sve/struct_vect_12_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_13.c: Likewise. * gcc.target/aarch64/sve/struct_vect_13_run.c: Likewise. * gcc.target/aarch64/sve/struct_vect_14.c: Likewise. * gcc.target/aarch64/sve/struct_vect_15.c: Likewise. * gcc.target/aarch64/sve/struct_vect_16.c: Likewise. * gcc.target/aarch64/sve/struct_vect_17.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256619 |
||
|
Richard Sandiford
|
9f4cbab84d |
[AArch64] SVE load/store_lanes support
This patch adds support for SVE LD[234], ST[234] and associated structure modes. Unlike Advanced SIMD, these modes are extra-long vector modes instead of integer modes. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * config/aarch64/aarch64-modes.def: Define x2, x3 and x4 vector modes for SVE. * config/aarch64/aarch64-protos.h (aarch64_sve_struct_memory_operand_p): Declare. * config/aarch64/iterators.md (SVE_STRUCT): New mode iterator. (vector_count, insn_length, VSINGLE, vsingle): New mode attributes. (VPRED, vpred): Handle SVE structure modes. * config/aarch64/constraints.md (Utx): New constraint. * config/aarch64/predicates.md (aarch64_sve_struct_memory_operand) (aarch64_sve_struct_nonimmediate_operand): New predicates. * config/aarch64/aarch64.md (UNSPEC_LDN, UNSPEC_STN): New unspecs. * config/aarch64/aarch64-sve.md (mov<mode>, *aarch64_sve_mov<mode>_le) (*aarch64_sve_mov<mode>_be, pred_mov<mode>): New patterns for structure modes. Split into pieces after RA. (vec_load_lanes<mode><vsingle>, vec_mask_load_lanes<mode><vsingle>) (vec_store_lanes<mode><vsingle>, vec_mask_store_lanes<mode><vsingle>): New patterns. * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle SVE structure modes. (aarch64_classify_address): Likewise. (sizetochar): Move earlier in file. (aarch64_print_operand): Handle SVE register lists. (aarch64_array_mode): New function. (aarch64_sve_struct_memory_operand_p): Likewise. (TARGET_ARRAY_MODE): Redefine. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_vect_load_lanes): Return true for SVE too. * g++.dg/vect/pr36648.cc: XFAIL for variable-length vectors if load/store lanes are supported. * gcc.dg/vect/slp-10.c: Likewise. * gcc.dg/vect/slp-12c.c: Likewise. * gcc.dg/vect/slp-17.c: Likewise. * gcc.dg/vect/slp-33.c: Likewise. * gcc.dg/vect/slp-6.c: Likewise. * gcc.dg/vect/slp-cond-1.c: Likewise. * gcc.dg/vect/slp-multitypes-11-big-array.c: Likewise. * gcc.dg/vect/slp-multitypes-11.c: Likewise. * gcc.dg/vect/slp-multitypes-12.c: Likewise. * gcc.dg/vect/slp-perm-5.c: Remove XFAIL for variable-length SVE. * gcc.dg/vect/slp-perm-6.c: Likewise. * gcc.dg/vect/slp-perm-9.c: Likewise. * gcc.dg/vect/slp-reduc-6.c: Remove XFAIL for variable-length vectors. * gcc.dg/vect/vect-load-lanes-peeling-1.c: Expect an epilogue loop for variable-length vectors. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256618 |
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|
Richard Sandiford
|
695da53448 |
Give the target more control over ARRAY_TYPE modes
So far we've used integer modes for LD[234] and ST[234] arrays. That doesn't scale well to SVE, since the sizes aren't fixed at compile time (and even if they were, we wouldn't want integers to be so wide). This patch lets the target use double-, triple- and quadruple-length vectors instead. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * target.def (array_mode): New target hook. * doc/tm.texi.in (TARGET_ARRAY_MODE): New hook. * doc/tm.texi: Regenerate. * hooks.h (hook_optmode_mode_uhwi_none): Declare. * hooks.c (hook_optmode_mode_uhwi_none): New function. * tree-vect-data-refs.c (vect_lanes_optab_supported_p): Use targetm.array_mode. * stor-layout.c (mode_for_array): Likewise. Support polynomial type sizes. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256617 |
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Richard Sandiford
|
779fed5fdb |
Fix folding of vector mask EQ/NE expressions
fold_binary_loc assumed that if the type of the result wasn't a vector, the operands wouldn't be either. This isn't necessarily true for EQ_EXPR and NE_EXPR of vector masks, which can return a single scalar for the mask as a whole. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * fold-const.c (fold_binary_loc): Check the argument types rather than the result type when testing for a vector operation. gcc/testsuite/ * gcc.target/aarch64/sve/vec_bool_cmp_1.c: New test. * gcc.target/aarch64/sve/vec_bool_cmp_1_run.c: Likweise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256616 |
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Richard Sandiford
|
dbc3af4fc6 |
SVE unwinding
This patch adds support for unwinding frames that use the SVE pseudo VG register. We want this register to act like a normal register if the CFI explicitly sets it, but want to provide a default value otherwise. Computing the default value requires an SVE target, so we only want to compute it on demand. aarch64_vg uses a hard-coded .inst in order to avoid a build dependency on binutils 2.28 or later. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * doc/tm.texi.in (DWARF_LAZY_REGISTER_VALUE): Document. * doc/tm.texi: Regenerate. libgcc/ * config/aarch64/value-unwind.h (aarch64_vg): New function. (DWARF_LAZY_REGISTER_VALUE): Define. * unwind-dw2.c (_Unwind_GetGR): Use DWARF_LAZY_REGISTER_VALUE to provide a fallback register value. gcc/testsuite/ * g++.target/aarch64/sve/aarch64-sve.exp: New harness. * g++.target/aarch64/sve/catch_1.C: New test. * g++.target/aarch64/sve/catch_2.C: Likewise. * g++.target/aarch64/sve/catch_3.C: Likewise. * g++.target/aarch64/sve/catch_4.C: Likewise. * g++.target/aarch64/sve/catch_5.C: Likewise. * g++.target/aarch64/sve/catch_6.C: Likewise. Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> From-SVN: r256615 |
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Richard Sandiford
|
825b856cd0 |
[AArch64] SVE tests
This patch adds gcc.target/aarch64 tests for SVE, and forces some existing Advanced SIMD tests to use -march=armv8-a. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_asm_sve_ok): New proc. * gcc.target/aarch64/bic_imm_1.c: Use #pragma GCC target "+nosve". * gcc.target/aarch64/fmaxmin.c: Likewise. * gcc.target/aarch64/fmul_fcvt_2.c: Likewise. * gcc.target/aarch64/orr_imm_1.c: Likewise. * gcc.target/aarch64/pr62178.c: Likewise. * gcc.target/aarch64/pr71727-2.c: Likewise. * gcc.target/aarch64/saddw-1.c: Likewise. * gcc.target/aarch64/saddw-2.c: Likewise. * gcc.target/aarch64/uaddw-1.c: Likewise. * gcc.target/aarch64/uaddw-2.c: Likewise. * gcc.target/aarch64/uaddw-3.c: Likewise. * gcc.target/aarch64/vect-add-sub-cond.c: Likewise. * gcc.target/aarch64/vect-compile.c: Likewise. * gcc.target/aarch64/vect-faddv-compile.c: Likewise. * gcc.target/aarch64/vect-fcm-eq-d.c: Likewise. * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. * gcc.target/aarch64/vect-fmax-fmin-compile.c: Likewise. * gcc.target/aarch64/vect-fmaxv-fminv-compile.c: Likewise. * gcc.target/aarch64/vect-fmovd-zero.c: Likewise. * gcc.target/aarch64/vect-fmovd.c: Likewise. * gcc.target/aarch64/vect-fmovf-zero.c: Likewise. * gcc.target/aarch64/vect-fmovf.c: Likewise. * gcc.target/aarch64/vect-fp-compile.c: Likewise. * gcc.target/aarch64/vect-ld1r-compile-fp.c: Likewise. * gcc.target/aarch64/vect-ld1r-compile.c: Likewise. * gcc.target/aarch64/vect-movi.c: Likewise. * gcc.target/aarch64/vect-mull-compile.c: Likewise. * gcc.target/aarch64/vect-reduc-or_1.c: Likewise. * gcc.target/aarch64/vect-vaddv.c: Likewise. * gcc.target/aarch64/vect_saddl_1.c: Likewise. * gcc.target/aarch64/vect_smlal_1.c: Likewise. * gcc.target/aarch64/vector_initialization_nostack.c: XFAIL for fixed-length SVE. * gcc.target/aarch64/sve/aarch64-sve.exp: New file. * gcc.target/aarch64/sve/arith_1.c: New test. * gcc.target/aarch64/sve/const_pred_1.C: Likewise. * gcc.target/aarch64/sve/const_pred_2.C: Likewise. * gcc.target/aarch64/sve/const_pred_3.C: Likewise. * gcc.target/aarch64/sve/const_pred_4.C: Likewise. * gcc.target/aarch64/sve/cvtf_signed_1.c: Likewise. * gcc.target/aarch64/sve/cvtf_signed_1_run.c: Likewise. * gcc.target/aarch64/sve/cvtf_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/cvtf_unsigned_1_run.c: Likewise. * gcc.target/aarch64/sve/dup_imm_1.c: Likewise. * gcc.target/aarch64/sve/dup_imm_1_run.c: Likewise. * gcc.target/aarch64/sve/dup_lane_1.c: Likewise. * gcc.target/aarch64/sve/ext_1.c: Likewise. * gcc.target/aarch64/sve/ext_2.c: Likewise. * gcc.target/aarch64/sve/extract_1.c: Likewise. * gcc.target/aarch64/sve/extract_2.c: Likewise. * gcc.target/aarch64/sve/extract_3.c: Likewise. * gcc.target/aarch64/sve/extract_4.c: Likewise. * gcc.target/aarch64/sve/fabs_1.c: Likewise. * gcc.target/aarch64/sve/fcvtz_signed_1.c: Likewise. * gcc.target/aarch64/sve/fcvtz_signed_1_run.c: Likewise. * gcc.target/aarch64/sve/fcvtz_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/fcvtz_unsigned_1_run.c: Likewise. * gcc.target/aarch64/sve/fdiv_1.c: Likewise. * gcc.target/aarch64/sve/fdup_1.c: Likewise. * gcc.target/aarch64/sve/fdup_1_run.c: Likewise. * gcc.target/aarch64/sve/fmad_1.c: Likewise. * gcc.target/aarch64/sve/fmla_1.c: Likewise. * gcc.target/aarch64/sve/fmls_1.c: Likewise. * gcc.target/aarch64/sve/fmsb_1.c: Likewise. * gcc.target/aarch64/sve/fmul_1.c: Likewise. * gcc.target/aarch64/sve/fneg_1.c: Likewise. * gcc.target/aarch64/sve/fnmad_1.c: Likewise. * gcc.target/aarch64/sve/fnmla_1.c: Likewise. * gcc.target/aarch64/sve/fnmls_1.c: Likewise. * gcc.target/aarch64/sve/fnmsb_1.c: Likewise. * gcc.target/aarch64/sve/fp_arith_1.c: Likewise. * gcc.target/aarch64/sve/frinta_1.c: Likewise. * gcc.target/aarch64/sve/frinti_1.c: Likewise. * gcc.target/aarch64/sve/frintm_1.c: Likewise. * gcc.target/aarch64/sve/frintp_1.c: Likewise. * gcc.target/aarch64/sve/frintx_1.c: Likewise. * gcc.target/aarch64/sve/frintz_1.c: Likewise. * gcc.target/aarch64/sve/fsqrt_1.c: Likewise. * gcc.target/aarch64/sve/fsubr_1.c: Likewise. * gcc.target/aarch64/sve/index_1.c: Likewise. * gcc.target/aarch64/sve/index_1_run.c: Likewise. * gcc.target/aarch64/sve/ld1r_1.c: Likewise. * gcc.target/aarch64/sve/load_const_offset_1.c: Likewise. * gcc.target/aarch64/sve/load_const_offset_2.c: Likewise. * gcc.target/aarch64/sve/load_const_offset_3.c: Likewise. * gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise. * gcc.target/aarch64/sve/logical_1.c: Likewise. * gcc.target/aarch64/sve/loop_add_1.c: Likewise. * gcc.target/aarch64/sve/loop_add_1_run.c: Likewise. * gcc.target/aarch64/sve/mad_1.c: Likewise. * gcc.target/aarch64/sve/maxmin_1.c: Likewise. * gcc.target/aarch64/sve/maxmin_1_run.c: Likewise. * gcc.target/aarch64/sve/maxmin_strict_1.c: Likewise. * gcc.target/aarch64/sve/maxmin_strict_1_run.c: Likewise. * gcc.target/aarch64/sve/mla_1.c: Likewise. * gcc.target/aarch64/sve/mls_1.c: Likewise. * gcc.target/aarch64/sve/mov_rr_1.c: Likewise. * gcc.target/aarch64/sve/msb_1.c: Likewise. * gcc.target/aarch64/sve/mul_1.c: Likewise. * gcc.target/aarch64/sve/neg_1.c: Likewise. * gcc.target/aarch64/sve/nlogical_1.c: Likewise. * gcc.target/aarch64/sve/nlogical_1_run.c: Likewise. * gcc.target/aarch64/sve/pack_1.c: Likewise. * gcc.target/aarch64/sve/pack_1_run.c: Likewise. * gcc.target/aarch64/sve/pack_fcvt_signed_1.c: Likewise. * gcc.target/aarch64/sve/pack_fcvt_signed_1_run.c: Likewise. * gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/pack_fcvt_unsigned_1_run.c: Likewise. * gcc.target/aarch64/sve/pack_float_1.c: Likewise. * gcc.target/aarch64/sve/pack_float_1_run.c: Likewise. * gcc.target/aarch64/sve/popcount_1.c: Likewise. * gcc.target/aarch64/sve/popcount_1_run.c: Likewise. * gcc.target/aarch64/sve/reduc_1.c: Likewise. * gcc.target/aarch64/sve/reduc_1_run.c: Likewise. * gcc.target/aarch64/sve/reduc_2.c: Likewise. * gcc.target/aarch64/sve/reduc_2_run.c: Likewise. * gcc.target/aarch64/sve/reduc_3.c: Likewise. * gcc.target/aarch64/sve/rev_1.c: Likewise. * gcc.target/aarch64/sve/revb_1.c: Likewise. * gcc.target/aarch64/sve/revh_1.c: Likewise. * gcc.target/aarch64/sve/revw_1.c: Likewise. * gcc.target/aarch64/sve/shift_1.c: Likewise. * gcc.target/aarch64/sve/single_1.c: Likewise. * gcc.target/aarch64/sve/single_2.c: Likewise. * gcc.target/aarch64/sve/single_3.c: Likewise. * gcc.target/aarch64/sve/single_4.c: Likewise. * gcc.target/aarch64/sve/spill_1.c: Likewise. * gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise. * gcc.target/aarch64/sve/subr_1.c: Likewise. * gcc.target/aarch64/sve/trn1_1.c: Likewise. * gcc.target/aarch64/sve/trn2_1.c: Likewise. * gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Likewise. * gcc.target/aarch64/sve/unpack_fcvt_signed_1_run.c: Likewise. * gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/unpack_fcvt_unsigned_1_run.c: Likewise. * gcc.target/aarch64/sve/unpack_float_1.c: Likewise. * gcc.target/aarch64/sve/unpack_float_1_run.c: Likewise. * gcc.target/aarch64/sve/unpack_signed_1.c: Likewise. * gcc.target/aarch64/sve/unpack_signed_1_run.c: Likewise. * gcc.target/aarch64/sve/unpack_unsigned_1.c: Likewise. * gcc.target/aarch64/sve/unpack_unsigned_1_run.c: Likewise. * gcc.target/aarch64/sve/uzp1_1.c: Likewise. * gcc.target/aarch64/sve/uzp1_1_run.c: Likewise. * gcc.target/aarch64/sve/uzp2_1.c: Likewise. * gcc.target/aarch64/sve/uzp2_1_run.c: Likewise. * gcc.target/aarch64/sve/vcond_1.C: Likewise. * gcc.target/aarch64/sve/vcond_1_run.C: Likewise. * gcc.target/aarch64/sve/vcond_2.c: Likewise. * gcc.target/aarch64/sve/vcond_2_run.c: Likewise. * gcc.target/aarch64/sve/vcond_3.c: Likewise. * gcc.target/aarch64/sve/vcond_4.c: Likewise. * gcc.target/aarch64/sve/vcond_4_run.c: Likewise. * gcc.target/aarch64/sve/vcond_5.c: Likewise. * gcc.target/aarch64/sve/vcond_5_run.c: Likewise. * gcc.target/aarch64/sve/vcond_6.c: Likewise. * gcc.target/aarch64/sve/vcond_6_run.c: Likewise. * gcc.target/aarch64/sve/vec_init_1.c: Likewise. * gcc.target/aarch64/sve/vec_init_1_run.c: Likewise. * gcc.target/aarch64/sve/vec_init_2.c: Likewise. * gcc.target/aarch64/sve/vec_perm_1.c: Likewise. * gcc.target/aarch64/sve/vec_perm_1_run.c: Likewise. * gcc.target/aarch64/sve/vec_perm_1_overrange_run.c: Likewise. * gcc.target/aarch64/sve/vec_perm_const_1.c: Likewise. * gcc.target/aarch64/sve/vec_perm_const_1_overrun.c: Likewise. * gcc.target/aarch64/sve/vec_perm_const_1_run.c: Likewise. * gcc.target/aarch64/sve/vec_perm_const_single_1.c: Likewise. * gcc.target/aarch64/sve/vec_perm_const_single_1_run.c: Likewise. * gcc.target/aarch64/sve/vec_perm_single_1.c: Likewise. * gcc.target/aarch64/sve/vec_perm_single_1_run.c: Likewise. * gcc.target/aarch64/sve/zip1_1.c: Likewise. * gcc.target/aarch64/sve/zip2_1.c: Likewise. Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256614 |
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Richard Sandiford
|
801e38459d |
[AArch64] Testsuite markup for SVE
This patch adds new target selectors for SVE and updates existing selectors accordingly. It also XFAILs some tests that don't yet work for some SVE modes; most of these go away with follow-on vectorisation enhancements. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_sve) (aarch64_sve_bits, check_effective_target_aarch64_sve_hw) (aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw): New procedures. (check_effective_target_vect_perm): Handle SVE. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_hi_to_si): Likewise. (check_effective_target_vect_element_align_preferred): Likewise. (check_effective_target_vect_align_stack_vars): Likewise. (check_effective_target_vect_load_lanes): Likewise. (check_effective_target_vect_masked_store): Likewise. (available_vector_sizes): Use aarch64_sve_bits for SVE. * gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately for SVE. * gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL. * gcc.dg/vect/bb-slp-pr69907.c: Likewise. * gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise. * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise. * gcc.dg/vect/slp-23.c: Likewise. * gcc.dg/vect/slp-perm-5.c: Likewise. * gcc.dg/vect/slp-perm-6.c: Likewise. * gcc.dg/vect/slp-perm-9.c: Likewise. * gcc.dg/vect/slp-reduc-3.c: Likewise. * gcc.dg/vect/vect-114.c: Likewise. * gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise. * gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise. Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r256613 |
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Richard Sandiford
|
43cacb12fc |
[AArch64] Add SVE support
This patch adds support for ARM's Scalable Vector Extension.
The patch just contains the core features that work with the
current vectoriser framework; later patches will add extra
capabilities to both the target-independent code and AArch64 code.
The patch doesn't include:
- support for unwinding frames whose size depends on the vector length
- modelling the effect of __tls_get_addr on the SVE registers
These are handled by later patches instead.
Some notes:
- The copyright years for aarch64-sve.md start at 2009 because some of
the code is based on aarch64.md, which also starts from then.
- The patch inserts spaces between items in the AArch64 section
of sourcebuild.texi. This matches at least the surrounding
architectures and looks a little nicer in the info output.
- aarch64-sve.md includes a pattern:
while_ult<GPI:mode><PRED_ALL:mode>
A later patch adds a matching "while_ult" optab, but the pattern
is also needed by the predicate vec_duplicate expander.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/invoke.texi (-msve-vector-bits=): Document new option.
(sve): Document new AArch64 extension.
* doc/md.texi (w): Extend the description of the AArch64
constraint to include SVE vectors.
(Upl, Upa): Document new AArch64 predicate constraints.
* config/aarch64/aarch64-opts.h (aarch64_sve_vector_bits_enum): New
enum.
* config/aarch64/aarch64.opt (sve_vector_bits): New enum.
(msve-vector-bits=): New option.
* config/aarch64/aarch64-option-extensions.def (fp, simd): Disable
SVE when these are disabled.
(sve): New extension.
* config/aarch64/aarch64-modes.def: Define SVE vector and predicate
modes. Adjust their number of units based on aarch64_sve_vg.
(MAX_BITSIZE_MODE_ANY_MODE): Define.
* config/aarch64/aarch64-protos.h (ADDR_QUERY_ANY): New
aarch64_addr_query_type.
(aarch64_const_vec_all_same_in_range_p, aarch64_sve_pred_mode)
(aarch64_sve_cnt_immediate_p, aarch64_sve_addvl_addpl_immediate_p)
(aarch64_sve_inc_dec_immediate_p, aarch64_add_offset_temporaries)
(aarch64_split_add_offset, aarch64_output_sve_cnt_immediate)
(aarch64_output_sve_addvl_addpl, aarch64_output_sve_inc_dec_immediate)
(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): Declare.
(aarch64_simd_imm_zero_p): Delete.
(aarch64_check_zero_based_sve_index_immediate): Declare.
(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): Likewise.
(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
rather than an rtx.
(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): Declare.
(aarch64_expand_mov_immediate): Take a gen_vec_duplicate callback.
(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move): Declare.
(aarch64_expand_sve_vec_cmp_int, aarch64_expand_sve_vec_cmp_float)
(aarch64_expand_sve_vcond, aarch64_expand_sve_vec_perm): Declare.
(aarch64_regmode_natural_size): Likewise.
* config/aarch64/aarch64.h (AARCH64_FL_SVE): New macro.
(AARCH64_FL_V8_3, AARCH64_FL_RCPC, AARCH64_FL_DOTPROD): Shift
left one place.
(AARCH64_ISA_SVE, TARGET_SVE): New macros.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REGISTER_NAMES): Add entries
for VG and the SVE predicate registers.
(V_ALIASES): Add a "z"-prefixed alias.
(FIRST_PSEUDO_REGISTER): Change to P15_REGNUM + 1.
(AARCH64_DWARF_VG, AARCH64_DWARF_P0): New macros.
(PR_REGNUM_P, PR_LO_REGNUM_P): Likewise.
(PR_LO_REGS, PR_HI_REGS, PR_REGS): New reg_classes.
(REG_CLASS_NAMES): Add entries for them.
(REG_CLASS_CONTENTS): Likewise. Update ALL_REGS to include VG
and the predicate registers.
(aarch64_sve_vg): Declare.
(BITS_PER_SVE_VECTOR, BYTES_PER_SVE_VECTOR, BYTES_PER_SVE_PRED)
(SVE_BYTE_MODE, MAX_COMPILE_TIME_VEC_BYTES): New macros.
(REGMODE_NATURAL_SIZE): Define.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
SVE macros.
* config/aarch64/aarch64.c: Include cfgrtl.h.
(simd_immediate_info): Add a constructor for series vectors,
and an associated step field.
(aarch64_sve_vg): New variable.
(aarch64_dbx_register_number): Handle VG and the predicate registers.
(aarch64_vect_struct_mode_p, aarch64_vector_mode_p): Delete.
(VEC_ADVSIMD, VEC_SVE_DATA, VEC_SVE_PRED, VEC_STRUCT, VEC_ANY_SVE)
(VEC_ANY_DATA, VEC_STRUCT): New constants.
(aarch64_advsimd_struct_mode_p, aarch64_sve_pred_mode_p)
(aarch64_classify_vector_mode, aarch64_vector_data_mode_p)
(aarch64_sve_data_mode_p, aarch64_sve_pred_mode)
(aarch64_get_mask_mode): New functions.
(aarch64_hard_regno_nregs): Handle SVE data modes for FP_REGS
and FP_LO_REGS. Handle PR_REGS, PR_LO_REGS and PR_HI_REGS.
(aarch64_hard_regno_mode_ok): Handle VG. Also handle the SVE
predicate modes and predicate registers. Explicitly restrict
GPRs to modes of 16 bytes or smaller. Only allow FP registers
to store a vector mode if it is recognized by
aarch64_classify_vector_mode.
(aarch64_regmode_natural_size): New function.
(aarch64_hard_regno_caller_save_mode): Return the original mode
for predicates.
(aarch64_sve_cnt_immediate_p, aarch64_output_sve_cnt_immediate)
(aarch64_sve_addvl_addpl_immediate_p, aarch64_output_sve_addvl_addpl)
(aarch64_sve_inc_dec_immediate_p, aarch64_output_sve_inc_dec_immediate)
(aarch64_add_offset_1_temporaries, aarch64_offset_temporaries): New
functions.
(aarch64_add_offset): Add a temp2 parameter. Assert that temp1
does not overlap dest if the function is frame-related. Handle
SVE constants.
(aarch64_split_add_offset): New function.
(aarch64_add_sp, aarch64_sub_sp): Add temp2 parameters and pass
them aarch64_add_offset.
(aarch64_allocate_and_probe_stack_space): Add a temp2 parameter
and update call to aarch64_sub_sp.
(aarch64_add_cfa_expression): New function.
(aarch64_expand_prologue): Pass extra temporary registers to the
functions above. Handle the case in which we need to emit new
DW_CFA_expressions for registers that were originally saved
relative to the stack pointer, but now have to be expressed
relative to the frame pointer.
(aarch64_output_mi_thunk): Pass extra temporary registers to the
functions above.
(aarch64_expand_epilogue): Likewise. Prevent inheritance of
IP0 and IP1 values for SVE frames.
(aarch64_expand_vec_series): New function.
(aarch64_expand_sve_widened_duplicate): Likewise.
(aarch64_expand_sve_const_vector): Likewise.
(aarch64_expand_mov_immediate): Add a gen_vec_duplicate parameter.
Handle SVE constants. Use emit_move_insn to move a force_const_mem
into the register, rather than emitting a SET directly.
(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move)
(aarch64_get_reg_raw_mode, offset_4bit_signed_scaled_p)
(offset_6bit_unsigned_scaled_p, aarch64_offset_7bit_signed_scaled_p)
(offset_9bit_signed_scaled_p): New functions.
(aarch64_replicate_bitmask_imm): New function.
(aarch64_bitmask_imm): Use it.
(aarch64_cannot_force_const_mem): Reject expressions involving
a CONST_POLY_INT. Update call to aarch64_classify_symbol.
(aarch64_classify_index): Handle SVE indices, by requiring
a plain register index with a scale that matches the element size.
(aarch64_classify_address): Handle SVE addresses. Assert that
the mode of the address is VOIDmode or an integer mode.
Update call to aarch64_classify_symbol.
(aarch64_classify_symbolic_expression): Update call to
aarch64_classify_symbol.
(aarch64_const_vec_all_in_range_p): New function.
(aarch64_print_vector_float_operand): Likewise.
(aarch64_print_operand): Handle 'N' and 'C'. Use "zN" rather than
"vN" for FP registers with SVE modes. Handle (const ...) vectors
and the FP immediates 1.0 and 0.5.
(aarch64_print_address_internal): Handle SVE addresses.
(aarch64_print_operand_address): Use ADDR_QUERY_ANY.
(aarch64_regno_regclass): Handle predicate registers.
(aarch64_secondary_reload): Handle big-endian reloads of SVE
data modes.
(aarch64_class_max_nregs): Handle SVE modes and predicate registers.
(aarch64_rtx_costs): Check for ADDVL and ADDPL instructions.
(aarch64_convert_sve_vector_bits): New function.
(aarch64_override_options): Use it to handle -msve-vector-bits=.
(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
rather than an rtx.
(aarch64_legitimate_constant_p): Use aarch64_classify_vector_mode.
Handle SVE vector and predicate modes. Accept VL-based constants
that need only one temporary register, and VL offsets that require
no temporary registers.
(aarch64_conditional_register_usage): Mark the predicate registers
as fixed if SVE isn't available.
(aarch64_vector_mode_supported_p): Use aarch64_classify_vector_mode.
Return true for SVE vector and predicate modes.
(aarch64_simd_container_mode): Take the number of bits as a poly_int64
rather than an unsigned int. Handle SVE modes.
(aarch64_preferred_simd_mode): Update call accordingly. Handle
SVE modes.
(aarch64_autovectorize_vector_sizes): Add BYTES_PER_SVE_VECTOR
if SVE is enabled.
(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): New functions.
(aarch64_sve_valid_immediate): New function.
(aarch64_simd_valid_immediate): Use it as the fallback for SVE vectors.
Explicitly reject structure modes. Check for INDEX constants.
Handle PTRUE and PFALSE constants.
(aarch64_check_zero_based_sve_index_immediate): New function.
(aarch64_simd_imm_zero_p): Delete.
(aarch64_mov_operand_p): Use aarch64_simd_valid_immediate for
vector modes. Accept constants in the range of CNT[BHWD].
(aarch64_simd_scalar_immediate_valid_for_move): Explicitly
ask for an Advanced SIMD mode.
(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): New functions.
(aarch64_simd_vector_alignment): Handle SVE predicates.
(aarch64_vectorize_preferred_vector_alignment): New function.
(aarch64_simd_vector_alignment_reachable): Use it instead of
the vector size.
(aarch64_shift_truncation_mask): Use aarch64_vector_data_mode_p.
(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): New
functions.
(MAX_VECT_LEN): Delete.
(expand_vec_perm_d): Add a vec_flags field.
(emit_unspec2, aarch64_expand_sve_vec_perm): New functions.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip)
(aarch64_evpc_ext): Don't apply a big-endian lane correction
for SVE modes.
(aarch64_evpc_rev): Rename to...
(aarch64_evpc_rev_local): ...this. Use a predicated operation for SVE.
(aarch64_evpc_rev_global): New function.
(aarch64_evpc_dup): Enforce a 64-byte range for SVE DUP.
(aarch64_evpc_tbl): Use MAX_COMPILE_TIME_VEC_BYTES instead of
MAX_VECT_LEN.
(aarch64_evpc_sve_tbl): New function.
(aarch64_expand_vec_perm_const_1): Update after rename of
aarch64_evpc_rev. Handle SVE permutes too, trying
aarch64_evpc_rev_global and using aarch64_evpc_sve_tbl rather
than aarch64_evpc_tbl.
(aarch64_vectorize_vec_perm_const): Initialize vec_flags.
(aarch64_sve_cmp_operand_p, aarch64_unspec_cond_code)
(aarch64_gen_unspec_cond, aarch64_expand_sve_vec_cmp_int)
(aarch64_emit_unspec_cond, aarch64_emit_unspec_cond_or)
(aarch64_emit_inverted_unspec_cond, aarch64_expand_sve_vec_cmp_float)
(aarch64_expand_sve_vcond): New functions.
(aarch64_modes_tieable_p): Use aarch64_vector_data_mode_p instead
of aarch64_vector_mode_p.
(aarch64_dwarf_poly_indeterminate_value): New function.
(aarch64_compute_pressure_classes): Likewise.
(aarch64_can_change_mode_class): Likewise.
(TARGET_GET_RAW_RESULT_MODE, TARGET_GET_RAW_ARG_MODE): Redefine.
(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): Likewise.
(TARGET_VECTORIZE_GET_MASK_MODE): Likewise.
(TARGET_DWARF_POLY_INDETERMINATE_VALUE): Likewise.
(TARGET_COMPUTE_PRESSURE_CLASSES): Likewise.
(TARGET_CAN_CHANGE_MODE_CLASS): Likewise.
* config/aarch64/constraints.md (Upa, Upl, Uav, Uat, Usv, Usi, Utr)
(Uty, Dm, vsa, vsc, vsd, vsi, vsn, vsl, vsm, vsA, vsM, vsN): New
constraints.
(Dn, Dl, Dr): Accept const as well as const_vector.
(Dz): Likewise. Compare against CONST0_RTX.
* config/aarch64/iterators.md: Refer to "Advanced SIMD" instead
of "vector" where appropriate.
(SVE_ALL, SVE_BH, SVE_BHS, SVE_BHSI, SVE_HSDI, SVE_HSF, SVE_SD)
(SVE_SDI, SVE_I, SVE_F, PRED_ALL, PRED_BHS): New mode iterators.
(UNSPEC_SEL, UNSPEC_ANDF, UNSPEC_IORF, UNSPEC_XORF, UNSPEC_COND_LT)
(UNSPEC_COND_LE, UNSPEC_COND_EQ, UNSPEC_COND_NE, UNSPEC_COND_GE)
(UNSPEC_COND_GT, UNSPEC_COND_LO, UNSPEC_COND_LS, UNSPEC_COND_HS)
(UNSPEC_COND_HI, UNSPEC_COND_UO): New unspecs.
(Vetype, VEL, Vel, VWIDE, Vwide, vw, vwcore, V_INT_EQUIV)
(v_int_equiv): Extend to SVE modes.
(Vesize, V128, v128, Vewtype, V_FP_EQUIV, v_fp_equiv, VPRED): New
mode attributes.
(LOGICAL_OR, SVE_INT_UNARY, SVE_FP_UNARY): New code iterators.
(optab): Handle popcount, smin, smax, umin, umax, abs and sqrt.
(logical_nn, lr, sve_int_op, sve_fp_op): New code attributs.
(LOGICALF, OPTAB_PERMUTE, UNPACK, UNPACK_UNSIGNED, SVE_COND_INT_CMP)
(SVE_COND_FP_CMP): New int iterators.
(perm_hilo): Handle the new unpack unspecs.
(optab, logicalf_op, su, perm_optab, cmp_op, imm_con): New int
attributes.
* config/aarch64/predicates.md (aarch64_sve_cnt_immediate)
(aarch64_sve_addvl_addpl_immediate, aarch64_split_add_offset_immediate)
(aarch64_pluslong_or_poly_operand, aarch64_nonmemory_operand)
(aarch64_equality_operator, aarch64_constant_vector_operand)
(aarch64_sve_ld1r_operand, aarch64_sve_ldr_operand): New predicates.
(aarch64_sve_nonimmediate_operand): Likewise.
(aarch64_sve_general_operand): Likewise.
(aarch64_sve_dup_operand, aarch64_sve_arith_immediate): Likewise.
(aarch64_sve_sub_arith_immediate, aarch64_sve_inc_dec_immediate)
(aarch64_sve_logical_immediate, aarch64_sve_mul_immediate): Likewise.
(aarch64_sve_dup_immediate, aarch64_sve_cmp_vsc_immediate): Likewise.
(aarch64_sve_cmp_vsd_immediate, aarch64_sve_index_immediate): Likewise.
(aarch64_sve_float_arith_immediate): Likewise.
(aarch64_sve_float_arith_with_sub_immediate): Likewise.
(aarch64_sve_float_mul_immediate, aarch64_sve_arith_operand): Likewise.
(aarch64_sve_add_operand, aarch64_sve_logical_operand): Likewise.
(aarch64_sve_lshift_operand, aarch64_sve_rshift_operand): Likewise.
(aarch64_sve_mul_operand, aarch64_sve_cmp_vsc_operand): Likewise.
(aarch64_sve_cmp_vsd_operand, aarch64_sve_index_operand): Likewise.
(aarch64_sve_float_arith_operand): Likewise.
(aarch64_sve_float_arith_with_sub_operand): Likewise.
(aarch64_sve_float_mul_operand): Likewise.
(aarch64_sve_vec_perm_operand): Likewise.
(aarch64_pluslong_operand): Include aarch64_sve_addvl_addpl_immediate.
(aarch64_mov_operand): Accept const_poly_int and const_vector.
(aarch64_simd_lshift_imm, aarch64_simd_rshift_imm): Accept const
as well as const_vector.
(aarch64_simd_imm_zero, aarch64_simd_imm_minus_one): Move earlier
in file. Use CONST0_RTX and CONSTM1_RTX.
(aarch64_simd_or_scalar_imm_zero): Likewise. Add match_codes.
(aarch64_simd_reg_or_zero): Accept const as well as const_vector.
Use aarch64_simd_imm_zero.
* config/aarch64/aarch64-sve.md: New file.
* config/aarch64/aarch64.md: Include it.
(VG_REGNUM, P0_REGNUM, P7_REGNUM, P15_REGNUM): New register numbers.
(UNSPEC_REV, UNSPEC_LD1_SVE, UNSPEC_ST1_SVE, UNSPEC_MERGE_PTRUE)
(UNSPEC_PTEST_PTRUE, UNSPEC_UNPACKSHI, UNSPEC_UNPACKUHI)
(UNSPEC_UNPACKSLO, UNSPEC_UNPACKULO, UNSPEC_PACK)
(UNSPEC_FLOAT_CONVERT, UNSPEC_WHILE_LO): New unspec constants.
(sve): New attribute.
(enabled): Disable instructions with the sve attribute unless
TARGET_SVE.
(movqi, movhi): Pass CONST_POLY_INT operaneds through
aarch64_expand_mov_immediate.
(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Handle
CNT[BHSD] immediates.
(movti): Split CONST_POLY_INT moves into two halves.
(add<mode>3): Accept aarch64_pluslong_or_poly_operand.
Split additions that need a temporary here if the destination
is the stack pointer.
(*add<mode>3_aarch64): Handle ADDVL and ADDPL immediates.
(*add<mode>3_poly_1): New instruction.
(set_clobber_cc): New expander.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256612
|
||
|
Richard Sandiford
|
11e0322aea |
Mark SLP failures for vect_variable_length
Until SLP support for variable-length vectors is added, many tests fall back to non-SLP vectorisation with permutes. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/testsuite/ * gcc.dg/vect/no-scevccp-slp-30.c: XFAIL SLP test for vect_variable_length, expecting the test to be vectorized without SLP instead. * gcc.dg/vect/pr33953.c: Likewise. * gcc.dg/vect/pr37027.c: Likewise. * gcc.dg/vect/pr67790.c: Likewise. * gcc.dg/vect/pr68445.c: Likewise. * gcc.dg/vect/slp-1.c: Likewise. * gcc.dg/vect/slp-10.c: Likewise. * gcc.dg/vect/slp-12a.c: Likewise. * gcc.dg/vect/slp-12b.c: Likewise. * gcc.dg/vect/slp-12c.c: Likewise. * gcc.dg/vect/slp-13-big-array.c: Likewise. * gcc.dg/vect/slp-13.c: Likewise. * gcc.dg/vect/slp-14.c: Likewise. * gcc.dg/vect/slp-15.c: Likewise. * gcc.dg/vect/slp-17.c: Likewise. * gcc.dg/vect/slp-19b.c: Likewise. * gcc.dg/vect/slp-2.c: Likewise. * gcc.dg/vect/slp-20.c: Likewise. * gcc.dg/vect/slp-21.c: Likewise. * gcc.dg/vect/slp-22.c: Likewise. * gcc.dg/vect/slp-24-big-array.c: Likewise. * gcc.dg/vect/slp-24.c: Likewise. * gcc.dg/vect/slp-28.c: Likewise. * gcc.dg/vect/slp-39.c: Likewise. * gcc.dg/vect/slp-42.c: Likewise. * gcc.dg/vect/slp-6.c: Likewise. * gcc.dg/vect/slp-7.c: Likewise. * gcc.dg/vect/slp-cond-1.c: Likewise. * gcc.dg/vect/slp-cond-2-big-array.c: Likewise. * gcc.dg/vect/slp-cond-2.c: Likewise. * gcc.dg/vect/slp-multitypes-1.c: Likewise. * gcc.dg/vect/slp-multitypes-10.c: Likewise. * gcc.dg/vect/slp-multitypes-12.c: Likewise. * gcc.dg/vect/slp-multitypes-2.c: Likewise. * gcc.dg/vect/slp-multitypes-4.c: Likewise. * gcc.dg/vect/slp-multitypes-5.c: Likewise. * gcc.dg/vect/slp-multitypes-8.c: Likewise. * gcc.dg/vect/slp-multitypes-9.c: Likewise. * gcc.dg/vect/slp-reduc-1.c: Likewise. * gcc.dg/vect/slp-reduc-2.c: Likewise. * gcc.dg/vect/slp-reduc-4.c: Likewise. * gcc.dg/vect/slp-reduc-5.c: Likewise. * gcc.dg/vect/slp-reduc-7.c: Likewise. * gcc.dg/vect/slp-widen-mult-half.c: Likewise. * gcc.dg/vect/vect-live-slp-1.c: Likewise. * gcc.dg/vect/vect-live-slp-2.c: Likewise. * gcc.dg/vect/vect-live-slp-3.c: Likewise. From-SVN: r256611 |
||
|
Richard Sandiford
|
646e47bcd1 |
Extra subreg fold for variable-length CONST_VECTORs
The SVE support for the new CONST_VECTOR encoding needs to be able to extract the first N bits of the vector and duplicate it. This patch adds a simplify_subreg rule for that. The code is covered by the gcc.target/aarch64/sve_slp_*.c tests. 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * simplify-rtx.c (simplify_immed_subreg): Add an inner_bytes parameter and use it instead of GET_MODE_SIZE (innermode). Use inner_bytes * BITS_PER_UNIT instead of GET_MODE_BITSIZE (innermode). Use CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode)) instead of GET_MODE_NUNITS (innermode). Also add a first_elem parameter. Change innermode from fixed_mode_size to machine_mode. (simplify_subreg): Update call accordingly. Handle a constant-sized subreg of a variable-length CONST_VECTOR. From-SVN: r256610 |
||
|
Richard Sandiford
|
729f495ad7 |
Improve canonicalisation of TARGET_MEM_REFs
A general TARGET_MEM_REF is:
BASE + STEP * INDEX + INDEX2 + OFFSET
After classifying the address in this way, the code that builds
TARGET_MEM_REFs tries to simplify the address until it's valid
for the current target and for the mode of memory being addressed.
It does this in a fixed order:
(1) add SYMBOL to BASE
(2) add INDEX * STEP to the base, if STEP != 1
(3) add OFFSET to INDEX or BASE (reverted if unsuccessful)
(4) add INDEX to BASE
(5) add OFFSET to BASE
So suppose we had an address:
&symbol + offset + index * 8
(e.g. a[i + 1] for a global "a") on a target only allows an index or an
offset, not both. Following the steps above, we'd first create:
tmp = symbol
tmp2 = tmp + index * 8
Then if the given offset value was valid for the mode being addressed,
we'd create:
MEM[base:tmp2, offset:offset]
while if it was invalid we'd create:
tmp3 = tmp2 + offset
MEM[base:tmp3, offset:0]
The problem is that this could happen if ivopts had decided to use
a scaled index for an address that happens to have a constant base.
The old procedure failed to give an indexed TARGET_MEM_REF in that case,
and adding the offset last prevented later passes from being able to
fold the index back in.
The patch avoids this by checking at (2) whether the offset is the
only component that causes the address to be invalid, folding it
into the base if so.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssa-address.c (mem_ref_valid_without_offset_p): New function.
(add_offset_to_base): New function, split out from...
(create_mem_ref): ...here. When handling a scale other than 1,
check first whether the address is valid without the offset.
Add it into the base if so, leaving the index and scale as-is.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256609
|
||
|
Jakub Jelinek
|
b4923738ef |
re PR c/83801 ([avr] String constant in __flash not put into .progmem)
PR c/83801 * c-tree.h (decl_constant_value_1): Add a bool argument. * c-typeck.c (decl_constant_value_1): Add IN_INIT argument, allow returning a CONSTRUCTOR if it is true. Use error_operand_p. (decl_constant_value): Adjust caller. * c-fold.c (c_fully_fold_internal): If in_init, pass true to decl_constant_value_1 as IN_INIT. Otherwise, punt if decl_constant_value returns initializer that has BLKmode or array type. (c_fully_fold_internal) <case COMPONENT_REF>: Fold if !lval. * gcc.dg/pr83801.c: New test. From-SVN: r256608 |
||
|
Paul Thomas
|
567a6e1cdb |
re PR fortran/52162 (Bogus -fcheck=bounds with realloc on assignment to unallocated LHS)
2018-01-13 Paul Thomas <pault@gcc.gnu.org> PR fortran/52162 * trans-expr.c (gfc_trans_scalar_assign): Flag is_alloc_lhs if the rhs expression is neither an elemental nor a conversion function. PR fortran/83622 * trans-array.c (is_pointer_array): Remove unconditional return of false for -fopenmp. 2018-01-13 Paul Thomas <pault@gcc.gnu.org> PR fortran/52162 * gfortran.dg/bounds_check_19.f90 : New test. From-SVN: r256607 |
||
|
Thomas Koenig
|
700b62ccf2 |
re PR fortran/83803 (Using -fc-prototypes on modules with empty dummy arg lists does not close paren.)
2018-01-13 Thomas Koenig <tkoenig@gcc.gnu.org> <emsr@gcc.gnu.org> PR fortran/83803 * dump-parse-tree.c (write_proc): Always emit closing parenthesis for functions. From-SVN: r256606 |
||
|
GCC Administrator
|
e8b078f514 |
Daily bump.
From-SVN: r256602 |
||
|
Jakub Jelinek
|
32490940f0 |
re PR c++/83778 (g++.dg/ext/altivec-cell-2.C fails starting with r256448)
PR c++/83778 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Call fold_for_warn before checking if arg2 is INTEGER_CST. From-SVN: r256599 |
||
|
Segher Boessenkool
|
20c89ab7c5 |
rs6000: Remove -mstring
-mstring is only enabled by default on 601, and with -Os on some configurations. It is almost always slower (than not using it) and does not very often lead to smaller code. This patch disables it. If a user uses -mstring he gets a warning (but not with -mno-string). I left the target attribute in place, it just doesn't do anything anymore. The patch also deletes a whole bunch of code. The 'N' and 'O' output modifiers are now unused, but now is not the time to delete them. * config/rs6000/predicates.md (load_multiple_operation): Delete. (store_multiple_operation): Delete. * config/rs6000/rs6000-cpus.def (601): Remove MASK_STRING. * config/rs6000/rs6000-protos.h (rs6000_output_load_multiple): Delete. * config/rs6000/rs6000-string.c (expand_block_move): Delete everything guarded by TARGET_STRING. (rs6000_output_load_multiple): Delete. * config/rs6000/rs6000.c (rs6000_option_override_internal): Delete OPTION_MASK_STRING / TARGET_STRING handling. (print_operand) <'N', 'O'>: Add comment that these are unused now. (const rs6000_opt_masks) <"string">: Change mask to 0. * config/rs6000/rs6000.h (TARGET_DEFAULT): Remove MASK_STRING. (MASK_STRING): Delete. * config/rs6000/rs6000.md (*mov<mode>_string): Delete TARGET_STRING parts. Simplify. (load_multiple): Delete. (*ldmsi8): Delete. (*ldmsi7): Delete. (*ldmsi6): Delete. (*ldmsi5): Delete. (*ldmsi4): Delete. (*ldmsi3): Delete. (store_multiple): Delete. (*stmsi8): Delete. (*stmsi7): Delete. (*stmsi6): Delete. (*stmsi5): Delete. (*stmsi4): Delete. (*stmsi3): Delete. (movmemsi_8reg): Delete. (corresponding unnamed define_insn): Delete. (movmemsi_6reg): Delete. (corresponding unnamed define_insn): Delete. (movmemsi_4reg): Delete. (corresponding unnamed define_insn): Delete. (movmemsi_2reg): Delete. (corresponding unnamed define_insn): Delete. (movmemsi_1reg): Delete. (corresponding unnamed define_insn): Delete. * config/rs6000/rs6000.opt (mno-string): New. (mstring): Replace by deprecation warning stub. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mstring. From-SVN: r256598 |
||
|
Jakub Jelinek
|
02147434d7 |
float128-hw7.c: Use scan-assembler-times instead of scan-assembler-not for xsnabsqp.
* gcc.target/powerpc/float128-hw7.c: Use scan-assembler-times instead of scan-assembler-not for xsnabsqp. From-SVN: r256597 |
||
|
Jakub Jelinek
|
d508a932f1 |
regrename.c (regrename_do_replace): If replacing the same reg multiple times, try to reuse last created gen_raw_REG.
* regrename.c (regrename_do_replace): If replacing the same reg multiple times, try to reuse last created gen_raw_REG. From-SVN: r256596 |
||
|
Jerry DeLisle
|
708c4094ee |
re PR fortran/83525 (open(newunit=funit, status="scratch") fails if an internal file (characters) was read previously.)
2018-01-12 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libgfortran/83525
* gfortran.dg/newunit_5.f90: New test.
From-SVN: r256595
|
||
|
Jason Merrill
|
abdca01e86 |
PR c++/83186 - ICE with static_cast of list-initialized temporary.
* typeck.c (build_static_cast): Use build_non_dependent_expr. From-SVN: r256594 |
||
|
Nathan Sidwell
|
b84619155e |
[C++ PATCH] some reformatting
https://gcc.gnu.org/ml/gcc-patches/2018-01/msg01107.html * cp-tree.h (mark_rvalue_use): Add parm name. * expr.c (mark_lvalue_use, mark_lvalue_use_nonread): Move next to mark_rvalue_use. * call.c (convert_like_real): Fix formatting. From-SVN: r256593 |
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Jakub Jelinek
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8f72ce2cec |
re PR debug/81155 (Debug make check regressions in GCC 8.0)
PR debug/81155 * bb-reorder.c (pass_partition_blocks::gate): In lto don't partition main to workaround a bug in GDB. From-SVN: r256592 |
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Tom de Vries
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52956fbc5d |
Set use_gcc_stdint=wrap for nvptx
2018-01-12 Tom de Vries <tom@codesourcery.com> PR target/83737 * config.gcc (nvptx*-*-*): Set use_gcc_stdint=wrap. From-SVN: r256591 |
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Vladimir Makarov
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0550a77b6e |
re PR rtl-optimization/80481 (Unoptimal additional copy instructions)
2018-01-12 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/80481 * ira-color.c (get_cap_member): New function. (allocnos_conflict_by_live_ranges_p): Use it. (slot_coalesced_allocno_live_ranges_intersect_p): Add assert. (setup_slot_coalesced_allocno_live_ranges): Ditto. 2018-01-12 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/80481 * g++.dg/pr80481.C: New. From-SVN: r256590 |
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Uros Bizjak
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f7aad330fd |
re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha)
PR target/83628 * config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern. (*saddl_se_1): Ditto. (*ssubsi_1): Ditto. (*saddl_se_1): Ditto. testsuite/ChangeLog: PR target/83628 * gcc.target/alpha/pr83628-3.c: New test. From-SVN: r256589 |
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Rainer Orth
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38081436e5 |
Guard against incomplete AVX512F support in Solaris as
* lib/target-supports.exp (check_effective_target_avx512f): Also check for __builtin_ia32_addsd_round, __builtin_ia32_getmantsd_round. * gcc.target/i386/i386.exp (check_effective_target_avx512f): Remove. From-SVN: r256588 |
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Richard Sandiford
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c0a465457b |
Handle polynomial DR_INIT
The idea with the main 107-patch poly_int series (latterly 109-patch)
was to change the mode sizes and vector element counts to poly_int and
then propagate those changes as far as they needed to go to fix build
failures from incompatible types. This means that DR_INIT is now
constructed as a poly_int64:
poly_int64 pbytepos;
if (!multiple_p (pbitpos, BITS_PER_UNIT, &pbytepos))
{
if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "failed: bit offset alignment.\n");
return false;
}
[...]
init = ssize_int (pbytepos);
This patch adjusts other references to DR_INIT accordingly. Unlike
the above, the adjustments weren't needed to avoid a build-time type
incompatibility, but they are needed to make the producer and consumers
of DR_INIT logically consistent.
2018-01-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-predcom.c (aff_combination_dr_offset): Use wi::to_poly_widest
rather than wi::to_widest for DR_INITs.
* tree-vect-data-refs.c (vect_find_same_alignment_drs): Use
wi::to_poly_offset rather than wi::to_offset for DR_INIT.
(vect_analyze_data_ref_accesses): Require both DR_INITs to be
INTEGER_CSTs.
(vect_analyze_group_access_1): Note that here.
From-SVN: r256587
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Richard Sandiford
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cf736b092a |
Handle poly_int vector sizes in get_vec_alignment_for_array_type
get_vectype_for_scalar_type returns a variable-length vector type for SVE, whereas get_vec_alignment_for_array_type assumed it would always be an INTEGER_CST. This is needed to build libstdc++-v3/src/closures.cc for SVE (and probably many other places besides -- this was just the first hit). 2018-01-12 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * tree-vectorizer.c (get_vec_alignment_for_array_type): Handle polynomial type sizes. From-SVN: r256586 |
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Richard Sandiford
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825010bb37 |
Allow variable-sized temporary variables in gimplify.c
This is needed to build libgfortran for SVE. The OpenMP code needs to create temporary vector variables, and the variables will therefore be variable-sized for SVE. Earlier patches made such variables work. 2018-01-12 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * gimplify.c (gimple_add_tmp_var_fn): Allow variables to have a poly_uint64 size, rather than requiring an unsigned HOST_WIDE_INT size. (gimple_add_tmp_var): Likewise. From-SVN: r256585 |
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Martin Liska
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33b366c3d4 |
Fix integer overflow in stats of GIMPLE statements.
2018-01-12 Martin Liska <mliska@suse.cz> * gimple.c (gimple_alloc_counts): Use uint64_t instead of int. (gimple_alloc_sizes): Likewise. (dump_gimple_statistics): Use PRIu64 in printf format. * gimple.h: Change uint64_t to int. From-SVN: r256584 |
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Martin Liska
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00e4d22dc1 |
Fix integer overflow in stats of trees.
2018-01-12 Martin Liska <mliska@suse.cz> * tree-core.h: Use uint64_t instead of int. * tree.c (tree_node_counts): Likewise. (tree_node_sizes): Likewise. (dump_tree_statistics): Use PRIu64 in printf format. From-SVN: r256583 |
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Martin Liska
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b27b31dc2d |
Fix --enable-gather-detailed-mem-stats build.
2018-01-12 Martin Liska <mliska@suse.cz> * Makefile.in: As qsort_chk is implemented in vec.c, add vec.o to linkage of gencfn-macros. * tree.c (build_new_poly_int_cst): Add CXX_MEM_STAT_INFO as it's passing the info to record_node_allocation_statistics. (test_vector_cst_patterns): Add CXX_MEM_STAT_INFO to declaration and pass the info. * ggc-common.c (struct ggc_usage): Add operator== and use it in operator< and compare function. * mem-stats.h (struct mem_usage): Likewise. * vec.c (struct vec_usage): Remove operator< and compare function. Can be simply inherited. From-SVN: r256582 |
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Martin Jambor
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4a0d0ed28f |
Deferring FMA transformations in tight loops
2018-01-12 Martin Jambor <mjambor@suse.cz> PR target/81616 * params.def: New parameter PARAM_AVOID_FMA_MAX_BITS. * tree-ssa-math-opts.c: Include domwalk.h. (convert_mult_to_fma_1): New function. (fma_transformation_info): New type. (fma_deferring_state): Likewise. (cancel_fma_deferring): New function. (result_of_phi): Likewise. (last_fma_candidate_feeds_initial_phi): Likewise. (convert_mult_to_fma): Added deferring logic, split actual transformation to convert_mult_to_fma_1. (math_opts_dom_walker): New type. (math_opts_dom_walker::after_dom_children): New method, body moved here from pass_optimize_widening_mul::execute, added deferring logic bits. (pass_optimize_widening_mul::execute): Moved most of code to math_opts_dom_walker::after_dom_children. * config/i386/x86-tune.def (X86_TUNE_AVOID_128FMA_CHAINS): New. * config/i386/i386.c (ix86_option_override_internal): Added maybe_setting of PARAM_AVOID_FMA_MAX_BITS. From-SVN: r256581 |
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Richard Biener
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80c93fa982 |
re PR debug/83157 (gcc.dg/guality/pr41616-1.c fail, inline instances refer to concrete instance as abstract origin)
2018-01-12 Richard Biener <rguenther@suse.de> PR debug/83157 * dwarf2out.c (gen_variable_die): Do not reset old_die for inline instance vars. From-SVN: r256580 |