* ipa-split.c (struct split_point): Add count.
(consider_split): Do not compute incoming frequency; compute incoming
count and store it to split_point.
(split_function): Set count of the call to split part correctly.
* testsuite/gcc.dg/tree-ssa/fnsplit-2.c: New testcase.
From-SVN: r254720
2017-11-13 Fritz Reese <fritzoreese@gmail.com>
PR fortran/78240
gcc/fortran/ChangeLog:
PR fortran/78240
* decl.c (match_clist_expr): Replace gcc_assert with proper
handling of bad result from spec_size().
* resolve.c (check_data_variable): Avoid NULL dereference when passing
locus to gfc_error.
gcc/testsuite/ChangeLog:
PR fortran/78240
* gfortran.dg/dec_structure_23.f90: New.
* gfortran.dg/pr78240.f90: New.
From-SVN: r254718
gcc/ChangeLog:
2017-11-13 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand.
gcc/testsuite/ChangeLog:
2017-11-13 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file.
From-SVN: r254714
This implements __VA_OPT__, a new preprocessor feature added in C++2A.
The paper can be found here:
http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2017/p0306r4.html
gcc/ChangeLog
* doc/cpp.texi (Variadic Macros): Document __VA_OPT__.
gcc/testsuite/ChangeLog
* c-c++-common/cpp/va-opt-pedantic.c: New file.
* c-c++-common/cpp/va-opt.c: New file.
* c-c++-common/cpp/va-opt-error.c: New file.
libcpp/ChangeLog
* pch.c (cpp_read_state): Set n__VA_OPT__.
* macro.c (vaopt_state): New class.
(_cpp_arguments_ok): Check va_opt flag.
(replace_args, create_iso_definition): Use vaopt_state.
* lex.c (lex_identifier_intern): Possibly issue errors for
__VA_OPT__.
(lex_identifier): Likewise.
(maybe_va_opt_error): New function.
* internal.h (struct lexer_state) <va_args_ok>: Update comment.
(struct spec_nodes) <n__VA_OPT__>: New field.
* init.c (struct lang_flags) <va_opt>: New field.
(lang_defaults): Add entries for C++2A. Update all entries for
va_opt.
(cpp_set_lang): Initialize va_opt.
* include/cpplib.h (struct cpp_options) <va_opt>: New field.
* identifiers.c (_cpp_init_hashtable): Initialize n__VA_OPT__.
From-SVN: r254707
The description of our 1-based column-numbering convention was in
a non-obvious place withn line-map.h; this patch moves it to the top
of that header.
libcpp/ChangeLog:
* include/line-map.h (linenum_type): Move this typedef and the
comment describing column numbering to near the top of the file.
From-SVN: r254703
[gcc]
2017-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* match.pd: Convert fminf<N>, fminf<N>x, fmax<N>, and fmax<N>x
into the min/max operations for _Float<N> and _Float<N>X types.
[gcc/testsuite]
2017-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/float128-minmax.c: New test.
From-SVN: r254702
PR lto/81351
* dwarf2out.c (do_eh_frame): New static variable.
(dwarf2out_begin_prologue): Set it.
(dwarf2out_frame_finish): Test it instead of dwarf2out_do_eh_frame.
From-SVN: r254700
gcc/cp/
Remove the null check from placement new in all modes
* init.c (build_new_1): Don't do a null check for
a namespace-scope non-replaceable placement new
in any mode unless -fcheck-new is provided.
testsuite/
Remove the null check from placement new in all modes
* g++.dg/init/pr35878_1.C: Adjust.
* g++.dg/init/pr35878_4.C: New.
* g++.dg/torture/pr48695.C: Adjust.
* g++.dg/tree-ssa/pr31146-2.C: Likewise.
* g++.dg/tree-ssa/pr41428.C: Adjust.
From-SVN: r254694
PR tree-optimization/78821
* gimple-ssa-store-merging.c (compatible_load_p): Don't require
that bit_not_p is the same.
(imm_store_chain_info::coalesce_immediate_stores): Likewise.
(split_group): Count precisely bit_not_p bits in each statement.
(invert_op): New function.
(imm_store_chain_info::output_merged_store): Use invert_op to
emit BIT_XOR_EXPR with a xor_mask instead of BIT_NOT_EXPR if some
but not all orig_stores have BIT_NOT_EXPR in the corresponding spots.
* gcc.dg/store_merging_15.c: New test.
From-SVN: r254679
2017-11-13 Martin Liska <mliska@suse.cz>
* gcov.c (function_info::is_artificial): New function.
(process_file): Erase all artificial early.
(generate_results): Skip as all artificial are already
removed.
From-SVN: r254673
2017-11-13 Martin Liska <mliska@suse.cz>
* gcov.c (read_graph_file): Store to global vector of functions.
(read_count_file): Iterate the vector.
(process_file): Likewise.
(generate_results): Likewise.
(release_structures): Likewise.
From-SVN: r254672
PR tree-optimization/82954
* gimple-ssa-store-merging.c
(imm_store_chain_info::coalesce_immediate_stores): If
!infof->ops[N].base_addr, split group if info->ops[N].base_addr.
* gcc.c-torture/execute/pr82954.c: New test.
From-SVN: r254671
r254466 failed to update some uses of ENDIAN_LANE_N that were added after
the patch was initially written, which meant that we were treating the
mode number as an element count.
2017-11-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
Upddate call to ENDIAN_LANE_N.
(aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx.
(aarch64_<sur>dot_laneq<vsi2qi>): Likewise.
(*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N
and use aarch64_endian_lane_rtx.
(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
From-SVN: r254670
[gcc]
2017-11-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (bswaphi2_reg): On ISA 3.0 systems,
enable generating XXBRH if the value is in a vector register.
(bswapsi2_reg): On ISA 3.0 systems, enable generating XXBRW if the
value is in a vector register.
(bswapdi2_reg): On ISA 3.0 systems, always use XXBRD to do
register to register bswap64's instead of doing the GPR sequence
used on previous machines.
(bswapdi2_xxbrd): New insn.
(bswapdi2_reg): Disallow on ISA 3.0.
(register to register bswap64 splitter): Do not split the insn on
ISA 3.0 systems that use XXBRD.
[gcc/testsuite]
2017-11-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-xxbr-3.c: New test.
From-SVN: r254643
