2017-10-27 Martin Liska <mliska@suse.cz>
PR gcov-profile/82457
* doc/invoke.texi: Document that one needs a non-strict ISO mode
for fork-like functions to be properly instrumented.
From-SVN: r254137
2017-10-27 Richard Biener <rguenther@suse.de>
PR middle-end/81659
* tree-eh.c (pass_lower_eh_dispatch::execute): Free dominator
info when we redirected EH.
* g++.dg/torture/pr81659.C: New testcase.
From-SVN: r254136
2017-10-26 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64.md(<optab>_trunc><vf><GPI:mode>2):
New pattern.
(<optab>_trunchf<GPI:mode>2: New pattern.
(<optab>_trunc<vgp><GPI:mode>2: New pattern.
* config/aarch64/iterators.md (wv): New mode attribute.
(vf, VF): New mode attributes.
(vgp, VGP): New mode attributes.
(s): Update attribute with SImode and DImode prefixes.
* testsuite/gcc.target/aarch64/fix_trunc1.c: New testcase.
* testsuite/gcc.target/aarch64/vect-vcvt.c: Fix scan-assembler
directives to allow float or integer destination registers for
fcvtz[su].
From-SVN: r254133
[gcc]
2017-10-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/aix.h (TARGET_IEEEQUAD_DEFAULT): Set long double
default to IBM.
* config/rs6000/darwin.h (TARGET_IEEEQUAD_DEFAULT): Likewise.
* config/rs6000/rs6000.opt (-mabi=ieeelongdouble): Move the
warning to rs6000.c. Remove the Undocumented flag, since it has
been documented.
(-mabi=ibmlongdouble): Likewise.
* config/rs6000/rs6000.c (TARGET_IEEEQUAD_DEFAULT): If it is not
already set, set the default format for long double.
(rs6000_debug_reg_global): Print whether long double is IBM or
IEEE.
(rs6000_option_override_internal): Rework setting long double
format. Only warn if the user is changing the long double default
and they did not use -Wno-psabi.
* doc/invoke.texi (PowerPC options): Update the documentation for
-mabi=ieeelongdouble and -mabi=ibmlongdouble.
From-SVN: r254116
This patch adds helper functions that say which of the two modes
involved in a subreg is the larger, preferring the outer mode in
the event of a tie. It also converts IRA and reload to track modes
instead of byte sizes, since this is slightly more convenient when
variable-sized modes are added later.
2017-10-26 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (wider_subreg_mode): New function.
* ira.h (ira_sort_regnos_for_alter_reg): Take a machine_mode *
rather than an unsigned int *.
* ira-color.c (regno_max_ref_width): Replace with...
(regno_max_ref_mode): ...this new variable.
(coalesced_pseudo_reg_slot_compare): Update accordingly.
Use wider_subreg_mode.
(ira_sort_regnos_for_alter_reg): Likewise. Take a machine_mode *
rather than an unsigned int *.
* lra-constraints.c (uses_hard_regs_p): Use wider_subreg_mode.
(process_alt_operands): Likewise.
(invariant_p): Likewise.
* lra-spills.c (assign_mem_slot): Likewise.
(add_pseudo_to_slot): Likewise.
* lra.c (collect_non_operand_hard_regs): Likewise.
(add_regs_to_insn_regno_info): Likewise.
* reload1.c (regno_max_ref_width): Replace with...
(regno_max_ref_mode): ...this new variable.
(reload): Update accordingly. Update call to
ira_sort_regnos_for_alter_reg.
(alter_reg): Update to use regno_max_ref_mode. Call wider_subreg_mode.
(init_eliminable_invariants): Update to use regno_max_ref_mode.
(scan_paradoxical_subregs): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254115
The current frame code combines the separate concepts of a frame chain
(saving old FP,LR in a record and pointing new FP to it) and a frame
pointer used to access locals. Add emit_frame_chain to the aarch64_frame
descriptor and use it in the prolog and epilog code. For now just
initialize it as before, so generated code is identical.
Also correctly set EXIT_IGNORE_STACK. The current AArch64 epilog code
restores SP from FP if alloca is used. If a frame pointer is used but
there is no alloca, SP must remain valid for the epilog to work correctly.
gcc/
* config/aarch64/aarch64.h (EXIT_IGNORE_STACK): Set if alloca is used.
(aarch64_frame): Add emit_frame_chain boolean.
* config/aarch64/aarch64.c (aarch64_frame_pointer_required)
Move eh_return case to aarch64_layout_frame.
(aarch64_layout_frame): Initialize emit_frame_chain.
(aarch64_expand_prologue): Use emit_frame_chain.
From-SVN: r254114
This patch makes some changes to the frame layout in order to simplify
stack probing. We want to use the save of LR as a probe in any non-leaf
function. With shrinkwrapping we may only save LR before a call, so it
is useful to define a fixed location in the callee-saves. So force LR at
the bottom of the callee-saves even with -fomit-frame-pointer.
Also remove a rarely used frame layout that saves the callee-saves first
with -fomit-frame-pointer. Doing so allows the store of LR to be used as
a valid stack probe in all frames.
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame):
Ensure LR is always stored at the bottom of the callee-saves.
Remove rarely used frame layout which saves callee-saves at top of
frame, so the store of LR can be used as a valid probe in all cases.
From-SVN: r254112
In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong
pointed out some addressing inefficiencies due to a recent change in
regcprop (https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00775.html).
This patch improves aarch64_legitimize_address_displacement to split
unaligned offsets of TImode and TFmode accesses. The resulting code
is better and no longer relies on the original regcprop optimization.
For the test we now produce:
add x1, sp, 4
stp xzr, xzr, [x1, 24]
rather than:
mov x1, sp
add x1, x1, 28
stp xzr, xzr, [x1]
gcc/
* config/aarch64/aarch64.c (aarch64_legitimize_address_displacement):
Improve unaligned TImode/TFmode base/offset split.
testsuite/
* gcc.target/aarch64/ldp_stp_unaligned_2.c: New file.
From-SVN: r254111
This patch uses df_read_modify_subreg_p to check whether writing
to a subreg would preserve some of the existing contents.
This has the effect of putting more emphasis on the
REGMODE_NATURAL_SIZE-based definition of whether something can be
partially modified, instead of using UNITS_PER_WORD unconditionally.
This becomes important for SVE, where UNITS_PER_WORD has no
significance for subregs of multi-register LD2/ST2, LD3/ST3 and
LD4/ST4 tuples.
2017-10-26 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* caller-save.c (mark_referenced_regs): Use read_modify_subreg_p.
* combine.c (find_single_use_1): Likewise.
(expand_field_assignment): Likewise.
(move_deaths): Likewise.
* lra-constraints.c (simplify_operand_subreg): Likewise.
(curr_insn_transform): Likewise.
* lra.c (collect_non_operand_hard_regs): Likewise.
(add_regs_to_insn_regno_info): Likewise.
* rtlanal.c (reg_referenced_p): Likewise.
(covers_regno_no_parallel_p): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254110
2017-10-26 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* wide-int-print.cc (print_hex): Loop based on extract_uhwi.
Don't print any bits outside the precision of the value.
* wide-int.cc (test_printing): Add some new tests.
From-SVN: r254109
After r254010 we now add -gcolumn-info by default, that means the tests
in gcc.target/arm/require-pic-register-loc.c need adjusting to not expect
to see column zero.
gcc/testsuite/
* gcc.target/arm/require-pic-register-loc.c: Use wider regex for
column information.
From-SVN: r254106
TARGET_STATIC_RTX_ALIGNMENT
This patch adds a new hook that gives the preferred alignment for
a static rtx, so that we don't need to query the front end in
force_const_mem.
2017-10-26 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* target.def (static_rtx_alignment): New hook.
* targhooks.h (default_static_rtx_alignment): Declare.
* targhooks.c (default_static_rtx_alignment): New function.
* doc/tm.texi.in (TARGET_STATIC_RTX_ALIGNMENT): New hook.
* doc/tm.texi: Regenerate.
* varasm.c (force_const_mem): Use targetm.static_rtx_alignment
instead of targetm.constant_alignment. Remove call to
set_mem_attributes.
* config/cris/cris.c (TARGET_STATIC_RTX_ALIGNMENT): Redefine.
(cris_preferred_mininum_alignment): New function, split out from...
(cris_constant_alignment): ...here.
(cris_static_rtx_alignment): New function.
* config/i386/i386.c (ix86_static_rtx_alignment): New function,
split out from...
(ix86_constant_alignment): ...here.
(TARGET_STATIC_RTX_ALIGNMENT): Redefine.
* config/mmix/mmix.c (TARGET_STATIC_RTX_ALIGNMENT): Redefine.
(mmix_static_rtx_alignment): New function.
* config/spu/spu.c (spu_static_rtx_alignment): New function.
(TARGET_STATIC_RTX_ALIGNMENT): Redefine.
From-SVN: r254102
c_parser_declaration_or_fndef has logic for parsing what might be
either a declaration or a function definition.
This patch adds a test to detect cases where a semicolon would have
terminated the decls as a declaration, where the token that follows
would start a new declaration specifier, and updates the error message
accordingly, with a fix-it hint.
This addresses PR c/7356, fixing the case of a stray token before a
#include that previously gave inscrutable output, and improving e.g.:
int i
int j;
from:
t.c:2:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'int'
int j;
^~~
to:
t.c:1:6: error: expected ';' before 'int'
int i
^
;
int j;
~~~
gcc.dg/noncompile/920923-1.c needs a slight update, as the output for
the first line changes from:
920923-1.c:2:14: error: expected '=', ',', ';', 'asm' or
'__attribute__' before 'unsigned'
typedef BYTE unsigned char; /* { dg-error "expected" } */
^~~~~~~~
to:
920923-1.c:2:13: error: expected ';' before 'unsigned'
typedef BYTE unsigned char; /* { dg-error "expected" } */
^~~~~~~~~
;
920923-1.c:2:1: warning: useless type name in empty declaration
typedef BYTE unsigned char; /* { dg-error "expected" } */
^~~~~~~
The patch also adds a test for PR c/44515 as a baseline.
gcc/c/ChangeLog:
PR c/7356
* c-parser.c (c_parser_declaration_or_fndef): Detect missing
semicolons.
gcc/testsuite/ChangeLog:
PR c/7356
PR c/44515
* c-c++-common/pr44515.c: New test case.
* gcc.dg/pr7356-2.c: New test case.
* gcc.dg/pr7356.c: New test case.
* gcc.dg/spellcheck-typenames.c: Update the "singed" char "TODO"
case to reflect changes to output.
* gcc.dg/noncompile/920923-1.c: Add dg-warning to reflect changes
to output.
From-SVN: r254093
Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns. This corrects the problem, and adds
a zero-extending pattern as well.
gcc/ChangeLog
2017-10-25 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
* config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
mark as a sign-extending load.
(local_pic_load_u): Define.
From-SVN: r254092
PR middle-end/82062
* fold-const.c (operand_equal_for_comparison_p): Also return true
if ARG0 is a simple variant of ARG1 with narrower precision.
(fold_ternary_loc): Always pass unstripped operands to the predicate.
From-SVN: r254089
PR libstdc++/82716
* include/std/array (tuple_size, tuple_element): Change class-key
from class to struct, to avoid annoying Clang warnings.
From-SVN: r254077
2017-10-25 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.h (vn_eliminate): Declare.
* tree-ssa-pre.c (class eliminate_dom_walker, eliminate,
class pass_fre): Move to ...
* tree-ssa-sccvn.c (class eliminate_dom_walker, vn_eliminate,
class pass_fre): ... here and adjust for statistics.
From-SVN: r254074
2017-10-25 Tom de Vries <tom@codesourcery.com>
* gcc.dg/tree-ssa/loop-1.c: Add xfail for nvptx in scan-assembler-times
line, and add nvptx-specific version.
From-SVN: r254071
