libgcc/ChangeLog:
PR gcov-profile/98739
* libgcov.h (gcov_topn_add_value): Do not train when
we have a merged profile with a negative number of total
value.
This allows the openrisc softfloat implementation to set exceptions.
This also sets the correct tininess after rounding value to be
consistent with hardware and simulator implementations.
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (FP_RND_NEAREST, FP_RND_ZERO,
FP_RND_PINF, FP_RND_MINF, FP_RND_MASK, FP_EX_OVERFLOW,
FP_EX_UNDERFLOW, FP_EX_INEXACT, FP_EX_INVALID, FP_EX_DIVZERO,
FP_EX_ALL): New constant macros.
(_FP_DECL_EX, FP_ROUNDMODE, FP_INIT_ROUNDMODE,
FP_HANDLE_EXCEPTIONS): New macros.
(_FP_TININESS_AFTER_ROUNDING): Change to 1.
When the application sets SA_SIGINFO, the signal trampoline parameters
are different to follow POSIX.
libgcc/
* config/i386/gnu-unwind.h (x86_gnu_fallback_frame_state): Add the
posix siginfo case to struct handler_args. Detect between legacy
and siginfo from the second parameter, which is a small sigcode in
the legacy case, and a pointer in the siginfo case.
If you use a compiler with long double defaulting to 64-bit instead of 128-bit
with IBM extended double, you get linker warnings about mis-matches in the gnu
attributes for long double (PR libgcc/97543). Even if the compiler is
configured to have long double be 64 bit as the default with the configuration
option '--without-long-double-128' you get the warnings.
You also get the same issues if you use a compiler with long double defaulting
to IEEE 128-bit instead of IBM extended double (PR libgcc/97643).
The issue is the way libgcc.a/libgcc.so is built. Right now when building
libgcc under Linux, the long double size is set to 128-bits when building
libgcc. However, the gnu attributes are set, leading to the warnings.
One feature of the current GNU attribute implementation is if you have a shared
library (such as libgcc_s.so), the GNU attributes for the shared library is an
inclusive OR of all of the objects within the library. This means if any
object file that uses the -mlong-double-128 option and uses long double, the GNU
attributes for the library will indicate that it uses 128-bit IBM long
doubles. If you have a static library, you will get the warning only if you
actually reference an object file with the attribute set.
This patch does two things:
1) All of the object files that support IBM 128-bit long doubles
explicitly set the ABI to IBM extended double.
2) I turned off GNU attributes for building the shared library or for
building the IBM 128-bit long double support.
libgcc/
2020-12-03 Michael Meissner <meissner@linux.ibm.com>
PR libgcc/97543
PR libgcc/97643
* config/rs6000/t-linux (IBM128_STATIC_OBJS): New make variable.
(IBM128_SHARED_OBJS): New make variable.
(IBM128_OBJS): New make variable. Set all objects to use the
explicit IBM format, and disable gnu attributes.
(IBM128_CFLAGS): New make variable.
(gcc_s_compile): Add -mno-gnu-attribute to all shared library
modules.
This patch introduces maybe_emit_call_builtin___clear_cache for the
builtin expander machinery and the trampoline initializers to use to
clear the instruction cache, removing a source of inconsistencies and
subtle errors in low-level machinery.
I've adjusted all trampoline_init implementations that used to issue
explicit calls to __clear_cache or similar to use this new primitive.
Specifically on vxworks targets, we needed to drop the __clear_cache
symbol in libgcc, for reasons related with linking that I didn't need
to understand, and we wanted to call cacheTextUpdate directly, despite
the different calling conventions: the second argument is a length
rather than the end address.
So I introduced a target hook to enable target OS-level overriding of
builtin __clear_cache call emission, retaining nearly (*) the same
logic to govern the decision on whether to emit a call (or nothing, or
a machine-dependent insn) but enabling a call to a target
system-defined function with different calling conventions to be
issued, without having to modify .md files of the various
architectures supported by the target system to introduce or modify
clear_cache insns.
(*) I write "nearly" mainly because, when not optimizing, we'd issue a
call regardless, but since the call may now be overridden, I added it
to the set of builtins that are not directly turned into calls when
not optimizing, following the normal expansion path instead. It
wouldn't be hard to skip the emission of cache-clearing insns when not
optimizing, but it didn't seem very important, especially for the new
uses from trampoline init.
Another difference that might be relevant is that now we expand
the begin and end arguments unconditionally. This might make a
difference if they have side effects. That's prettty much impossible
at expand time, but I thought I'd mention it.
I have NOT modified targets that did not issue cache-clearing calls in
trampoline init to use the new clear_cache-calling infrastructure even
if it would expand to nothing. I have considered doing so, to have
__builtin___clear_cache and trampoline init call cacheTextUpdate on
all vxworks targets, but decided not to, since on targets that don't
do any cache clearing, cacheTextUpdate ought to be a no-op, even
though rs6000 seems to use icbi and dcbf instructions in the function
called to initialize a trampoline, but AFAICT not in the __clear_cache
builtin. Hopefully target maintainers will have a look and take
advantage of this new piece of infrastructure to remove such
(apparent?) inconsistencies. Not rs6000 and other that call asm-coded
trampoline setup instructions, for sure, but they might wish to
introduce a CLEAR_INSN_CACHE macro or a clear_cache expander if they
don't have one.
for gcc/ChangeLog
* builtins.c (default_emit_call_builtin___clear_cache): New.
(maybe_emit_call_builtin___clear_cache): New.
(expand_builtin___clear_cache): Split into the above.
(expand_builtin): Do not issue clear_cache call any more.
* builtins.h (maybe_emit_call_builtin___clear_cache): Declare.
* config/aarch64/aarch64.c (aarch64_trampoline_init): Use
maybe_emit_call_builtin___clear_cache.
* config/arc/arc.c (arc_trampoline_init): Likewise.
* config/arm/arm.c (arm_trampoline_init): Likewise.
* config/c6x/c6x.c (c6x_initialize_trampoline): Likewise.
* config/csky/csky.c (csky_trampoline_init): Likewise.
* config/m68k/linux.h (FInALIZE_TRAMPOLINE): Likewise.
* config/tilegx/tilegx.c (tilegx_trampoline_init): Likewise.
* config/tilepro/tilepro.c (tilepro_trampoline_init): Ditto.
* config/vxworks.c: Include rtl.h, memmodel.h, and optabs.h.
(vxworks_emit_call_builtin___clear_cache): New.
* config/vxworks.h (CLEAR_INSN_CACHE): Drop.
(TARGET_EMIT_CALL_BUILTIN___CLEAR_CACHE): Define.
* target.def (trampoline_init): In the documentation, refer to
maybe_emit_call_builtin___clear_cache.
(emit_call_builtin___clear_cache): New.
* doc/tm.texi.in: Add new hook point.
(CLEAR_CACHE_INSN): Remove duplicate 'both'.
* doc/tm.texi: Rebuilt.
* targhooks.h (default_meit_call_builtin___clear_cache):
Declare.
* tree.h (BUILTIN_ASM_NAME_PTR): New.
for libgcc/ChangeLog
* config/t-vxworks (LIB2ADD): Drop.
* config/t-vxworks7 (LIB2ADD): Likewise.
* config/vxcache.c: Remove.
Disable USE_PT_GNU_EH_FRAME frame unwinder support for old OS versions,
fixing compilation errors:
.../libgcc/unwind-dw2-fde-dip.c:75:21: error: unknown type name 'Elf_Phdr'
75 | # define ElfW(type) Elf_##type
| ^~~~
.../libgcc/unwind-dw2-fde-dip.c:132:9: note: in expansion of macro 'ElfW'
132 | const ElfW(Phdr) *p_eh_frame_hdr;
| ^~~~
.../libgcc/unwind-dw2-fde-dip.c:75:21: error: unknown type name 'Elf_Phdr'
75 | # define ElfW(type) Elf_##type
| ^~~~
.../libgcc/unwind-dw2-fde-dip.c:133:9: note: in expansion of macro 'ElfW'
133 | const ElfW(Phdr) *p_dynamic;
| ^~~~
.../libgcc/unwind-dw2-fde-dip.c:165:37: warning: 'struct dl_phdr_info' declared inside parameter list will not be visible outside of this definition or declaration
165 | _Unwind_IteratePhdrCallback (struct dl_phdr_info *info, size_t size, void *ptr)
| ^~~~~~~~~~~~
[...]
and producing a working cross-compiler at least with VAX/NetBSD 1.6.2.
libgcc/
* unwind-dw2-fde-dip.c [__OpenBSD__ || __NetBSD__]
(USE_PT_GNU_EH_FRAME): Do not define if !TARGET_DL_ITERATE_PHDR.
Hardware multipliers that support widening 32-bit multiplication can
be used to perform a 64-bit * 64-bit multiplication more efficiently
than a software implementation.
The following equation is used to perform 64-bit multiplication for
devices with "32bit" or "f5series" hardware multiply versions:
64bit_result = (low32_op0 * lop32_op1)
+ ((low32_op0 * high32_op1) << 32)
+ ((high32_op0 * low32_op1) << 32)
libgcc/ChangeLog:
* config/msp430/lib2hw_mul.S (mult64_hw): New.
(if MUL_32): Use mult64_hw for __muldi3.
(if MUL_F5): Use mult64_hw for __muldi3.
* config/msp430/lib2mul.c (__muldi3): New.
* config/msp430/t-msp430 (LIB2FUNCS_EXCLUDE): Define.
This patch retires ppc64-fp.c in favour of using
"LIB2_SIDITI_CONV_FUNCS = yes", which is a lot better solution than
having a copy of selected libgcc2.c functions.
* config/rs6000/t-ppc64-fp (LIB2ADD): Delete.
(LIB2_SIDITI_CONV_FUNCS): Define.
* config/rs6000/ppc64-fp.c: Delete file.
The naming scheme used by GCC to reference MSP430 hardware multiply
library functions is inconsistent.
Sometimes the "GCC" names (e.g. mulsi2) are used, other times the
"MSPABI" names (e.g. __mspabi_mpyl) are used.
Also, sometimes an identifier for the hardware multiply support is
appended to the GCC name, when the functions are defined, but this is
not required.
This patch fixes those issues, so the names used to refer to the
hardware multiply library functions follow a consistent pattern.
gcc/ChangeLog:
* config/msp430/msp430.c (msp430_output_labelref): Don't process mspabi
hwmult library function names into GCC-style names.
libgcc/ChangeLog:
* config/msp430/lib2hw_mul.S: Omit _hw* suffix from GCC names for
hwmult library functions.
gcc/testsuite/ChangeLog:
* gcc.target/msp430/rtx-cost-Os-f5series.c: Adjust test to use new
hwmult library function name.
This adds ${cpu_type}/t-lse and t-slibgcc-libgcc to the tmake_file
list for aarch64-vxworks7* configurations, as the Linux port does.
t-lse is needed by all triplets now anyway and the standard setting
for slibgcc makes sense as we are working on reintroducing PIC support
for RTPs on various targets. The VxWorks7 system environments are leaning
towards more and more similarilties with Linux in general, so the
closer configurations the better.
2020-11-02 Pat Bernardi <bernardi@adacore.com>
libgcc/
* config.host (aarch64-vxworks7*, tmake_file): Add
${cpu_type}/t-lse and t-slibgcc-libgcc.
Co-authored-by: Olivier Hainque <hainque@adacore.com>
Previously, the SEH version of _Unwind_Backtrace did unwind
the stack and call the provided callback function as intended,
but there was little the caller could do within the callback to
actually get any info about that particular level in the unwind.
Set the ra and cfa pointers, which are used by _Unwind_GetIP
and _Unwind_GetCFA, to allow using these functions from the
callacb to inspect the state at each stack frame.
2020-09-08 Martin Storsjö <martin@martin.st>
libgcc/
* unwind-seh.c (_Unwind_Backtrace): Set the ra and cfa pointers
before calling the callback.
This change extends the VxWorks support on intel CPUs to
VxWorks7r2 for x86_64 as well as x86, with a "mcmodel=large"
additional multilib for the 64bit configuration.
The support for fPIC is not functional yet for this model,
so we just don't add the corresponding multilib.
We extend the range of CPU families handled by TARGET_OS_CPP_BUILTINS,
accounting for the fact that archs older than PENTIUM4 are
not supported (any more) by VxWorks 7.
As we did for powerpc, we leverage VX_CPU_PREFIX to emit different
forms of definitions for different families of VxWorks as the system
headers's expectations has evolved between Vx 5, 6 and 7.
2020-10-27 Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc: Adjust the ix86/x86_64-wrs-vxworks filters
to apply to VxWorks 7 as well.
* config/i386/t-vxworks (MULTILIB_OPTIONS, MULTILIB_DIRNAMES):
Remove the fPIC multilib and add one for the large code model
on x86_64.
* config/i386/vxworks.h: Separate sections for TARGET_VXWORKS7,
other variants and common bits.
(TARGET_OS_CPP_BUILTINS): Augment to support a range of CPU
families. Leverage VX_CPU_PREFIX.
(CC1_SPEC): Add definition.
(STACK_CHECK_PROTECT): Use conditional expression instead of
heavier to read conditioned macro definitions.
libgcc/
* config.host: Adjust the ix86/x86_64-wrs-vxworks filters
to apply to VxWorks 7 as well.
Co-authored-by: Douglas Rupp <rupp@adacore.com>
Co-authored-by: Pat Bernardi <bernardi@adacore.com>
Fix a basic #if/#ifdef confusion which leads to improper
choices in some configurations.
2020-10-28 Olivier Hainque <hainque@adacore.com>
libgcc/
* config/gthr-vxworks-tls.c: Fix preprocessor logic
controlling the definition of VX_ENTER_TLS_DTOR and
VX_LEAVE_TLS_DTOR based on a version major check.
This fixes the name of the macro used to condition the
inclusion of an actual implementation of some of the gthread
support services for VxWorks, to agree with the side
defining that macro based on tests against the targetted
VxWorks version major.
2020-10-28 Olivier Hainque <hainque@adacore.com>
libgcc/
* config/gthr-vxworks-thread.c: Fix name of macro used
to condition the inclusion of an actual implementation.
gcc/ChangeLog:
PR gcov-profile/97461
* gcov-io.h (GCOV_PREALLOCATED_KVP): Pre-allocate 64
static counters.
libgcc/ChangeLog:
PR gcov-profile/97461
* libgcov.h (gcov_counter_add): Use first static counters
as it should help to have malloc wrappers set up.
gcc/testsuite/ChangeLog:
PR gcov-profile/97461
* gcc.dg/tree-prof/pr97461.c: New test.
The tests for macros possibly defined in gthr.h needs to
be performed after the corresponding #include. This was tested
together with the previous updates to gthr-vxworks-thread.c
and gthr-vxworks-cond.c and was meant to be squashed with them.
2010-10-23 Rasmus Villemoes <rv@rasmusvillemoes.dk>
libgcc/
* config/gthr-vxworks-thread.c: #include gthr.h before
testing the guard defined there.
* config/gthr-vxworks-cond.c: Likewise.
As mentioned in the PR, since 2005 we reject if array elements are smaller
than their alignment (i.e. overaligned elements), because such arrays don't
make much sense, only their first element is guaranteed to be aligned as
user requested, but the next element can't be.
The following testcases show something we've been silent about but is
equally bad, the 2005 case is just the most common special case of that
the array element size is not divisible by the alignment. In those arrays
too only the first element is guaranteed to be properly aligned and the
second one can't be.
This patch rejects those cases too, but keeps the existing wording for the
old common case.
Unfortunately, the patch breaks bootstrap, because libbid uses this mess
(forms arrays with 24 byte long elements with 16 byte element alignment).
I don't really see justification for that, so I've decreased the alignment
to 8 bytes instead.
2020-10-23 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/97164
gcc/
* stor-layout.c (layout_type): Also reject arrays where element size
is constant, but not a multiple of element alignment.
gcc/testsuite/
* c-c++-common/pr97164.c: New test.
* gcc.c-torture/execute/pr36093.c: Move ...
* gcc.dg/pr36093.c: ... here. Add dg-do compile and dg-error
directives.
* gcc.c-torture/execute/pr43783.c: Move ...
* gcc.dg/pr43783.c: ... here. Add dg-do compile, dg-options and
dg-error directives.
libgcc/config/libbid/
* bid_functions.h (UINT192): Decrease alignment to 8 bytes.
This change introduces support for the most recent versions
of VxWorks on PowerPC targets, for both 32 and 64 bit thanks
to a bi-arch setup.
The system compilers are essentially configured as Linux
toolchains with only a few specificities and we replicate
that model here.
The most visible specificities are the use of secureplt by
default, the pre-definition of some macros that the system
headers still rely on (_VX_CPU and _VX_CPU_FAMILY, for example),
and of course some variations related to the so VxWorks typical
kernel vs RTP mode distinction.
In addition to the introduction of config.gcc and libgcc
configuration chunks, much inspired by the linux ones, the
change
- Reworks rs6000/vxworks.h file to feature bits common to the
Vx6 and Vx7 port then a separate section for each, where the
Vx7 part is very short as we rely on the Linux definitions
for most things.
- Adjusts the CPU macro predefinitions in CPP_SPEC to resort
to "_VX_CPU" instead of "CPU" for Vx7, to better match the
more recent system headers expectations,
- Adds a cpu definition case for e6500.
- Changes to the use SUB3TARGET_OVERRIDE_OPTIONS instead of
SUBSUBTARGET_OVERRIDE_OPTIONS for specifics, so we don't
override the Linux's version of the latter for vx7.
2020-10-20 Douglas Rupp <rupp@adacore.com>
gcc/
* config.gcc (powerpc*-wrs-vxworks7r*): New case.
* config/rs6000/vxworks.h: Rework to handle VxWorks7.
Refactor as common bits + vx6 vs vx7 ones. For the
latter, rely essentially on the Linux configuration
and adjust CPU to _VX_CPU in CPP_SPEC. Add a case
for e6500. Use SUB3TARGET_OVERRIDE_OPTIONS for specifics
to preserve the Linux SUBSUBTARGET_OVERRIDE_OPTIONS
for vx7.
libgcc/
* config.host (powerpc*-wrs-vxworks7*): New case.
* configure.ac: Handle powerpc*-*-vxworks7* as
powerpc*-*-linux* for ppc-fp_type.
* configure: Regenerate.
Co-authored-by: Olivier Hainque <hainque@adacore.com>
As for condition variables, the C++0x threads support relies on
VxWorks entry points not available in VxWorks versions prior to 6.
We just expose absence of support for C++0x threads on such systems.
2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk>
libgcc/
* config/gthr-vxworks.h: Condition the ___GTHREADS_CXX0X
section on VxWorks >= 6.
* config/gthr-vxworks-thread.c: Condition the entire
implementation on __GTHREAD_CXX0X.
The condition variables support relies on kernel entry points
to enforce critical aspects of it's expected behavior.
Some of these entry points are not available prior to VxWorks 6,
so we just expose absence of support for condition variables on
such systems.
2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk>
libgcc/
* config/gthr-vxworks.h: Condition the __GTHREAD_HAS_COND
section on VxWorks >= 6.
* config/gthr-vxworks-cond.c: Condition the entire
implementation on __GTHREAD_HAS_COND.
This fixes an oversight and addresses a few build time warnings.
2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk>
libgcc/
* config/gthr-vxworks.c: #include <taskLib.h>.
As of today, the __gthread_enter/leave entry points are
only meaningful on VxWorks 6. Refactor the VX_ENTER_TLS_DTOR
macros accordingly.
2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk>
libgcc/
* config/gthr-vxworks-tls.c (VX_ENTER_TLS_DTOR): Nil
except on VxWorks 6.
Co-authored-by: Olivier Hainque <hainque@adacore.com>
The ports that support RTPs achieve the kernel/rtp compilation
and link distinction through the multilib mechanism.
This patch just removes the bogus explicit extraneous
materialization of this distinction in the common VxWorks
configuration files and leaves the rtp specialization all
to the multilib machinery.
2020-10-15 Olivier Hainque <hainque@adacore.com>
libgcc/
* config/t-vxcrtstuff: Remove the -kernel/-rtp specialization.
gcc/
* config/vxworks.h (VX_CRTBEGIN_SPEC): Likewise.
This change reworks the condition variables support for VxWorks
to address the very legit points raised by Rasmus in
https://gcc.gnu.org/pipermail/gcc/2020-May/232524.html
While some of the issues were taken care of by the use of semFlush,
a few others were indeed calling for adjustments.
We first considered resorting to the condvarLib library available
in VxWorks7. Unfortunately, it is vx7 only and we wanted something working
for at least vx 6.9 as well. It also turned out requiring the use of
recursive mutexes for condVarWait, which seemed unnecessarily constraining.
Instead, this change corrects the sequencing logic in a few places and
leverages the semExchange API to ensure the key atomicity requirement on
cond_wait operations.
2020-10-14 Alexandre Oliva <oliva@adacore.com>
libgcc/
* config/gthr-vxworks-thread.c: Include stdlib.h.
(tls_delete_hook): Prototype it.
(__gthread_cond_signal): Return early if no waiters. Consume
signal in case the semaphore got full. Use semInfoGet instead
of kernel-mode-only semInfo.
(__gthread_cond_timedwait): Use semExchange. Always take the
mutex again before returning.
* config/gthr-vxworks-cond.c (__ghtread_cond_wait): Likewise.
This is useful to handle ports where we might arrange to use
different sets of fixed headers for different multilibs, typically
for kernel vs rtp modes.
2020-10-14 Olivier Hainque <hainque@adacore.com>
libgcc/
* config/t-vxworks (LIBGCC2_INCLUDES): Append
$(MULTISUBDIR) to the -I path for fixed headers, as we
arrange to have different sets of such headers for different
multilibs when they are activated.
* config/t-vxworks7: Likewise.
The special vxworks rules for the compilation of libgcc had
-I.../gcc/include and not .../gcc/include-fixed, causing build
failure of our arm-vxworks7r2 port because of indirect dependencies
on limits.h.
The omission was just an oversight and this change just adds the
missing -I.
2020-10-14 Olivier Hainque <hainque@adacore.com>
libgcc/
* config/t-vxworks: Add include-fixed to include search
paths for libgcc on VxWorks.
* config/t-vxworks7: Likewise.
For sources which can't use any vector instructions, <x86intrin.h> and
<immintrin.h> cannot be included for compiler intrinsics:
$ echo "#include <x86intrin.h>" | gcc -S -O2 -mno-sse -mno-mmx -x c -
In file included from /usr/include/stdlib.h:1013,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/mm_malloc.h:27,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/xmmintrin.h:34,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:29,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32,
from <stdin>:1:
/usr/include/bits/stdlib-float.h: In function ‘atof’:
/usr/include/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled
26 | {
| ^
$
libgcc/config/i386/shadow-stack-unwind.h has a workaround:
/* NB: We need _get_ssp and _inc_ssp from <cetintrin.h>. But we can't
include <x86intrin.h> which ends up including <mm_malloc.h>, which
includes <stdlib.h> and <errno.h> unconditionally. But we can't
include any libc system headers unconditionally from libgcc. Avoid
including <mm_malloc.h> here by defining _IMMINTRIN_H_INCLUDED. */
#define _IMMINTRIN_H_INCLUDED
#include <cetintrin.h>
#undef _IMMINTRIN_H_INCLUDED
Add a standalone intrinsic header file, <x86gprintrin.h>, to provide
integer only intrinsics. All integer only intrinsics are placed in
<x86gprintrin.h>. <x86intrin.h> and <immintrin.h> simply include
<x86gprintrin.h>.
gcc/
PR target/97148
* config.gcc (extra_headers): Add x86gprintrin.h.
* config/i386/adxintrin.h: Check _X86GPRINTRIN_H_INCLUDED for
<x86gprintrin.h>.
* config/i386/bmi2intrin.h: Likewise.
* config/i386/bmiintrin.h: Likewise.
* config/i386/cetintrin.h: Likewise.
* config/i386/cldemoteintrin.h: Likewise.
* config/i386/clflushoptintrin.h: Likewise.
* config/i386/clwbintrin.h: Likewise.
* config/i386/enqcmdintrin.h: Likewise.
* config/i386/fxsrintrin.h: Likewise.
* config/i386/ia32intrin.h: Likewise.
* config/i386/lwpintrin.h: Likewise.
* config/i386/lzcntintrin.h: Likewise.
* config/i386/movdirintrin.h: Likewise.
* config/i386/pconfigintrin.h: Likewise.
* config/i386/pkuintrin.h: Likewise.
* config/i386/rdseedintrin.h: Likewise.
* config/i386/rtmintrin.h: Likewise.
* config/i386/serializeintrin.h: Likewise.
* config/i386/tbmintrin.h: Likewise.
* config/i386/tsxldtrkintrin.h: Likewise.
* config/i386/waitpkgintrin.h: Likewise.
* config/i386/wbnoinvdintrin.h: Likewise.
* config/i386/xsavecintrin.h: Likewise.
* config/i386/xsaveintrin.h: Likewise.
* config/i386/xsaveoptintrin.h: Likewise.
* config/i386/xsavesintrin.h: Likewise.
* config/i386/xtestintrin.h: Likewise.
* config/i386/immintrin.h: Include <x86gprintrin.h> instead of
<fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>,
<xsavesintrin.h>, <xsavecintrin.h>, <lzcntintrin.h>,
<bmiintrin.h>, <bmi2intrin.h>, <xtestintrin.h>, <cetintrin.h>,
<movdirintrin.h>, <sgxintrin.h, <pconfigintrin.h>,
<waitpkgintrin.h>, <cldemoteintrin.h>, <enqcmdintrin.h>,
<serializeintrin.h>, <tsxldtrkintrin.h>, <adxintrin.h>,
<clwbintrin.h>, <clflushoptintrin.h>, <wbnoinvdintrin.h> and
<pkuintrin.h>.
(_wbinvd): Moved to config/i386/x86gprintrin.h.
(_rdrand16_step): Likewise.
(_rdrand32_step): Likewise.
(_rdpid_u32): Likewise.
(_readfsbase_u32): Likewise.
(_readfsbase_u64): Likewise.
(_readgsbase_u32): Likewise.
(_readgsbase_u64): Likewise.
(_writefsbase_u32): Likewise.
(_writefsbase_u64): Likewise.
(_writegsbase_u32): Likewise.
(_writegsbase_u64): Likewise.
(_rdrand64_step): Likewise.
(_ptwrite64): Likewise.
(_ptwrite32): Likewise.
* config/i386/x86gprintrin.h: New file.
* config/i386/x86intrin.h: Include <x86gprintrin.h>. Don't
include <ia32intrin.h>, <lwpintrin.h>, <tbmintrin.h>,
<popcntintrin.h>, <mwaitxintrin.h> and <clzerointrin.h>.
gcc/testsuite/
* gcc.target/i386/avx-1.c (__builtin_ia32_lwpval32): New to
support <lwpintrin.h> included in <x86gprintrin.h>.
(__builtin_ia32_lwpval64): Likewise.
(__builtin_ia32_lwpins32): Likewise.
(__builtin_ia32_lwpins64): Likewise.
(__builtin_ia32_bextri_u32): New to support <tbmintrin.h>
included in <x86gprintrin.h>.
(__builtin_ia32_bextri_u64): Likewise.
* gcc.target/i386/x86gprintrin-1.c: New test.
* gcc.target/i386/x86gprintrin-2.c: Likewise.
* gcc.target/i386/x86gprintrin-3.c: Likewise.
* gcc.target/i386/x86gprintrin-4.c: Likewise.
* gcc.target/i386/x86gprintrin-4a.c: Likewise.
* gcc.target/i386/x86gprintrin-5.c: Likewise.
* gcc.target/i386/x86gprintrin-5a.c: Likewise.
* gcc.target/i386/x86gprintrin-5b.c: Likewise.
* gcc.target/i386/x86gprintrin-6.c: Likewise.
libgcc/
PR target/97148
* config/i386/shadow-stack-unwind.h: Include <x86gprintrin.h>
instead of <cetintrin.h>.
Generate assembly with .localentry,1 functions using @notoc calls.
This patch makes libgcc.a asm look the same as power10 pcrel as far as
toc/notoc is concerned.
Otherwise calling between functions that advertise as using the TOC
and those that don't, will require linker call stubs in statically
linked code.
gcc/
* config/rs6000/ppc-asm.h: Support __PCREL__ code.
libgcc/
* config/rs6000/morestack.S,
* config/rs6000/tramp.S: Support __PCREL__ code.
libitm/
* config/powerpc/sjlj.S: Support __PCREL__ code.
We've had this hack in the libgcc config to build libgcc with
-mcmodel=small for powerpc64 for a long time. It wouldn't be a bad
thing if someone who knows the multilib machinery well could arrange
for -mcmodel=small to be passed just for ppc64 when building for
earlier than power10. But for now, make -mno-minimal-toc do nothing
when pcrel. Which will do the right thing for any project that has
copied libgcc's trick.
We want this if configuring using --with-cpu=power10 to build a
power10 pcrel libgcc. --mcmodel=small turns off pcrel.
gcc/
* config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
set -mcmodel=small for -mno-minimal-toc when pcrel.
libgcc/
* config/rs6000/t-linux: Document purpose of -mno-minimal-toc.
Use `-fasynchronous-unwind-tables' rather than `-fexceptions
-fnon-call-exceptions' in LIB2_DIVMOD_FUNCS compilation flags so as to
provide unwind tables for the affected functions while not pulling the
unwinder proper, which is not required here.
Beyond saving program space it fixes a RISC-V glibc build error due to
unsatisfied `malloc' and `free' references from the unwinder causing
link errors with `ld.so' where libgcc has been built at -O0.
libgcc/
* config/riscv/t-elf (LIB2_DIVMOD_EXCEPTION_FLAGS): New
variable.
The libgcc HF support routines were being linked into libgcc_s.so,
but weren't being exported.
libgcc/
* config/aarch64/libgcc-softfp.ver: New file.
* config/aarch64/t-softfp (SHLIB_MAPFILES): Add it.
AIX FAT libraries should be built with the version of AR chosen by configure.
The GNU Make $(AR) variable includes the AIX -X32_64 option needed
by the default Makefile rules to accept both 32 bit and 64 bit object files.
The -X32_64 option conflicts with ar archiving objects of the same name
used to build FAT libraries.
This patch changes the Makefile fragments for AIX FAT libraries to use $(AR),
but strips the -X32_64 option from the Make variable.
libgcc/ChangeLog:
2020-09-27 Clement Chigot <clement.chigot@atos.net>
* config/rs6000/t-slibgcc-aix: Use $(AR) without -X32_64.
libatomic/ChangeLog:
2020-09-27 Clement Chigot <clement.chigot@atos.net>
* config/t-aix: Use $(AR) without -X32_64.
libgomp/ChangeLog:
2020-09-27 Clement Chigot <clement.chigot@atos.net>
* config/t-aix: Use $(AR) without -X32_64.
libstdc++-v3/ChangeLog:
2020-09-27 Clement Chigot <clement.chigot@atos.net>
* config/os/aix/t-aix: Use $(AR) without -X32_64.
libgfortran/ChangeLog:
2020-09-27 Clement Chigot <clement.chigot@atos.net>
* config/t-aix: Use $(AR) without -X32_64.
Before the change gcc did not stream correctly TOPN counters
if counters belonged to a non-local shared object.
As a result zero-section optimization generated TOPN sections
in a form not recognizable by '__gcov_merge_topn'.
The problem happens because in a case of multiple shared objects
'__gcov_merge_topn' function is present in address space multiple
times (once per each object).
The fix is to never rely on function address and predicate on TOPN
counter types.
libgcc/ChangeLog:
PR gcov-profile/96913
* libgcov-driver.c (write_one_data): Avoid function pointer
comparison in TOP streaming decision.
This patch makes the *_internal functions 'static inline' to avoid these warnings during the build:
/libgcc/config/arm/fp16.c:169:1: warning: no previous prototype for '__gnu_h2f_internal' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:194:1: warning: no previous prototype for '__gnu_f2h_ieee' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:200:1: warning: no previous prototype for '__gnu_h2f_ieee' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:206:1: warning: no previous prototype for '__gnu_f2h_alternative' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:212:1: warning: no previous prototype for '__gnu_h2f_alternative' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:218:1: warning: no previous prototype for '__gnu_d2h_ieee' [-Wmissing-prototypes]
/libgcc/config/arm/fp16.c:224:1: warning: no previous prototype for '__gnu_d2h_alternative' [-Wmissing-prototypes]
2020-09-11 Torbjörn SVENSSON <torbjorn.svensson@st.com>
Christophe Lyon <christophe.lyon@linaro.org>
libgcc/
* config/arm/fp16.c (__gnu_h2f_internal): Add 'static inline'
qualifier.
(__gnu_f2h_ieee, __gnu_h2f_ieee, __gnu_f2h_alternative)
(__gnu_h2f_alternative,__gnu_d2h_ieee, __gnu_d2h_alternative): Add
missing prototypes.
When building for target nvptx, we get this and similar warnings for libgcc:
...
src/libgcc/config/nvptx/atomic.c:39:1: warning: conflicting types for \
built-in function ‘__sync_val_compare_and_swap_1’; expected \
‘unsigned char(volatile void *, unsigned char, unsigned char)’ \
[-Wbuiltin-declaration-mismatch]
...
Fix this by making sure in atomic.c that the pointers used are of type
'volatile void *'.
Tested by rebuilding atomic.c.
libgcc/ChangeLog:
* config/nvptx/atomic.c (__SYNC_SUBWORD_COMPARE_AND_SWAP): Fix
Wbuiltin-declaration-mismatch.
The implementation of define_expand and define_insn patterns to handle
shifts in the MSP430 backend is inconsistent, resulting in missed
opportunities to make best use of the architecture's features.
There's now a single define_expand used as the entry point for all valid
shifts, and the decision to either use a helper function to perform the
shift (often required for the 430 ISA), or fall through to the
define_insn patterns can be made from that expander function.
Shifts by a constant amount have been grouped into one define_insn for
each type of shift, instead of having different define_insn patterns for
shifts by different amounts.
A new target option "-mmax-inline-shift=" has been added to allow tuning
of the number of shift instructions to emit inline, instead of using
a library helper function.
gcc/ChangeLog:
* config/msp430/constraints.md (K): Change unused constraint to
constraint to a const_int between 1 and 19.
(P): New constraint.
* config/msp430/msp430-protos.h (msp430x_logical_shift_right): Remove.
(msp430_expand_shift): New.
(msp430_output_asm_shift_insns): New.
* config/msp430/msp430.c (msp430_rtx_costs): Remove shift costs.
(CSH): Remove.
(msp430_expand_helper): Remove hard-coded generation of some inline
shift insns.
(use_helper_for_const_shift): New.
(msp430_expand_shift): New.
(msp430_output_asm_shift_insns): New.
(msp430_print_operand): Add new 'W' operand selector.
(msp430x_logical_shift_right): Remove.
* config/msp430/msp430.md (HPSI): New define_mode_iterator.
(HDI): Likewise.
(any_shift): New define_code_iterator.
(shift_insn): New define_code_attr.
Adjust unnamed insn patterns searched for by combine.
(ashlhi3): Remove.
(slli_1): Remove.
(430x_shift_left): Remove.
(slll_1): Remove.
(slll_2): Remove.
(ashlsi3): Remove.
(ashldi3): Remove.
(ashrhi3): Remove.
(srai_1): Remove.
(430x_arithmetic_shift_right): Remove.
(srap_1): Remove.
(srap_2): Remove.
(sral_1): Remove.
(sral_2): Remove.
(ashrsi3): Remove.
(ashrdi3): Remove.
(lshrhi3): Remove.
(srli_1): Remove.
(430x_logical_shift_right): Remove.
(srlp_1): Remove.
(srll_1): Remove.
(srll_2x): Remove.
(lshrsi3): Remove.
(lshrdi3): Remove.
(<shift_insn><mode>3): New define_expand.
(<shift_insn>hi3_430): New define_insn.
(<shift_insn>si3_const): Likewise.
(ashl<mode>3_430x): Likewise.
(ashr<mode>3_430x): Likewise.
(lshr<mode>3_430x): Likewise.
(*bitbranch<mode>4_z): Replace renamed predicate msp430_bitpos with
const_0_to_15_operand.
* config/msp430/msp430.opt: New option -mmax-inline-shift=.
* config/msp430/predicates.md (const_1_to_8_operand): New predicate.
(const_0_to_15_operand): Rename msp430_bitpos predicate.
(const_1_to_19_operand): New predicate.
* doc/invoke.texi: Document -mmax-inline-shift=.
libgcc/ChangeLog:
* config/msp430/slli.S (__gnu_mspabi_sllp): New.
* config/msp430/srai.S (__gnu_mspabi_srap): New.
* config/msp430/srli.S (__gnu_mspabi_srlp): New.
gcc/testsuite/ChangeLog:
* gcc.target/msp430/emulate-srli.c: Fix expected assembler text.
* gcc.target/msp430/max-inline-shift-430-no-opt.c: New test.
* gcc.target/msp430/max-inline-shift-430.c: New test.
* gcc.target/msp430/max-inline-shift-430x.c: New test.
This adds support for __sync_val_compare_and_swap and
__sync_bool_compare_and_swap for 1-byte and 2-byte long
values, which are not natively supported on nvptx.
Build and reg-tested on nvptx.
Build and reg-tested libgomp on x86_64 with nvptx accelerator.
2020-07-16 Kwok Cheung Yeung <kcy@codesourcery.com>
libgcc/
* config/nvptx/atomic.c: New.
* config/nvptx/t-nvptx (LIB2ADD): Add atomic.c.
gcc/testsuite/
* gcc.target/nvptx/ia64-sync-5.c: New.
libgomp/
* testsuite/libgomp.c-c++-common/reduction-16.c: New.
This accomodates increased space required by use of the xsavec
instruction in the dynamic linker trampoline.
libgcc/ChangeLog:
* config/i386/morestack.S (BACKOFF) [x86_64]: Add 2048 bytes.
As mentioned in the PR, the fallback path when LSE is unavailable writes
incorrect registers to the memory if the previous content compares equal
to x0, x1 - it writes copy of x0, x1 from the start of function, but it
should write x2, x3.
2020-08-03 Jakub Jelinek <jakub@redhat.com>
PR target/96402
* config/aarch64/lse.S (__aarch64_cas16_acq_rel): Use x2, x3 instead
of x(tmp0), x(tmp1) in STXP arguments.
* gcc.target/aarch64/pr96402.c: New test.
Rewrite code sequences throughout the 64-bit RISC-V `__riscv_save_*'
routines replacing `li t1, -48', `li t1, -64', and `li t1, -80',
instructions, which do not have a compressed encoding, respectively with
`li t1, 3', `li t1, 4', and `li t1, 4', which do, and then adjusting the
remaining code accordingly observing that `sub sp, sp, t1' takes the
same amount of space as an `slli t1, t1, 4'/`add sp, sp, t1' instruction
pair does, again due to the use of compressed encodings, saving 6 bytes
total.
This change does increase code size by 4 bytes for RISC-V processors
lacking the compressed instruction set, however their users couldn't
care about the code size or they would have chosen an implementation
that does have the compressed instructions, wouldn't they?
libgcc/
* config/riscv/save-restore.S [__riscv_xlen == 64]
(__riscv_save_10, __riscv_save_8, __riscv_save_6, __riscv_save_4)
(__riscv_save_2): Replace negative immediates used for the final
stack pointer adjustment with positive ones, right-shifted by 4.
This note is not used anywhere currently but it is supposed to mark
objects if the return address is protected with PAC on the stack.
Since lse.S only has leaf functions the return address is never
saved on the stack so we can add the note.
The note is only added if pac-ret is enabled because it can cause
problems with old linkers and we don't have checks for that. This
can be changed later to be unconditional, for now it is consistent
with how gcc generates the notes.
libgcc/ChangeLog:
* config/aarch64/lse.S: Add PAC property note.
The FAT libraries config fragments need to know which library is native
and which is a multilib to choose the correct multilib from which to
append the additional object file or shared object file. Testing the
top-level archive is fragile because it will fail if rebuilding. This
patch tests the compiler preprocessing macros for the 64 bit AIX specific
__64BIT__ to determine the native mode of the compiler in MULTILIBTOP.
2020-07-14 David Edelsohn <dje.gcc@gmail.com>
libatomic/ChangeLog
* config/t-aix: Set BITS from compiler cpp macro.
libgcc/ChangeLog
* config/rs6000/t-slibgcc-aix: Set BITS from compiler cpp macro.
libgfortran/ChangeLog
* config/t-aix: Set BITS from compiler cpp macro.
libgomp/ChangeLog
* config/t-aix: Set BITS from compiler cpp macro.
libstdc++-v3/ChangeLog
* config/os/aix/t-aix: Set BITS from compiler cpp macro.
Mangling, currently only used on AArch64 for return address signing,
is an internal representation that should not be exposed via
__builtin_return_address return value,
__builtin_eh_return handler argument,
_Unwind_DebugHook handler argument.
Note that a mangled address might not even fit into a void *, e.g.
with AArch64 ilp32 ABI the return address is stored as 64bit, so
the mangled return address cannot be accessed via _Unwind_GetPtr.
This patch changes the unwinder hooks as follows:
MD_POST_EXTRACT_ROOT_ADDR is removed: root address comes from
__builtin_return_address which is not mangled.
MD_POST_EXTRACT_FRAME_ADDR is renamed to MD_DEMANGLE_RETURN_ADDR,
it now operates on _Unwind_Word instead of void *, so the hook
should work when return address signing is enabled on AArch64 ilp32.
(But for that __builtin_aarch64_autia1716 should be fixed to operate
on 64bit input instead of a void *.)
MD_POST_FROB_EH_HANDLER_ADDR is removed: it is the responsibility of
__builtin_eh_return to do the mangling if necessary.
2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com>
libgcc/ChangeLog:
PR target/94891
* config/aarch64/aarch64-unwind.h (MD_POST_EXTRACT_ROOT_ADDR): Remove.
(MD_POST_FROB_EH_HANDLER_ADDR): Remove.
(MD_POST_EXTRACT_FRAME_ADDR): Rename to ...
(MD_DEMANGLE_RETURN_ADDR): This.
(aarch64_post_extract_frame_addr): Rename to ...
(aarch64_demangle_return_addr): This.
(aarch64_post_frob_eh_handler_addr): Remove.
* unwind-dw2.c (uw_update_context): Demangle return address.
(uw_frob_return_addr): Remove.
lse.S did not have the GNU property note markup and the BTI c
instructions that are necessary when it is built with branch
protection.
The notes are only added when libgcc is built with branch
protection, because old linkers mishandle the note (merge
them incorrectly or emit warnings), the BTI instructions
are added unconditionally.
Note: BTI c is only necessary at function entry if the function
may be called indirectly, currently lse functions are not called
indirectly, but BTI is added for ABI reasons e.g. to allow
linkers later to emit stub code with indirect jump.
2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com>
libgcc/ChangeLog:
PR target/96001
* config/aarch64/lse.S: Add BTI marking and related definitions,
and add BTI c to function entries.
lse.S did not have GNU stack note, this may cause missing
PT_GNU_STACK in binaries on Linux and FreeBSD.
2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com>
libgcc/ChangeLog:
* config/aarch64/lse.S: Add stack note.
gcc/ChangeLog:
PR gcov-profile/95348
* coverage.c (read_counts_file): Read only COUNTERS that are
not all-zero.
* gcov-dump.c (tag_function): Change signature from unsigned to
signed integer.
(tag_blocks): Likewise.
(tag_arcs): Likewise.
(tag_lines): Likewise.
(tag_counters): Likewise.
(tag_summary): Likewise.
* gcov.c (read_count_file): Read all non-zero counters
sensitively.
libgcc/ChangeLog:
PR gcov-profile/95348
* libgcov-driver.c (merge_one_data): Merge only profiles
that are not of non-zero type.
(write_one_data): Write counters only if there's one non-zero
value.
* libgcov-util.c (tag_function): Change signature from unsigned
to int.
(tag_blocks): Likewise.
(tag_arcs): Likewise.
(tag_counters): Likewise.
(tag_summary): Likewise.
(tag_lines): Read only if COUNTERS is non-zero.
(read_gcda_file): Handle negative length for COUNTERS type.
libgcc/ChangeLog:
* libgcov-driver.c (merge_summary): Remove function as its name
is misleading and doing something different.
(dump_one_gcov): Add ATTRIBUTE_UNUSED for 2 args. Take read summary
in gcov-tool.
* libgcov-util.c (curr_object_summary): Remove.
(read_gcda_file): Remove unused curr_object_summary.
(gcov_merge): Merge summaries.
* libgcov.h: Add summary argument for gcov_info struct.
Both x86 backend and libgcc define enum processor_features. libgcc sets
enum processor_feature and x86 backend checks enum processor_feature.
They are very easy out of sync and it has happened multiple times in the
past.
1. Move cpuinfo.h from libgcc to common/config/i386 so that we can share
the same enum processor_features in x86 backend and libgcc.
2. Change __cpu_features2 to an array to support more processor features.
3. Add more processor features to enum processor_features.
gcc/
PR target/95259
* common/config/i386/cpuinfo.h: New file.
(__processor_model): Moved from libgcc/config/i386/cpuinfo.h.
(__processor_model2): New.
(CHECK___builtin_cpu_is): New. Defined as empty if not defined.
(has_cpu_feature): New function.
(set_cpu_feature): Likewise.
(get_amd_cpu): Moved from libgcc/config/i386/cpuinfo.c. Use
CHECK___builtin_cpu_is. Return AMD CPU name.
(get_intel_cpu): Moved from libgcc/config/i386/cpuinfo.c. Use
Use CHECK___builtin_cpu_is. Return Intel CPU name.
(get_available_features): Moved from libgcc/config/i386/cpuinfo.c.
Also check FEATURE_3DNOW, FEATURE_3DNOWP, FEATURE_ADX,
FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT, FEATURE_CLWB,
FEATURE_CLZERO, FEATURE_CMPXCHG16B, FEATURE_CMPXCHG8B,
FEATURE_ENQCMD, FEATURE_F16C, FEATURE_FSGSBASE, FEATURE_FXSAVE,
FEATURE_HLE, FEATURE_IBT, FEATURE_LAHF_LM, FEATURE_LM,
FEATURE_LWP, FEATURE_LZCNT, FEATURE_MOVBE, FEATURE_MOVDIR64B,
FEATURE_MOVDIRI, FEATURE_MWAITX, FEATURE_OSXSAVE,
FEATURE_PCONFIG, FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW,
FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED,
FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA,
FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES,
FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC,
FEATURE_XSAVEOPT and FEATURE_XSAVES
(cpu_indicator_init): Moved from libgcc/config/i386/cpuinfo.c.
Also update cpu_model2.
* common/config/i386/i386-cpuinfo.h (processor_vendor): Add
Add VENDOR_CENTAUR, VENDOR_CYRIX and VENDOR_NSC.
(processor_features): Moved from gcc/config/i386/i386-builtins.c.
Renamed F_XXX to FEATURE_XXX. Add FEATURE_3DNOW, FEATURE_3DNOWP,
FEATURE_ADX, FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT,
FEATURE_CLWB, FEATURE_CLZERO, FEATURE_CMPXCHG16B,
FEATURE_CMPXCHG8B, FEATURE_ENQCMD, FEATURE_F16C,
FEATURE_FSGSBASE, FEATURE_FXSAVE, FEATURE_HLE, FEATURE_IBT,
FEATURE_LAHF_LM, FEATURE_LM, FEATURE_LWP, FEATURE_LZCNT,
FEATURE_MOVBE, FEATURE_MOVDIR64B, FEATURE_MOVDIRI,
FEATURE_MWAITX, FEATURE_OSXSAVE, FEATURE_PCONFIG,
FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW,
FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED,
FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA,
FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES,
FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC,
FEATURE_XSAVEOPT, FEATURE_XSAVES and CPU_FEATURE_MAX.
(SIZE_OF_CPU_FEATURES): New.
* config/i386/i386-builtins.c (processor_features): Removed.
(isa_names_table): Replace F_XXX with FEATURE_XXX.
(fold_builtin_cpu): Change __cpu_features2 to an array.
libgcc/
PR target/95259
* config/i386/cpuinfo.c: Don't include "cpuinfo.h". Include
"common/config/i386/i386-cpuinfo.h" and
"common/config/i386/cpuinfo.h".
(__cpu_features2): Changed to array.
(get_amd_cpu): Removed.
(get_intel_cpu): Likewise.
(get_available_features): Likewise.
(__cpu_indicator_init): Call cpu_indicator_init.
* config/i386/cpuinfo.h: Removed.
GNU Make supports "-include" keyword to prevent warnings and errors due to
inclusion of non-existent files. This patch changes gcc/ and libgcc/ to use
"-include" in place of the historical conditional inclusion and use of
empty.mk work-arounds.
gcc/ChangeLog
2020-06-23 David Edelsohn <dje.gcc@gmail.com>
* Makefile.in (LANG_MAKEFRAGS): Same.
(tmake_file): Use -include.
(xmake_file): Same.
libgcc/ChangeLog
2020-06-23 David Edelsohn <dje.gcc@gmail.com>
* Makefile.in: Remove uses of empty.mk. Use -include.
* config/avr/t-avr: Use -include.
* empty.mk: Delete.
libgcc/config/avr/libf7/ChangeLog
2020-06-23 David Edelsohn <dje.gcc@gmail.com>
* t-libf7: Same.
This patch adds the ability to configure GCC on AIX to build as a
64 bit application and to build target libraries "FAT" libraries in both
32 bit and 64 bit mode.
The patch adds makefile fragment hooks to target libraries that allows
them to include target-specific rules. The target specific rules for
AIX place both 32 bit and 64 bit objects and shared objects
in archives at the top-level, not multilib subdirectories. The
multilibs are built in subdirectories, but must be combined during the
last parts of the target library build process. Because of the way
that GCC bootstrap works, the libraries must be combined during the
multiple stages of GCC bootstrap, not solely when installed in the
final destination, so the libraries are correct at the end of
each target library build stage, not solely an install recipe.
gcc/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* config.gcc: Use t-aix64, biarch64 and default64 for cpu_is_64bit.
* config/rs6000/aix72.h (ASM_SPEC): Remove aix64 option.
(ASM_SPEC32): New.
(ASM_SPEC64): New.
(ASM_CPU_SPEC): Remove vsx and altivec options.
(CPP_SPEC_COMMON): Rename from CPP_SPEC.
(CPP_SPEC32): New.
(CPP_SPEC64): New.
(CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON..
(TARGET_DEFAULT): Only define if not BIARCH.
(LIB_SPEC_COMMON): Rename from LIB_SPEC.
(LIB_SPEC32): New.
(LIB_SPEC64): New.
(LINK_SPEC_COMMON): Rename from LINK_SPEC.
(LINK_SPEC32): New.
(LINK_SPEC64): New.
(STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase.
(ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P.
(CPP_SPEC): Same.
(CPLUSPLUS_CPP_SPEC): Same.
(LIB_SPEC): Same.
(LINK_SPEC): Same.
(SUBTARGET_EXTRA_SPECS): Add new 32/64 specs.
* config/rs6000/defaultaix64.h: New file.
* config/rs6000/t-aix64: New file.
libgcc/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* config.host (extra_parts): Add crtcxa_64 and crtdbase_64.
* config/rs6000/t-aix-cxa: Explicitly compile 32 bit with -maix32
and 64 bit with -maix64.
* config/rs6000/t-slibgcc-aix: Remove extra @multilib_dir@ level.
Build and install AIX-style FAT libraries.
libgomp/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.
libstdc++-v3/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host (aix*): Define tmake_file.
* config/os/aix/t-aix: New file.
libatomic/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.
libgfortran/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host: Add system configury stanza. Define tmake_file.
* config/t-aix: New file.
libgcc/
* config.host (md_unwind_header) <i[34567]86-*-gnu*>: Set to
'i386/gnu-unwind.h'
* config/i386/gnu-unwind.h: New file.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
libgcc/ChangeLog:
* libgcov-util.c (read_gcda_finalize): Remove const operator.
(merge_wrapper): Add both counts and use them properly.
(topn_to_memory_representation): New function.
(gcov_merge): Covert on disk representation to in memory
representation.
* libgcov.h: Remove const operator.
The patch fixes tree-prof.exp tests on solaris11 and i686-linux-gnu,
problem was that sizeof of a pointer is different from sizeof gcov_type.
I'm going to install it if there are no objections.
Thanks,
Martin
libgcc/ChangeLog:
PR gcov-profile/95494
* libgcov-driver.c (write_top_counters): Cast first to
intptr_t as sizeof(*) != sizeof(gcov_type).
* libgcov.h (gcov_counter_set_if_null): Remove.
(gcov_topn_add_value): Cast first to intptr_t and update
linked list directly.
Rewrite uw_install_context without function calls to avoid register
spilling in _Unwind_RaiseException during return context installation.
2020-06-08 Max Filippov <jcmvbkbc@gmail.com>
gcc/testsuite/
* g++.target/xtensa/pr95571.C: New test.
* g++.target/xtensa/xtensa.exp: New testsuite.
libgcc/
* config/xtensa/unwind-dw2-xtensa.c (uw_install_context): Merge
with uw_install_context_1.
We must guard used atomic builtins with GCOV_SUPPORTS_ATOMIC.
The patch is tested on AIX and I'm going to push it.
libgcc/ChangeLog:
PR gcov-profile/95480
* libgcov-profiler.c (GCOV_SUPPORTS_ATOMIC): Move to...
* libgcov.h (GCOV_SUPPORTS_ATOMIC): ...here.
(gcov_counter_add): Use GCOV_SUPPORTS_ATOMIC guard.
(gcov_counter_set_if_null): Likewise.
The ISA manual specifies that divide by zero always returns -1 as the result.
We were failing to do that when the dividend was negative.
Original patch from Virginie Moser.
libgcc/
* config/riscv/div.S (__divdi3): For negative arguments, change bgez
to bgtz.
The calloc was in the original tested version of the patch
and I made accidental last minute change.
Installed to master as obvious.
libgcc/ChangeLog:
* libgcov.h (gcov_topn_add_value): Use xcalloc instead
of xmalloc.
gcc/ChangeLog:
* coverage.c (get_coverage_counts): Skip sanity check for TOP N counters
as they have variable number of counters.
* gcov-dump.c (main): Add new option -r.
(print_usage): Likewise.
(tag_counters): All new raw format.
* gcov-io.h (struct gcov_kvp): New.
(GCOV_TOPN_VALUES): Remove.
(GCOV_TOPN_VALUES_COUNTERS): Likewise.
(GCOV_TOPN_MEM_COUNTERS): New.
(GCOV_TOPN_DISK_COUNTERS): Likewise.
(GCOV_TOPN_MAXIMUM_TRACKED_VALUES): Likewise.
* ipa-profile.c (ipa_profile_generate_summary): Use
GCOV_TOPN_MAXIMUM_TRACKED_VALUES.
(ipa_profile_write_edge_summary): Likewise.
(ipa_profile_read_edge_summary): Likewise.
(ipa_profile): Remove usage of GCOV_TOPN_VALUES.
* profile.c (sort_hist_values): Sort variable number
of counters.
(compute_value_histograms): Special case for TOP N counters
that have dynamic number of key-value pairs.
* value-prof.c (dump_histogram_value): Dump variable number
of key-value pairs.
(stream_in_histogram_value): Stream in variable number
of key-value pairs for TOP N counter.
(get_nth_most_common_value): Deal with variable number
of key-value pairs.
(dump_ic_profile): Use GCOV_TOPN_MAXIMUM_TRACKED_VALUES
for loop iteration.
(gimple_find_values_to_profile): Set GCOV_TOPN_MEM_COUNTERS
to n_counters.
* doc/gcov-dump.texi: Document new -r option.
libgcc/ChangeLog:
* libgcov-driver.c (prune_topn_counter): Remove.
(prune_counters): Likewise.
(merge_one_data): Special case TOP N counters
as they have variable length.
(write_top_counters): New.
(write_one_data): Special case TOP N.
(dump_one_gcov): Do not prune TOP N counters.
* libgcov-merge.c (merge_topn_values_set): Remove.
(__gcov_merge_topn): Use gcov_topn_add_value.
* libgcov-profiler.c (__gcov_topn_values_profiler_body):
Likewise here.
* libgcov.h (gcov_counter_add): New.
(gcov_counter_set_if_null): Likewise.
(gcov_topn_add_value): New.
Windows ABI (MinGW) is different than Linux ABI when bitfileds are involved.
The following patch adds __attribute__ ((gcc_struct)) to struct fenv in order
to match the layout of x87 state image in memory.
2020-06-01 Uroš Bizjak <ubizjak@gmail.com>
libatomic/ChangeLog:
* config/x86/fenv.c (struct fenv): Add __attribute__ ((gcc_struct)).
libgcc/ChangeLog:
* config/i386/sfp-exceptions.c (struct fenv):
Add __attribute__ ((gcc_struct)).
libgfortran/ChangeLog:
PR libfortran/95418
* config/fpu-387.h (struct fenv): Add __attribute__ ((gcc_struct)).
Update VPCLMULQDQ check to support processors with AVX version of
VPCLMULQDQ.
PR target/91695
* config/i386/cpuinfo.c (get_available_features): Fix VPCLMULQDQ
check.
Add FEATURE_AVX512VP2INTERSECT to libgcc so that enum processor_features
in libgcc matches enum processor_features in i386-builtins.c. Update
GFNI check to support processors with SSE and AVX versions of GFNI.
PR target/95212
PR target/95220
* config/i386/cpuinfo.c (get_available_features): Fix
FEATURE_GFNI check. Also check FEATURE_AVX512VP2INTERSECT.
* config/i386/cpuinfo.h (processor_features): Add
FEATURE_AVX512VP2INTERSECT.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
libgcc:
* config.host: Remove support for crisv32-*-* and cris*-*-linux.
* config/cris/libgcc-glibc.ver, config/cris/t-linux: Remove.
Introduce math_force_eval_div to use generic division to generate
INEXACT as well as INVALID and DIVZERO exceptions.
libgcc/ChangeLog:
* config/i386/sfp-exceptions.c (__math_force_eval): Remove.
(__math_force_eval_div): New define.
(__sfp_handle_exceptions): Use __math_force_eval_div to use
generic division to generate INVALID, DIVZERO and INEXACT
exceptions.
libatomic/ChangeLog:
* config/x86/fenv.c (__math_force_eval): Remove.
(__math_force_eval_div): New define.
(__atomic_deraiseexcept): Use __math_force_eval_div to use
generic division to generate INVALID, DIVZERO and INEXACT
exceptions.
libgfortran/ChangeLog:
* config/fpu-387.h (__math_force_eval): Remove.
(__math_force_eval_div): New define.
(local_feraiseexcept): Use __math_force_eval_div to use
generic division to generate INVALID, DIVZERO and INEXACT
exceptions.
(struct fenv): Define named struct instead of typedef.
This version of the fix uses __getauxval instead of getauxval.
The whole thing is guarded simply on __gnu_linux__.
__getauxval was introduced in 2.16 but the aarch64 port was added in 2.17 so in practice I expect all aarch64 glibcs to support __getauxval.
Bootstrapped and tested on aarch64-none-linux-gnu.
Also tested on aarch64-none-elf.
2020-05-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/lse-init.c (init_have_lse_atomics): Use __getauxval
instead of getauxval.
(AT_HWCAP): Define.
(HWCAP_ATOMICS): Define.
Guard detection on __gnu_linux__.
