* lock-and-run.sh: Check for process existence rather than timeout.
Matthias Klose noted that on less powerful targets, a link might take more
than 5 minutes; he mentions a figure of 3 hours for an LTO link. So this
patch changes the timeout to a check for whether the locking process still
exists. If the lock exists in an erroneous state (no pid file or can't
signal the pid) for 30 sec, steal it.
From-SVN: r277277
2019-10-21 Kamlesh Kumar <kamleshbhalui@gmail.com>
* rtti.c (get_tinfo_decl_dynamic): Do not call
TYPE_MAIN_VARIANT for function.
(get_typeid): Likewise.
* g++.dg/rtti/pr83534.C: New Test.
Reviewed-by: Jason Merrill <jason@redhat.com>
Co-Authored-By: Jason Merrill <jason@redhat.com>
From-SVN: r277270
has_value_dependent_address wasn't stripping location wrappers so it
gave the wrong answer for "&x" in the static_assert. That led us to
thinking that the expression isn't instantiation-dependent, and we
skipped static initialization of A<0>::x.
This patch adds stripping so that has_value_dependent_address gives the
same answer as it used to before the location wrappers addition.
* pt.c (has_value_dependent_address): Strip location wrappers.
* g++.dg/cpp0x/constexpr-odr1.C: New test.
* g++.dg/cpp0x/constexpr-odr2.C: New test.
From-SVN: r277266
My DImode arithmetic patches introduced a bug on thumb2 where we could
generate a register controlled shift into an ALU operation. In
fairness the bug was always present, but latent.
As part of cleaning this up (and auditing to ensure I've caught them
all this time) I've gone through all the shift generating patterns in
the MD files and cleaned them up, reducing some duplicate patterns
between the arm and thumb2 descriptions where we can now share the
same pattern. In some cases we were missing the shift attribute; in
most cases I've eliminated an ugly attribute setting using the fact
that we normally need separate alternatives for shift immediate and
shift reg to simplify the logic.
* config/arm/iterators.md (t2_binop0): Fix typo in comment.
* config/arm/arm.md (addsi3_carryin_shift): Simplify selection of the
type attribute.
(subsi3_carryin_shift): Separate into register and constant controlled
alternatives. Use shift_amount_operand for operand 4. Set shift
attribute and simplify type attribute.
(subsi3_carryin_shift_alt): Likewise.
(rsbsi3_carryin_shift): Likewise.
(rsbsi3_carryin_shift_alt): Likewise.
(andsi_not_shiftsi_si): Enable for TARGET_32BIT. Separate constant
and register controlled shifts into distinct alternatives.
(andsi_not_shiftsi_si_scc_no_reuse): Likewise.
(andsi_not_shiftsi_si_scc): Likewise.
(arm_cmpsi_negshiftsi_si): Likewise.
(not_shiftsi): Remove redundant M constraint from alternative 1.
(not_shiftsi_compare0): Likewise.
(arm_cmpsi_insn): Remove redundant alternative 2.
(cmpsi_shift_swp): Likewise.
(sub_shiftsi): Likewise.
(sub_shiftsi_compare0_scratch): Likewise.
* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Delete pattern.
(thumb2_cmpsi_neg_shiftsi): Likewise.
From-SVN: r277262
Extend dg-extract-results.sh and dg-extract-results.py to support the
KPASS test result status. This is required by GDB which uses a copy
of the dg-extract-results.{sh,py} scripts that it tries to keep in
sync with GCC.
ChangeLog:
* contrib/dg-extract-results.sh: Add support for KPASS.
* contrib/dg-extract-results.py: Likewise.
From-SVN: r277260
2019-10-21 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_slp_tree::ops): New member.
(SLP_TREE_SCALAR_OPS): New.
(vect_get_slp_defs): Adjust prototype.
* tree-vect-slp.c (vect_free_slp_tree): Release
SLP_TREE_SCALAR_OPS.
(vect_create_new_slp_node): Initialize it. New overload for
initializing by an operands array.
(_slp_oprnd_info::ops): New member.
(vect_create_oprnd_info): Initialize it.
(vect_free_oprnd_info): Release it.
(vect_get_and_check_slp_defs): Populate the operands array.
Do not swap operands in the IL when not necessary.
(vect_build_slp_tree_2): Build SLP nodes for invariant operands.
Record SLP_TREE_SCALAR_OPS for all invariant nodes. Also
swap operands in the operands array. Do not swap operands in
the IL.
(vect_slp_rearrange_stmts): Re-arrange SLP_TREE_SCALAR_OPS as well.
(vect_gather_slp_loads): Fix.
(vect_detect_hybrid_slp_stmts): Likewise.
(vect_slp_analyze_node_operations_1): Search for a internal
def child for computing reduction SLP_TREE_NUMBER_OF_VEC_STMTS.
(vect_slp_analyze_node_operations): Skip ops-only stmts for
the def-type push/pop dance.
(vect_get_constant_vectors): Compute number_of_vectors here.
Use SLP_TREE_SCALAR_OPS and simplify greatly.
(vect_get_slp_vect_defs): Use gimple_get_lhs also for PHIs.
(vect_get_slp_defs): Simplify greatly.
* tree-vect-loop.c (vectorize_fold_left_reduction): Simplify.
(vect_transform_reduction): Likewise.
* tree-vect-stmts.c (vect_get_vec_defs): Simplify.
(vectorizable_call): Likewise.
(vectorizable_operation): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Likewise.
(vectorizable_comparison): Likewise.
From-SVN: r277241
This patch implements the recently published[1] __rndr and __rndrrs
intrinsics used to access the RNG in Armv8.5-A.
The __rndrrs intrinsics can be used to reseed the generator too.
They are guarded by the __ARM_FEATURE_RNG feature macro.
A quirk with these intrinsics is that they store the random number in
their pointer argument and return a status
code if the generation succeeded.
The instructions themselves write the CC flags indicating the success of
the operation that we can then read with a CSET.
Therefore this implementation makes use of the IGNORE indicator to the
builtin expand machinery to avoid generating
the CSET if its result is unused (the CC reg clobbering effect is still
reflected in the pattern).
I've checked that using unspec_volatile prevents undesirable CSEing of
the instructions.
[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
* config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS): Define.
(aarch64_rndr): New define_insn.
(aarch64_rndrrs): Likewise.
* config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
(TARGET_RNG): Likewise.
* config/aarch64/aarch64.c (aarch64_expand_builtin): Use IGNORE
argument.
* config/aarch64/aarch64-protos.h (aarch64_general_expand_builtin):
Add fourth argument in prototype.
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
(aarch64_init_rng_builtins): Define.
(aarch64_general_init_builtins): Call aarch64_init_rng_builtins.
(aarch64_expand_rng_builtin): Define.
(aarch64_general_expand_builtin): Use IGNORE argument, handle
RNG builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_RNG when TARGET_RNG.
* config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.
* gcc.target/aarch64/acle/rng_1.c: New test.
From-SVN: r277239
This patch makes sure ensure_base_align only changes alignment if the new
alignment is more restrictive. It already did this if we were dealing with
symbols, but it now does it for all types of declarations.
gcc/ChangeLog:
2019-10-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
* tree-vect-stmts (ensure_base_align): Only change alignment if new
alignment is more restrictive.
From-SVN: r277238
The increase_alignment pass was using get_vectype_for_scalar_type
to get the preferred vector type for each array element type.
This has the effect of carrying over the vector size chosen by
the first successful call to all subsequent calls, whereas it seems
more natural to treat each array type independently and pick the
"best" vector type for each element type.
2019-10-21 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vectorizer.c (get_vec_alignment_for_array_type): Use
get_vectype_for_scalar_type_and_size instead of
get_vectype_for_scalar_type.
From-SVN: r277223
After the previous patch, it seems more natural to apply the
PARAM_SLP_MAX_INSNS_IN_BB threshold as soon as we know what
the region is, rather than delaying it to vect_slp_analyze_bb_1.
(But rather than carve out the biggest region possible and then
reject it, wouldn't it be better to stop when the region gets
too big, to at least give us a chance of vectorising something?)
It also seems more natural for vect_slp_bb_region to create the
bb_vec_info itself rather than (a) having to pass bits of data down
for the initialisation and (b) forcing vect_slp_analyze_bb_1 to free
on every failure return.
2019-10-20 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vect-slp.c (vect_slp_analyze_bb_1): Take a bb_vec_info
and return a boolean success value. Move the allocation and
initialization of the bb_vec_info to...
(vect_slp_bb_region): ...here. Update call accordingly.
(vect_slp_bb): Apply PARAM_SLP_MAX_INSNS_IN_BB here rather
than in vect_slp_analyze_bb_1.
From-SVN: r277211
If the first attempt at applying BB SLP to a region fails, the main loop
in vect_slp_bb recomputes the region's bounds and datarefs for the next
vector size. AFAICT this isn't needed any more; we should be able
to reuse the datarefs from the first attempt instead.
2019-10-20 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vect-slp.c (vect_slp_analyze_bb_1): Call save_datarefs
when processing the given datarefs for the first time and
check_datarefs subsequently.
(vect_slp_bb_region): New function, split out of...
(vect_slp_bb): ...here. Don't recompute the region bounds and
dataref sets when retrying with a different vector size.
From-SVN: r277210
2019-10-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/91926
* runtime/ISO_Fortran_binding.c (cfi_desc_to_gfc_desc): Revert
the change made on 2019-10-05.
From-SVN: r277204
Darwin does not mark entries in string.h with nonnull attributes
so the test fails. Since the purpose of the test is to check that
the warnings are issued for an inlined function, not that the target
headers are marked up, we can provide marked up headers for Darwin.
gcc/testsuite/ChangeLog:
2019-10-19 Iain Sandoe <iain@sandoe.co.uk>
* gcc.dg/Wnonnull.c: Add attributed function declarations for
memcpy and strlen for Darwin.
From-SVN: r277202
2019-10-17 JeanHeyd Meneide <phdofthehouse@gmail.com>
gcc/
* escaped_string.h (escaped_string): New header.
* tree.c (escaped_string): Remove escaped_string class.
gcc/c-family
* c-lex.c (c_common_has_attribute): Update nodiscard value.
gcc/cp/
* tree.c (handle_nodiscard_attribute) Added C++2a nodiscard
string message.
(std_attribute_table) Increase nodiscard argument handling
max_length from 0 to 1.
* parser.c (cp_parser_check_std_attribute): Add requirement
that nodiscard only be seen once in attribute-list.
(cp_parser_std_attribute): Check that empty parenthesis lists are
not specified for attributes that have max_length > 0 (e.g.
[[attr()]]).
* cvt.c (maybe_warn_nodiscard): Add nodiscard message to
output, if applicable.
(convert_to_void): Allow constructors to be nodiscard-able (P1771).
gcc/testsuite/g++.dg/cpp0x
* gen-attrs-67.C: Test new error message for empty-parenthesis-list.
gcc/testsuite/g++.dg/cpp2a
* nodiscard-construct.C: New test.
* nodiscard-once.C: New test.
* nodiscard-reason-nonstring.C: New test.
* nodiscard-reason-only-one.C: New test.
* nodiscard-reason.C: New test.
Reviewed-by: Jason Merrill <jason@redhat.com>
From-SVN: r277200
gcc/testsuite/ChangeLog:
PR tree-optimization/92157
* gcc.dg/strlenopt-69.c: Disable test failing due to PR 92155.
* gcc.dg/strlenopt-87.c: New test.
gcc/ChangeLog:
PR tree-optimization/92157
* tree-ssa-strlen.c (handle_builtin_string_cmp): Be prepared for
compute_string_length to return a negative result.
From-SVN: r277194
In thumb2 we now generate a NEGS instruction rather than RSBS, so this
test needs updating.
* gcc.target/arm/negdi-3.c: Update expected output to allow NEGS.
From-SVN: r277192
The generic expansion code for negv does not try the subv patterns,
but instead emits a sub and a compare separately. Fortunately, the
patterns can make use of the new subv operations, so just call those.
We can also rewrite this using an iterator to simplify things further.
Finally, we can now make negvdi4 work on Thumb2 as well as Arm.
* config/arm/arm.md (negv<SIDI:mode>3): New expansion rule.
(negvsi3, negvdi3): Delete.
(negdi2_compare): Delete.
From-SVN: r277191
This patch adds early expansion of subvdi4. The expansion sequence
is broadly based on the expansion of usubvdi4.
* config/arm/arm.md (subvdi4): Decompose calculation into 32-bit
operations.
(subdi3_compare1): Delete pattern.
(subvsi3_borrow): New insn pattern.
(subvsi3_borrow_imm): Likewise.
From-SVN: r277190
