PR target/15130
* config/sh/sh-protos.h (sh_expand_epilogue): Change prototype.
* config/sh/sh.c (output_stack_adjust): Take the sibcall epilogue
into account. Compute the correct number of general registers
for the return value. Generate a special push/pop sequence when
failing to get a temporary register for non SHmedia epilogue.
(sh_expand_epilogue): Add an argument to show whether it's for
sibcall or not. Set the 3rd argument of output_stack_adjust to
-1 if needed.
(sh_need_epilogue): Call sh_expand_epilogue with 0.
* config/sh/sh.md (sibcall_epilogue): Call sh_expand_epilogue
with 1.
(epilogue): Call sh_expand_epilogue with 0.
From-SVN: r81683
[gcc/ChangeLog]
2004-05-10 Ziemowit Laski <zlaski@apple.com>
* config/rs6000/altivec.h (vec_sld): Add overloads for
argument/return types of 'vector bool int', 'vector bool short'
and 'vector bool char'.
[gcc/testsuite/ChangeLog]
2004-05-10 Ziemowit Laski <zlaski@apple.com>
* g++.dg/ext/altivec-8.C: New test case.
* gcc.dg/altivec-13.c: New test case.
From-SVN: r81681
* read-rtl.c (read_rtx): Allow 's' and 'T' strings to be omitted,
treating missing ones as "".
* config/mips/mips.md: Remove constraints from match_operands and
match_scratches if they appear in define_expands (except reload*),
define_peephole2s, define_splits or attribute specifications.
* config/mips/7000.md, config/mips/sb1.md: Remove match_operand
constraint strings.
From-SVN: r81676
* config/rs6000/rs6000.c (function_arg_boundary): Always align
AltiVec vectors.
(function_arg_advance): Pass TARGET_32BIT -mabi=no-altivec AltiVec
vectors by refererence. Align the same for TARGET_64BIT to a 16
byte boundary. Remove useless code. Add function comment.
(function_arg): Similarly. Move gpr rs6000_mixed_function_arg
call to where it belongs.
(function_arg_partial_nregs): Return true for all TARGET_32BIT
-mabi=no-altivec AltiVec vectors. Fix debug output.
(rs6000_va_arg): Adjust for AltiVec change.
From-SVN: r81666
* config/rs6000/rs6000.c (function_arg_boundary): Align for ABI_V4
when size is 8 bytes.
(function_arg_advance): Account for stack space used by AltiVec
args when -mabi=altivec. Simplify alignment calculations. For
ABI_V4, pass AltiVec vectors by reference when -mabi=no-altivec.
(function_arg): Similarly.
(function_arg_pass_by_reference): True for ABI_V4 AltiVec when
not AltiVec ABI.
(rs6000_va_arg): Correct fp arg test. Adjust for AltiVec change.
Correct alignment, and align before testing reg count. Remove
TREE_THIS_VOLATILE from reg. Don't emit unused labels.
(rs6000_complex_function_value): Check TARGET_HARD_FLOAT and
TARGET_FPRS here..
(rs6000_function_value): .. not here before call.
From-SVN: r81659
2004-05-07 Ziemowit Laski <zlaski@apple.com>
* config/rs6000/altivec.h (vector, pixel, bool): Do not
define as macros #ifdef __APPLE_ALTIVEC__.
From-SVN: r81641
* config/sparc/sparc-protos.h (sparc_skip_caller_unimp): New
declaration.
* config/sparc/sparc.c (SKIP_CALLERS_UNIMP_P): Delete.
(sparc_skip_caller_unimp): New global variable.
(sparc_function_epilogue): Set 'sparc_skip_caller_unimp'.
Use it instead of SKIP_CALLERS_UNIMP_P.
* config/sparc/sparc.md (call expander): Add sanity check.
(call_address_struct_value_sp32): Re-sync with expander.
(call_symbolic_struct_value_sp32): Likewise.
(return peepholes): Use 'sparc_skip_caller_unimp' instead
of custom predicate.
From-SVN: r81617
* config/rs6000/rs6000.h (STACK_BOUNDARY): Use 128 bit for either
TARGET_ALTIVEC or TARGET_ALTIVEC_ABI.
* config/rs6000/sysv4.h (ABI_STACK_BOUNDARY): Likewise.
(STACK_BOUNDARY): Delete.
From-SVN: r81597
* doc/invoke.texi: Document -mvr4130-align.
* config/mips/mips.h (MASK_VR4130_ALIGN, TARGET_VR4130_ALIGN)
(TUNE_MIPS4120, TUNE_MIPS4130): New macros.
(TUNE_MACC_CHAINS): Include TUNE_MIPS4120 and TUNE_MIPS4130.
(TARGET_SWITCHES): Add -mvr4130-align and -mno-vr4130-align.
* config/mips/mips.md: Include sched-int.h.
(USEFUL_INSN_P, SEQ_BEGIN, SEQ_END, FOR_EACH_SUBINSN): New macros.
(mips_rtx_costs): Set integer multiplication costs for TUNE_MIPS4130.
(override_options): Enable -mvr4130-align at -O3 and above.
(mips_sim_insn): New variable.
(mips_sim): New structure.
(mips_sim_reset, mips_sim_init, mips_sim_next_cycle, mips_sim_wait_reg)
(mips_sim_wait_regs_2, mips_sim_wait_regs_1, mips_sim_wait_regs)
(mips_sim_wait_units, mips_sim_wait_insn, mips_sim_record_set)
(mips_sim_issue_insn, mips_sim_issue_nop, mips_sim_finish_insn)
(vr4130_avoid_branch_rt_conflict, vr4130_align_insns): New functions.
(mips_reorg): Call vr4130_align_insns.
(vr4130_last_insn): New variable.
(vr4130_true_reg_dependence_p_1, vr4130_true_reg_dependence_p)
(vr4130_swap_insns_p, vr4130_reorder): New functions.
(mips_sched_reorder, mips_variable_issue): Hook in vr4130 code.
(mips_issue_rate): Return 2 for PROCESSOR_R4130.
(mips_use_dfa_pipeline_interface): Return true for the same.
* config/mips/4130.md: New file.
* config/mips/mips.md: Include it. Add a peephole2 to convert
"mult;mflo" into "mtlo;macc".
(*macc, *umul_acc_di, *smul_acc_di): Use $1 rather than $0 as the
target of maccs.
(*msac_using_macc): New pattern.
From-SVN: r81567
* optabs.h (enum optab_index): Add new OTI_fmod and OTI_drem.
(fmod_optab): Define corresponding macros.
* optabs.c (init_optabs): Initialize fmod_optab and drem_optab.
* genopinit.c (optabs): Implement fmod_optab and drem_optab
using fmod?f3 and drem?f3 patterns.
* builtins.c (expand_builtin_mathfn_2): Handle BUILT_IN_FMOD{,F,L}
using fmod_optab and BUILT_IN_DREM{,F,L} using drem_optab.
(expand_builtin): Expand BUILT_IN_FMOD{,F,L} and
BUILT_IN_DREM{,F,L} using expand_builtin_mathfn_2 if
flag_unsafe_math_optimizations is set.
* reg-stack.c (subst_stack_regs_pat): Handle UNSPEC_FPREM_F,
UNSPEC_FPREM_U, UNSPEC_FPREM1_F and UNSPEC_FPREM1_U.
* config/i386/i386.c (ix86_emit_fp_unordered_jump): New function.
* config/i386/i386-protos.h (ix86_emit_fp_unordered_jump):
Prototype here.
* config/i386/i386.md (UNSPEC_FPREM_F, UNSPEC_FPREM_U,
UNSPEC_FPREM1_F, UNSPEC_FPREM1_U): New unspecs to represent x87's
fprem and fprem1 instructions.
(*x86_fnstsw_1): Change input parameter to (reg:CCFP 18).
Rename insn definition to x86_fnstsw_1.
(fpremxf4, fprem1xf4): New patterns to implement fprem and fprem1
x87 instructions.
(fmodsf3, fmoddf3, fmodxf3): New expanders to implement fmodf, fmod
and fmodl built-ins as inline x87 intrinsics.
(dremsf3, dremdf3, dremxf3): New expanders to implement dremf, drem
and dreml built-ins as inline x87 intrinsics.
* testsuite/gcc.dg/builtins-40.c: New test.
From-SVN: r81555
* config/darwin-c.c (add_framework): Copy the directory name as it
can be freed later. Also, ensure we always allocate enough room
for the cached framework information.
(find_subframework_header): Keep track of the directory where the
subframework header was found.
(framework_construct_pathname): Speed up by not trying to re-add a
framework.
* cppfiles.c (search_path_exhausted): Arrange for the missing
header callback to be able to set the directory where the header
was found.
(cpp_get_dir): Add.
* cpplib.h (missing_header_cb): Add a parameter.
(cpp_get_dir): Add.
From-SVN: r81534
2004-05-05 Paolo Bonzini <bonzini@gnu.org>
* config/rs6000/rs6000.c (build_opaque_vector_type):
New function.
(rs6000_init_builtins): Use it.
From-SVN: r81509
2004-05-04 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.c (override_options): Default to no
generation of branch-likely operations when tuning for
CPUs where they tend to have a negative performance impact
(e.g., SB-1).
From-SVN: r81494
Diego Novillo
Aldy Hernandez
Fariborz Jahanian
Andrew Pinski
Kaz Kojima
Ziemowit Laski
Richard Sandiford
Alan Modra
Paul Brook
Alan Modra
Ziemowit Laski
Uros Bizjak
Eric Botcazou
Loren J. Rittle
John David Anglin
Chris Demetriou
H.J. Lu
Mike Stump
Steven Bosscher
Eric Christopher
Paolo Bonzini
Eric Botcazou
Alexandre Oliva