* tree-ssa-threadedge.c: Fix some trailing whitespace problems.
* tree-ssa-threadedge.c (thread_through_normal_block): Broken out of ...
(thread_across_edge): Here. Call it.
From-SVN: r203217
* i386.c (ix86_issue_rate): Pentium4, Nocona has issue rate of 2.
Core2, Corei7 and Haswell has issue rate of 4.
(ix86_adjust_cost): Remove ATOM case; fix core2/corei7/Haswell case.
From-SVN: r203172
2013-10-03 Wei Mi <wmi@google.com>
* lra-constraints.c (insert_move_for_subreg): New function
extracted from simplify_operand_subreg.
(simplify_operand_subreg): Add reload for paradoxical subreg.
From-SVN: r203169
* ipa-inline-analysis.c (find_foldable_builtin_expect): Find
the candidate of builtin_expect such that we should fix the
size/time estimation.
(estimate_function_body_sizes): Do the acutally size/time fix-up
for builtin_expect.
From-SVN: r203168
* predict.c (tree_predict_by_opcode): Get the probability
for builtin_expect from param builtin_expect_probability.
* params.def (BUILTIN_EXPECT_PROBABILITY): New parameter.
* predict.def (PRED_BUILTIN_EXPECT_RELAXED): Fix comments.
* doc/invoke.texi: Add documentation for builtin-expect-probability.
* gcc.target/i386/cold-attribute-2.c: Fix the test by using original
probability.
* gcc.dg/tree-ssa/ipa-split-5.c: Ditto.
* gcc.dg/tree-ssa/ipa-split-6.c: Ditto.
--This li (t)ene, and those below, will be ignored--
M gcc/params.def
M gcc/predict.def
M gcc/ChangeLog
M gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c
M gcc/testsuite/gcc.dg/tree-ssa/ipa-split-6.c
M gcc/testsuite/gcc.target/i386/cold-attribute-2.c
M gcc/predict.c
M gcc/doc/invoke.texi
From-SVN: r203167
2013-10-03 Marc Glisse <marc.glisse@inria.fr>
* libsupc++/del_op.cc (operator delete): Don't test for 0 before free.
* libsupc++/del_opnt.cc (free): Only declare if freestanding.
(operator delete): Qualify free with std::.
From-SVN: r203164
[gcc]
2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,
ceildf2, btruncdf2, instead of vsx_* name.
* config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic
iterators to only do V2DF and V4SF here. Move the DF code to
rs6000.md where it is combined with SF mode. Replace <VSv> with
just 'v' since only vector operations are handled with these insns
after moving the DF support to rs6000.md.
(vsx_sub<mode>3): Likewise.
(vsx_mul<mode>3): Likewise.
(vsx_div<mode>3): Likewise.
(vsx_fre<mode>2): Likewise.
(vsx_neg<mode>2): Likewise.
(vsx_abs<mode>2): Likewise.
(vsx_nabs<mode>2): Likewise.
(vsx_smax<mode>3): Likewise.
(vsx_smin<mode>3): Likewise.
(vsx_sqrt<mode>2): Likewise.
(vsx_rsqrte<mode>2): Likewise.
(vsx_fms<mode>4): Likewise.
(vsx_nfma<mode>4): Likewise.
(vsx_copysign<mode>3): Likewise.
(vsx_btrunc<mode>2): Likewise.
(vsx_floor<mode>2): Likewise.
(vsx_ceil<mode>2): Likewise.
(vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.
(vsx_sminsf3): Likewise.
(vsx_fmadf4): Likewise.
(vsx_fmsdf4): Likewise.
(vsx_nfmadf4): Likewise.
(vsx_nfmsdf4): Likewise.
(vsx_cmpdf_internal1): Likewise.
* config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it
simpler to select whether a target has SPE or traditional floating
point support in iterators.
(TARGET_DF_SPE): Likewise.
(TARGET_SF_FPR): Likewise.
(TARGET_DF_FPR): Likewise.
(TARGET_SF_INSN): Macros to say whether floating point support
exists for a given operation for expanders.
(TARGET_DF_INSN): Likewise.
* config/rs6000/rs6000.c (Ftrad): New mode attributes to allow
combining of SF/DF mode operations, using both traditional and VSX
registers.
(Fvsx): Likewise.
(Ff): Likewise.
(Fv): Likewise.
(Fs): Likewise.
(Ffre): Likewise.
(FFRE): Likewise.
(abs<mode>2): Combine SF/DF modes using traditional floating point
instructions. Add support for using the upper DF registers with
VSX support, and SF registers with power8-vector support. Update
expanders for operations supported by both the SPE and traditional
floating point units.
(abs<mode>2_fpr): Likewise.
(nabs<mode>2): Likewise.
(nabs<mode>2_fpr): Likewise.
(neg<mode>2): Likewise.
(neg<mode>2_fpr): Likewise.
(add<mode>3): Likewise.
(add<mode>3_fpr): Likewise.
(sub<mode>3): Likewise.
(sub<mode>3_fpr): Likewise.
(mul<mode>3): Likewise.
(mul<mode>3_fpr): Likewise.
(div<mode>3): Likewise.
(div<mode>3_fpr): Likewise.
(sqrt<mode>3): Likewise.
(sqrt<mode>3_fpr): Likewise.
(fre<Fs>): Likewise.
(rsqrt<mode>2): Likewise.
(cmp<mode>_fpr): Likewise.
(smax<mode>3): Likewise.
(smin<mode>3): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(negsf2): Delete SF operations that are merged with DF.
(abssf2): Likewise.
(addsf3): Likewise.
(subsf3): Likewise.
(mulsf3): Likewise.
(divsf3): Likewise.
(fres): Likewise.
(fmasf4_fpr): Likewise.
(fmssf4_fpr): Likewise.
(nfmasf4_fpr): Likewise.
(nfmssf4_fpr): Likewise.
(sqrtsf2): Likewise.
(rsqrtsf_internal1): Likewise.
(smaxsf3): Likewise.
(sminsf3): Likewise.
(cmpsf_internal1): Likewise.
(copysign<mode>3_fcpsgn): Add VSX/power8-vector support.
(negdf2): Delete DF operations that are merged with SF.
(absdf2): Likewise.
(nabsdf2): Likewise.
(adddf3): Likewise.
(subdf3): Likewise.
(muldf3): Likewise.
(divdf3): Likewise.
(fred): Likewise.
(rsqrtdf_internal1): Likewise.
(fmadf4_fpr): Likewise.
(fmsdf4_fpr): Likewise.
(nfmadf4_fpr): Likewise.
(nfmsdf4_fpr): Likewise.
(sqrtdf2): Likewise.
(smaxdf3): Likewise.
(smindf3): Likewise.
(cmpdf_internal1): Likewise.
(lrint<mode>di2): Use TARGET_<MODE>_FPR macro.
(btrunc<mode>2): Delete separate expander, and combine with the
insn and add VSX instruction support. Use TARGET_<MODE>_FPR.
(btrunc<mode>2_fpr): Likewise.
(ceil<mode>2): Likewise.
(ceil<mode>2_fpr): Likewise.
(floor<mode>2): Likewise.
(floor<mode>2_fpr): Likewise.
(fma<mode>4_fpr): Combine SF and DF fused multiply/add support.
Add support for using the upper registers with VSX and
power8-vector. Move insns to be closer to the define_expands. On
VSX systems, prefer the traditional form of FMA over the VSX
version, since the traditional form allows the target not to
overlap with the inputs.
(fms<mode>4_fpr): Likewise.
(nfma<mode>4_fpr): Likewise.
(nfms<mode>4_fpr): Likewise.
[gcc/testsuite]
2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-fp.c: New test for floating point
scalar operations when using -mupper-regs-sf and -mupper-regs-df.
* gcc.target/powerpc/ppc-target-1.c: Update tests to allow either
VSX scalar operations or the traditional floating point form of
the instruction.
* gcc.target/powerpc/ppc-target-2.c: Likewise.
* gcc.target/powerpc/recip-3.c: Likewise.
* gcc.target/powerpc/recip-5.c: Likewise.
* gcc.target/powerpc/pr72747.c: Likewise.
* gcc.target/powerpc/vsx-builtin-3.c: Likewise.
From-SVN: r203162
PR58460, the add and sub shifted register instruction forms in AArch64
do not permit the stack register. This patch removes k constraint
from the relevant patterns and adds reduced form of the test case.
From-SVN: r203157
2013-10-02 Vladimir Makarov <vmakarov@redhat.com>
* lra-constraints.c (process_alt_operand): Calculate scratch_p and
use it. Use smaller increase for scratch. Don't increase reject
for early clobber scratch.
* lra-eliminations.c (eliminate_regs_in_insn): Remove all insns
setting eliminated regs except setting fp from hfp.
(lra_eliminate): Check lra_insn_recog_data on NULL.
From-SVN: r203147
2013-10-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/58587
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off
setting -mvsx-timode by default until the underlying problem is
fixed.
(RS6000_CPU, power7 defaults): Likewise.
From-SVN: r203142
2013-10-02 Jonathan Wakely <jwakely.gcc@gmail.com>
Daniel Krugler <daniel.kruegler@gmail.com>
PR libstdc++/58569
* include/std/functional (function::_CheckResult): Move to namespace
scope and rename to __check_func_return_type.
* testsuite/20_util/function/58569.cc: New.
Co-Authored-By: Daniel Kruegler <daniel.kruegler@gmail.com>
From-SVN: r203132
* go-gcc.cc: Include "real.h" and "realmpfr.h".
(Backend::integer_constant_expression): New function.
(Backend::float_constant_expression): New function.
(Backend::complex_constant_expression): New function.
From-SVN: r203127
This patch fixes an issue where expansion of an ORIF expression arbitrarily
applied the probability that the entire condition was true to just the
first condition. When the ORIF true probability was 100%, this resulted
in the second condition's jump being given a count of zero (since the
first condition's jump got 100% of the count), leading to incorrect function
splitting when it had a non-zero probability in reality. Since there
currently isn't better information about which condition resulted
in the ORIF being true, apply a 50-50 probability that it is the first
vs. second condition that caused the entire expression to be true,
so that neither condition's true label ends up as a 0-count bb.
An equivalent fix is made for ANDIF expansion.
2013-10-02 Teresa Johnson <tejohnson@google.com>
* dojump.c (do_jump_1): Divide probability between
both conditions of a TRUTH_ORIF_EXPR.
From-SVN: r203126
