Commit Graph

174074 Commits

Author SHA1 Message Date
Jakub Jelinek
ea69031c5f re PR tree-optimization/93210 (Sub-optimal code optimization on struct/combound constexpr (gcc vs. clang))
PR tree-optimization/93210
	* fold-const.h (native_encode_initializer,
	can_native_interpret_type_p): Declare.
	* fold-const.c (native_encode_string): Fix up handling with off != -1,
	simplify.
	(native_encode_initializer): New function, moved from dwarf2out.c.
	Adjust to native_encode_expr compatible arguments, including dry-run
	and partial extraction modes.  Don't handle STRING_CST.
	(can_native_interpret_type_p): No longer static.
	* gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
	offset / BITS_PER_UNIT fits into int and don't call it if
	can_native_interpret_type_p fails.  If suboff is NULL and for
	CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
	native_encode_initializer.
	(fold_const_aggregate_ref_1): Formatting fix.
	* dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
	(tree_add_const_value_attribute): Adjust caller.

	* gcc.dg/pr93210.c: New test.
	* g++.dg/opt/pr93210.C: New test.

From-SVN: r280141
2020-01-10 22:18:22 +01:00
Jakub Jelinek
974bb8a4dc re PR tree-optimization/90838 (Detect table-based ctz implementation)
PR tree-optimization/90838
	* tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
	SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
	CTZ_DEFINED_VALUE_AT_ZERO.

From-SVN: r280140
2020-01-10 22:10:03 +01:00
Vladimir Makarov
a29a9962ea re PR inline-asm/93027 (ICE: in match_reload, at lra-constraints.c:1060)
2020-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR inline-asm/93027
	* gcc.target/i386/pr93027.c: Use the right PR number in the test.

From-SVN: r280138
2020-01-10 20:45:19 +00:00
Jakub Jelinek
91df4397a1 re PR libgomp/93219 (unused return value in affinity-fmt.c)
PR libgomp/93219
	* libgomp.h (gomp_print_string): Change return type from void to int.
	* affinity-fmt.c (gomp_print_string): Likewise.  Return true if
	not all characters have been written.

From-SVN: r280137
2020-01-10 21:42:00 +01:00
Vladimir Makarov
530cfcd7b1 Rename pr93207.c to pr93027.c. Fix PR number in change logs.
From-SVN: r280136
2020-01-10 20:27:48 +00:00
Vladimir Makarov
6f9dc60621 re PR inline-asm/93027 (ICE: in match_reload, at lra-constraints.c:1060)
2020-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR inline-asm/93207
	* gcc.target/i386/pr93207.c: Run it only for x86-64.

From-SVN: r280135
2020-01-10 20:18:00 +00:00
David Malcolm
83f604e706 testsuite: add dg-enable-nn-line-numbers
This patch adds support for obscuring the line numbers printed in the
left-hand margin when printing the source code, converting them to "NN",
e.g from:

  7111 |   if (!(flags & 0x0001)) {
       |      ^
       |      |
       |      (1) following 'true' branch...
  7112 |

to:

   NN  |   if (!(flags & 0x0001)) {
       |      ^
       |      |
       |      (1) following 'true' branch...
   NN  |

This is useful in followup patches e.g. when testing how interprocedural
paths are printed using multiline.exp, to avoid depending on precise line
numbers.

gcc/testsuite/ChangeLog:
	* lib/gcc-dg.exp (cleanup-after-saved-dg-test): Reset global
	nn_line_numbers_enabled.
	* lib/multiline.exp (nn_line_numbers_enabled): New global.
	(dg-enable-nn-line-numbers): New proc.
	(maybe-handle-nn-line-numbers): New proc.
	* lib/prune.exp (prune_gcc_output): Call maybe-handle-nn-line-numbers.

From-SVN: r280134
2020-01-10 20:14:31 +00:00
Vladimir Makarov
60257913f8 re PR inline-asm/93027 (ICE: in match_reload, at lra-constraints.c:1060)
2020-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR inline-asm/93207
	* lra-constraints.c (match_reload): Permit input operands have the
	same mode as output while other input operands have a different
	mode.

2020-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR inline-asm/93207
	* gcc.target/i386/pr93207.c: New test.

From-SVN: r280133
2020-01-10 20:07:45 +00:00
Wilco Dijkstra
b937050d30 PR90838: Support ctz idioms
Support common idioms for count trailing zeroes using an array lookup.
The canonical form is array[((x & -x) * C) >> SHIFT] where C is a magic
constant which when multiplied by a power of 2 creates a unique value
in the top 5 or 6 bits.  This is then indexed into a table which maps it
to the number of trailing zeroes.  When the table is valid, we emit a
sequence using the target defined value for ctz (0):

int ctz1 (unsigned x)
{
  static const char table[32] =
    {
      0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
      31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
    };

  return table[((unsigned)((x & -x) * 0x077CB531U)) >> 27];
}

Is optimized to:

	rbit	w0, w0
	clz	w0, w0
	and	w0, w0, 31
	ret

    gcc/
	PR tree-optimization/90838
	* tree-ssa-forwprop.c (check_ctz_array): Add new function.
	(check_ctz_string): Likewise.
	(optimize_count_trailing_zeroes): Likewise.
	(simplify_count_trailing_zeroes): Likewise.
	(pass_forwprop::execute): Try ctz simplification.
	* match.pd: Add matching for ctz idioms.

    testsuite/
	PR tree-optimization/90838
	* testsuite/gcc.target/aarch64/pr90838.c: New test.

From-SVN: r280132
2020-01-10 19:32:53 +00:00
Stam Markianos-Wright
9869896730 aarch64.c (aarch64_invalid_conversion): New function for target hook.
gcc/ChangeLog:

2020-01-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
	for target hook.
	(aarch64_invalid_unary_op): New function for target hook.
	(aarch64_invalid_binary_op): New function for target hook.

gcc/testsuite/ChangeLog:

2020-01-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* g++.target/aarch64/bfloat_cpp_typecheck.C: New test.
	* gcc.target/aarch64/bfloat16_scalar_typecheck.c: New test.
	* gcc.target/aarch64/bfloat16_vector_typecheck_1.c: New test.
	* gcc.target/aarch64/bfloat16_vector_typecheck_2.c: New test.

From-SVN: r280130
2020-01-10 19:29:36 +00:00
Stam Markianos-Wright
abbe1ed273 config.gcc: Add arm_bf16.h.
2020-01-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config.gcc: Add arm_bf16.h.
	* config/aarch64/aarch64-builtins.c
	(aarch64_simd_builtin_std_type): Add BFmode.
	(aarch64_init_simd_builtin_types): Define element types for vector
	types.
	(aarch64_init_bf16_types): New function.
	(aarch64_general_init_builtins): Add arm_init_bf16_types function call.
	* config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
	modes.
	* config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
	* config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
	patterns.
	* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
	(AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
	* config/aarch64/aarch64.c
	(aarch64_classify_vector_mode): Add support for BF types.
	(aarch64_gimplify_va_arg_expr): Add support for BF types.
	(aarch64_vq_mode): Add support for BF types.
	(aarch64_simd_container_mode): Add support for BF types.
	(aarch64_mangle_type): Add support for BF scalar type.
	* config/aarch64/aarch64.md: Add BFmode to movhf pattern.
	* config/aarch64/arm_bf16.h: New file.
	* config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
	* config/aarch64/iterators.md: Add BF types to mode attributes.
	(HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.

2020-01-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* g++.dg/abi/mangle-neon-aarch64.C: Add Bfloat SIMD types to test.
	* g++.dg/ext/arm-bf16/bf16-mangle-aarch64-1.C: New test.
	* gcc.target/aarch64/bfloat16_scalar_1.c: New test.
	* gcc.target/aarch64/bfloat16_scalar_2.c: New test.
	* gcc.target/aarch64/bfloat16_scalar_3.c: New test.
	* gcc.target/aarch64/bfloat16_scalar_4.c: New test.
	* gcc.target/aarch64/bfloat16_simd_1.c: New test.
	* gcc.target/aarch64/bfloat16_simd_2.c: New test.
	* gcc.target/aarch64/bfloat16_simd_3.c: New test.

From-SVN: r280129
2020-01-10 19:23:41 +00:00
Jason Merrill
337ea6b216 Shorten right-shift again in C++.
Back in SVN r131862 richi removed this code to fix PR 34235, but didn't
remove the parallel code from the C front-end because the bug had previously
been fixed in r44080.  This patch copies the code from C again.

	* typeck.c (cp_build_binary_op): Restore short_shift code.

From-SVN: r280128
2020-01-10 13:53:17 -05:00
Jason Merrill
e0804c9b5e PR c++/93143 - incorrect tree sharing with constexpr.
We don't unshare CONSTRUCTORs as often during constexpr evaluation, so we
need to unshare them here.

	* constexpr.c (cxx_eval_outermost_constant_expr): Don't assume
	CONSTRUCTORs are already unshared.

From-SVN: r280127
2020-01-10 13:47:02 -05:00
Jason Merrill
640b23d7ff PR c++/93173 - incorrect tree sharing.
My patch for 93033 wasn't sufficient to handle all the possible sharing
introduced by split_nonconstant_init, and it occurred to me that it would
make sense to use the same unsharing technique as unshare_body, namely
copy_if_shared.

	PR c++/93033
gcc/
	* gimplify.c (copy_if_shared): No longer static.
	* gimplify.h: Declare it.
gcc/cp/
	* cp-gimplify.c (cp_gimplify_init_expr, cp_gimplify_expr): Use
	copy_if_shared after cp_genericize_tree.
	* typeck2.c (split_nonconstant_init): Don't unshare here.

From-SVN: r280126
2020-01-10 13:46:57 -05:00
Richard Sandiford
9b0700571f [AArch64] Make -msve-vector-bits=128 generate VL-specific code
related_vector_mode and compatible_vector_types_p make it possible
to generate 128-bit SVE code while still maintaining the distinction
between SVE vectors and Advanced SIMD vectors.  We can therefore generate
VL-specific code for -msve-vector-bits=128 on little-endian targets.
In theory we could do the same for big-endian targets, but it could
have quite a high overhead; see the comment in the patch for details.

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* doc/invoke.texi (-msve-vector-bits=): Document that
	-msve-vector-bits=128 now generates VL-specific code for
	little-endian targets.
	* config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
	build_vector_type_for_mode to construct the data vector types.
	* config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
	VL-specific code for -msve-vector-bits=128 on little-endian targets.
	(aarch64_simd_container_mode): Always prefer Advanced SIMD modes
	for 128-bit vectors.

gcc/testsuite/
	* gcc.target/aarch64/sve/struct_vect_1.c (N): Protect with #ifndef.
	* gcc.target/aarch64/sve/pcs/return_1_128.c: New test.
	* gcc.target/aarch64/sve/pcs/return_4_128.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_5_128.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_6_128.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_128.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_128.c: Likewise.
	* gcc.target/aarch64/sve/single_5.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_25.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_26.c: Likewise.

From-SVN: r280125
2020-01-10 18:44:39 +00:00
Martin Sebor
f25e33fa1b PR c/93132 - bogus 'attribute((access))' warning when size-index is specified
gcc/c-family/ChangeLog:

	PR c/93132
	* c-attribs.c (append_access_attrs): Validate against the translated
	access string rather than the human-readable representation.

gcc/testsuite/ChangeLog:

	PR c/93132
	* gcc.dg/attr-access-read-only-2.c: New test.

From-SVN: r280124
2020-01-10 10:04:00 -07:00
Richard Sandiford
b2f5b38042 [AArch64] Fix reversed vcond_mask invocation in aarch64_evpc_sel
aarch64_evpc_sel (new in GCC 10) got the true and false vectors
the wrong way round, leading to execution failures with fixed-length
128-bit SVE.

Now that the ACLE types are in trunk, it's much easier to match
the exact asm sequence for a permute.

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
	invocation.

gcc/testsuite/
	* gcc.target/aarch64/sve/sel_1.c: Use SVE types for the arguments and
	return values.  Use check-function-bodies instead of scan-assembler.
	* gcc.target/aarch64/sve/sel_2.c: Likewise
	* gcc.target/aarch64/sve/sel_3.c: Likewise.

From-SVN: r280121
2020-01-10 16:31:13 +00:00
Ian Lance Taylor
3a33f87ffb gotest: don't use local
It's not part of the POSIX shell standard.
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/214300

From-SVN: r280118
2020-01-10 15:28:20 +00:00
Jonathan Wakely
78f02e8003 libstdc++: Fix testcase for C++98 compatibility
* testsuite/25_algorithms/equal/deque_iterators/1.cc: Don't use C++11
	initialization syntax.

From-SVN: r280117
2020-01-10 15:27:50 +00:00
Jonathan Wakely
7918cb93f6 libstdc++: Make istreambuf_iterator base class consistent (PR92285)
Since LWG 445 was implemented for GCC 4.7, the std::iterator base class
of std::istreambuf_iterator changes type depending on the -std mode
used. This creates an ABI incompatibility between different -std modes.

This change ensures the base class always has the same type. This makes
layout for C++98 compatible with the current -std=gnu++14 default, but
no longer compatible with C++98 code from previous releases. In practice
this is unlikely to cause real problems, because it only affects the
layout of types with two std::iterator base classes, one of which comes
from std::istreambuf_iterator. Such types are expected to be vanishingly
rare.

	PR libstdc++/92285
	* include/bits/streambuf_iterator.h (istreambuf_iterator): Make type
	of base class independent of __cplusplus value.
	[__cplusplus < 201103L] (istreambuf_iterator::reference): Override the
	type defined in the base class
	* testsuite/24_iterators/istreambuf_iterator/92285.cc: New test.
	* testsuite/24_iterators/istreambuf_iterator/requirements/
	base_classes.cc: Adjust expected base class for C++98.

From-SVN: r280116
2020-01-10 15:27:39 +00:00
Tobias Burnus
d5c23c6cea OpenACC – support "if" + "if_present" clauses with "host_data"
2020-01-10  Gergö Barany  <gergo@codesourcery.com>
	    Thomas Schwinge <thomas@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tobias Burnus  <tobias@codesourcery.com>

        gcc/c/
        * c-parser.c (OACC_HOST_DATA_CLAUSE_MASK): Add PRAGMA_OACC_CLAUSE_IF
        and PRAGMA_OACC_CLAUSE_IF_PRESENT.

        gcc/cp/
        * parser.c (OACC_HOST_DATA_CLAUSE_MASK): Add PRAGMA_OACC_CLAUSE_IF
        and PRAGMA_OACC_CLAUSE_IF_PRESENT.

        gcc/fortran/
        * openmp.c (OACC_HOST_DATA_CLAUSES): Add PRAGMA_OACC_CLAUSE_IF
        and PRAGMA_OACC_CLAUSE_IF_PRESENT.

	gcc/
	* omp-low.c (lower_omp_target): Use GOMP_MAP_USE_DEVICE_PTR_IF_PRESENT
	if PRAGMA_OACC_CLAUSE_IF_PRESENT exist.

	gcc/testsuite/
	* c-c++-common/goacc/host_data-1.c: Added tests of if and if_present
	clauses on host_data.
	* gfortran.dg/goacc/host_data-tree.f95: Likewise.

	include/
	* gomp-constants.h (enum gomp_map_kind): New enumeration constant
	GOMP_MAP_USE_DEVICE_PTR_IF_PRESENT.
        
	libgomp/
	* oacc-parallel.c (GOACC_data_start): Handle
	GOMP_MAP_USE_DEVICE_PTR_IF_PRESENT.
	* target.c (gomp_map_vars_async): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/host_data-7.c: New.
	* testsuite/libgomp.oacc-fortran/host_data-5.F90: New.

From-SVN: r280115
2020-01-10 16:08:41 +01:00
Richard Sandiford
7cee96370c [AArch64] Tighten mode checks in aarch64_builtin_vectorized_function
aarch64_builtin_vectorized_function checked vectors based on the
number of elements and the element mode.  This doesn't interact
well with fixed-length 128-bit SVE, where SVE modes can have those
same properties.  (And we can't just use the built-ins for SVE because
the types use a different ABI.  SVE handles this kind of thing using
optabs instead.)

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-builtins.c
	(aarch64_builtin_vectorized_function): Check for specific vector modes,
	rather than checking the number of elements and the element mode.

From-SVN: r280114
2020-01-10 15:05:40 +00:00
Richard Sandiford
d29c7f605f Use get_related_vectype_for_scalar_type for reduction indices
The related_vector_mode series missed this case in
vect_create_epilog_for_reduction, where we want to create the
unsigned integer equivalent of another vector.  Without it we
could mix SVE and Advanced SIMD vectors in the same operation.

This showed up on existing tests when testing with fixed-length
-msve-vector-bits=128.

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-loop.c (vect_create_epilog_for_reduction): Use
	get_related_vectype_for_scalar_type rather than build_vector_type
	to create the index type for a conditional reduction.

From-SVN: r280112
2020-01-10 14:56:31 +00:00
Richard Sandiford
ac190fcea1 Fix gather/scatter check when updating a vector epilogue loop
update_epilogue_loop_vinfo applies SSA renmaing to the DR_REF of a
gather or scatter, so that vect_check_gather_scatter continues to work.
However, we sometimes also rely on vect_check_gather_scatter when
using gathers and scatters to implement strided accesses.

This showed up on existing tests when testing with fixed-length
-msve-vector-bits=128.

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
	for any type of gather or scatter, including strided accesses.

From-SVN: r280111
2020-01-10 14:56:20 +00:00
Ian Lance Taylor
2fb672a257 compiler: permit duplicate methods from embedded interfaces
This is a language change for Go 1.14.
    
    Updates golang/go#6977
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/214240

From-SVN: r280109
2020-01-10 14:27:05 +00:00
Andre Vieira
9c158322b6 [vect] Add missing comment
gcc/ChangeLog:
2020-01-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
	 comment.

From-SVN: r280108
2020-01-10 13:48:35 +00:00
Andre Vieira
67723321fb [vect] Keep track of DR_OFFSET advance in dr_vec_info rather than data_reference
gcc/ChangeLog:
2020-01-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
	get_dr_vinfo_offset
	* tree-vect-loop.c (update_epilogue_loop_vinfo):  Remove orig_drs_init
	parameter and its use to reset DR_OFFSET's.
	(vect_transform_loop): Remove orig_drs_init argument.
	* tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
	member of dr_vec_info rather than the offset of the associated
	data_reference's innermost_loop_behavior.
	(vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
	(vect_do_peeling): Remove orig_drs_init parameter and its construction.
	* tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
	get_dr_vinfo_offset.
	(vectorizable_store): Likewise.
	(vectorizable_load): Likewise.

From-SVN: r280107
2020-01-10 13:33:10 +00:00
Richard Biener
6b412bf65c 2020-01-10 Richard Biener <rguenther@suse.de>
* gimple-ssa-store-merging
	(pass_store_merging::terminate_all_aliasing_chains): Cache alias info.

From-SVN: r280106
2020-01-10 13:24:04 +00:00
Martin Jambor
bd6e6e0a3c Fix ipa-clone-3.c on some targets
2020-01-10  Martin Jambor  <mjambor@suse.cz>

	* gcc.dg/ipa/ipa-clone-3.c: Replace struct initializer with
	piecemeal initialization.

From-SVN: r280105
2020-01-10 14:16:44 +01:00
Richard Sandiford
74d121b3ae [AArch64] Require aarch64_sve256_hw for a 256-bit SVE test
One of the SVE run tests was specific to 256-bit SVE but tried to
run for all SVE lengths.

2020-01-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/sve/index_1_run.c: Require aarch64_sve256_hw
	rather than aarch64_sve_hw.

From-SVN: r280104
2020-01-10 12:51:32 +00:00
Martin Liska
7e2b7e2335 Fix wrong parenthesis in inliner.
2020-01-10  Martin Liska  <mliska@suse.cz>

	PR ipa/93217
	* ipa-inline-analysis.c (offline_size): Make proper parenthesis
	encapsulation that was there before r280040.

From-SVN: r280103
2020-01-10 12:27:36 +00:00
Richard Biener
734efcdda9 re PR tree-optimization/93199 (Compile time hog in sink_clobbers)
2020-01-10  Richard Biener  <rguenther@suse.de>

	PR middle-end/93199
	* tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
	sequences to avoid walking them again for secondary opportunities.
	(pass_lower_eh_dispatch::execute): Instead actually insert
	them here.

From-SVN: r280102
2020-01-10 11:23:53 +00:00
Richard Biener
5eaf0c498f re PR tree-optimization/93199 (Compile time hog in sink_clobbers)
2020-01-10  Richard Biener  <rguenther@suse.de>

	PR middle-end/93199
	* tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
	(cleanup_all_empty_eh): Walk landing pads in reverse order to
	avoid quadraticness.

From-SVN: r280101
2020-01-10 10:49:57 +00:00
Martin Jambor
1a315435db IPA-CP: Access param_ipa_sra_max_replacements through opt_for_fn
2020-01-10  Martin Jambor  <mjambor@suse.cz>

	* params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
	* ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
	to get param_ipa_sra_max_replacements.
	(param_splitting_across_edge): Pass the caller to
	pull_accesses_from_callee.

From-SVN: r280100
2020-01-10 11:01:33 +01:00
Martin Jambor
f7725a4883 IPA-CP: Always access param_ipcp_unit_growth through opt_for_fn
2020-01-10  Martin Jambor  <mjambor@suse.cz>

	* params.opt (param_ipcp_unit_growth): Mark as Optimization.
	* ipa-cp.c (max_new_size): Removed.
	(orig_overall_size): New variable.
	(get_max_overall_size): New function.
	(estimate_local_effects): Use it.  Adjust dump.
	(decide_about_value): Likewise.
	(ipcp_propagate_stage): Do not calculate max_new_size, just store
	orig_overall_size.  Adjust dump.
	(ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.

From-SVN: r280099
2020-01-10 11:00:05 +01:00
Martin Jambor
de2e08355a IPA-CP: Always access param_ipa_max_agg_items through opt_for_fn
2020-01-10  Martin Jambor  <mjambor@suse.cz>

	* params.opt (param_ipa_max_agg_items): Mark as Optimization
	* ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
	instead of param_ipa_max_agg_items.
	(merge_aggregate_lattices): Extract param_ipa_max_agg_items from
	optimization info for the callee.

From-SVN: r280098
2020-01-10 10:57:59 +01:00
Richard Biener
8509584524 re PR testsuite/93216 (gcc.dg/optimize-bswaphi-1.c fails starting with r280034)
2020-01-10  Richard Biener  <rguenther@suse.de>

	PR testsuite/93216
	* gcc.dg/optimize-bswaphi-1.c: Split previously added
	case into a LE and BE variant.

From-SVN: r280097
2020-01-10 08:18:09 +00:00
GCC Administrator
daacc1a898 Daily bump.
From-SVN: r280096
2020-01-10 00:16:15 +00:00
Ian Lance Taylor
fcee603081 libgo: compile examples in _test packages
Previously if the only names defined by _test packages were examples,
    the gotest script would emit an incorrect _testmain.go file.
    I worked around that by marking the example_test.go files +build ignored.
    
    This CL changes the gotest script to handle this case correctly,
    and removes the now-unnecessary build tags.
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/214039

From-SVN: r280085
2020-01-09 23:14:57 +00:00
Olivier Hainque
acd43917df rename local _C2 identifiers in stl map header files
2020-01-09  Olivier Hainque  <hainque@adacore.com>

	* doc/xml/manual/appendix_contributing.xml: Document _C2
	as a reserved identifier, by VxWorks.
	* include/bits/stl_map.h: Rename _C2 template typenames	as _Cmp2.
	* include/bits/stl_multimap.h: Likewise.

From-SVN: r280076
2020-01-09 23:00:50 +00:00
Jonathan Wakely
1a7886386c libstdc++: Fix <ext/pointer.h> incompatibilities with C++20
The equality operators for _ExtPtr_allocator are defined as non-const
member functions, which causes ambiguities in C++20 due to the
synthesized operator!= candidates. They should always have been const.

The _Pointer_adapter class template has both value_type and element_type
members, which makes readable_traits<_Pointer_adapter<T>> ambiguous. The
intended workaround is to add a specialization of readable_traits.

	* include/ext/extptr_allocator.h (_ExtPtr_allocator::operator==)
	(_ExtPtr_allocator::operator!=): Add missing const qualifiers.
	* include/ext/pointer.h (readable_traits<_Pointer_adapter<S>>): Add
	partial specialization to disambiguate the two constrained
	specializations.

From-SVN: r280067
2020-01-09 21:31:55 +00:00
Jonathan Wakely
caa39b2e84 libstdc++: Fix testsuite failures and warnings due to is_pod deprecation
With -std=gnu++2a and -Wsystem-headers the std::is_pod deprecation
causes some new diagnostics. This suppresses them.

	* include/experimental/type_traits (experimental::is_pod_v): Disable
	-Wdeprecated-declarations warnings around reference to std::is_pod.
	* include/std/type_traits (is_pod_v): Likewise.
	* testsuite/18_support/max_align_t/requirements/2.cc: Also check
	is_standard_layout and is_trivial. Do not check is_pod for C++20.
	* testsuite/20_util/is_pod/requirements/explicit_instantiation.cc:
	Add -Wno-deprecated for C++20.
	* testsuite/20_util/is_pod/requirements/typedefs.cc: Likewise.
	* testsuite/20_util/is_pod/value.cc: Likewise.
	* testsuite/experimental/type_traits/value.cc: Likewise.

From-SVN: r280066
2020-01-09 21:31:50 +00:00
JeanHeyd "ThePhD" Meneide
1a6c5064f9 libstdc++: Implementing P0767 - deprecate POD
This adds the deprecated attribute to std::is_pod and std::is_pod_v for
C++20.

2019-12-05  JeanHeyd "ThePhD" Meneide  <phdofthehouse@gmail.com>

	* include/bits/c++config (_GLIBCXX20_DEPRECATED): Add new macro.
	* include/std/type_traits (is_pod, is_pod_v): Deprecate for C++20.
	* testuite/20_util/is_pod/deprecated-2a.cc: New test.

From-SVN: r280065
2020-01-09 21:31:43 +00:00
Jonathan Wakely
ab3a095c4b libstdc++: Fix whitespace in ChangeLog-2019
From-SVN: r280064
2020-01-09 21:31:35 +00:00
Thomas Koenig
d636017868 Save typespec for empty array constructor.
2020-01-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/65428
	* array.c (empty_constructor): New variable.
	(empty_ts): New variable.
	(expand_constructor): Save typespec in empty_ts.
	Unset empty_constructor if there is an element.
	(gfc_expand_constructor): Initialize empty_constructor
	and empty_ts.  If there was no explicit constructor
	type and the constructor is empty, take the type from
	empty_ts.

2020-01-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/65428
	* gfortran.dg/zero_sized_11.f90: New test.

From-SVN: r280063
2020-01-09 20:57:33 +00:00
Kwok Cheung Yeung
2b8ce6216e Remove inline debug markers if support not enabled on accelerator compiler
2020-01-09  Kwok Cheung Yeung  <kcy@codesourcery.com>

	gcc/
	* lto-streamer-in.c (input_function): Remove streamed-in inline debug
	markers	if debug_inline_points is false.

From-SVN: r280062
2020-01-09 16:52:23 +00:00
Jonathan Wakely
160e95dc3d libstdc++: Fix undefined behaviour in random dist serialization (PR93205)
The deserialization functions for random number distributions fail to
check the stream state before using the extracted values. In some cases
this leads to using indeterminate values to resize a vector, and then
filling that vector with indeterminate values.

No values that affect control flow should be used without checking that a
good value was read from the stream.

Additionally, where reasonable to do so, defer modifying any state in
the distribution until all values have been successfully read, to avoid
modifying some of the distribution's parameters and leaving others
unchanged.

	PR libstdc++/93205
	* include/bits/random.h (operator>>): Check stream operation succeeds.
	* include/bits/random.tcc (operator<<): Remove redundant __ostream_type
	typedefs.
	(operator>>): Remove redundant __istream_type typedefs. Check stream
	operations succeed.
	(__extract_params): New function to fill a vector from a stream.
	* testsuite/26_numerics/random/pr60037-neg.cc: Adjust dg-error line.

From-SVN: r280061
2020-01-09 16:50:51 +00:00
Richard Sandiford
0a09a94838 [AArch64] Add support for the SVE2 ACLE
This patch adds support for the SVE2 ACLE,  The implementation
and tests follow the same pattern as the exiting SVE ACLE support.

2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
	extra_objs.
	* config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
	aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
	aarch64-sve-builtins-sve2.h.
	(aarch64-sve-builtins-sve2.o): New rule.
	* config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
	(AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
	(AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
	(TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
	TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
	TARGET_SVE2_SM4.
	* config/aarch64/aarch64-sve.md: Update comments with SVE2
	instructions that are handled here.
	(@cond_asrd<mode>): Generalize to...
	(@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
	(*cond_asrd<mode>_2): Generalize to...
	(*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
	(*cond_asrd<mode>_z): Generalize to...
	(*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
	* config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
	(UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
	(UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
	* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
	pattern.
	(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
	(@aarch64_scatter_stnt<mode>): Likewise.
	(@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
	(@aarch64_mul_lane_<mode>): Likewise.
	(@aarch64_sve_suqadd<mode>_const): Likewise.
	(*<sur>h<addsub><mode>): Generalize to...
	(@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
	new pattern.
	(@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
	(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
	(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
	(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
	(*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
	(@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
	(@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
	(@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
	(@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
	(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
	(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
	(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
	(@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_add_mul_lane_<mode>): Likewise.
	(@aarch64_sve_sub_mul_lane_<mode>): Likewise.
	(@aarch64_sve2_xar<mode>): Likewise.
	(@aarch64_sve2_bcax<mode>): Likewise.
	(*aarch64_sve2_eor3<mode>): Rename to...
	(@aarch64_sve2_eor3<mode>): ...this.
	(@aarch64_sve2_bsl<mode>): New expander.
	(@aarch64_sve2_nbsl<mode>): Likewise.
	(@aarch64_sve2_bsl1n<mode>): Likewise.
	(@aarch64_sve2_bsl2n<mode>): Likewise.
	(@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
	(*aarch64_sve2_sra<mode>): Add MOVPRFX support.
	(@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
	(@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
	(@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
	(*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
	(@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
	(<su>mull<bt><Vwide>): Generalize to...
	(@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
	pattern.
	(@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
	(@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
	(@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
	(@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
	(@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
	(@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
	(@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
	(@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
	(@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
	(<SHRNB:r>shrnb<mode>): Generalize to...
	(@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
	new pattern.
	(<SHRNT:r>shrnt<mode>): Generalize to...
	(@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
	new pattern.
	(@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
	(@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
	(@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
	(*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
	(*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
	(@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
	(@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
	(@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
	(@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
	(@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
	(*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
	(@aarch64_sve2_cvtnt<mode>): Likewise.
	(@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
	(@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
	(*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
	(@aarch64_sve2_cvtxnt<mode>): Likewise.
	(@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
	(@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
	(*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
	(@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
	(@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
	(*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
	(@aarch64_sve2_pmul<mode>): Likewise.
	(@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
	(@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
	(@aarch64_sve2_tbl2<mode>): Likewise.
	(@aarch64_sve2_tbx<mode>): Likewise.
	(@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
	(@aarch64_sve2_histcnt<mode>): Likewise.
	(@aarch64_sve2_histseg<mode>): Likewise.
	(@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
	(*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
	(*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
	(aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
	(aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
	(*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
	(aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
	(<su>mulh<r>s<mode>3): Update after above pattern name changes.
	* config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
	(SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
	(SVE2_PMULL_PAIR_I): New mode iterators.
	(UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
	(UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
	(UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
	(UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
	(UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
	(UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
	(UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
	(UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
	(UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
	(UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
	(UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
	(UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
	(UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
	(UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
	(UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
	(UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
	(UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
	(UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
	(UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
	(UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
	(UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
	(UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
	(UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
	(UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
	(UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
	(UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
	(UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
	(UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
	(UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
	(UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
	(UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
	further down file.
	(VNARROW, Ventype): New mode attributes.
	(Vewtype): Handle VNx2DI.  Fix typo in comment.
	(VDOUBLE): New mode attribute.
	(sve_lane_con): Handle VNx8HI.
	(SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
	(SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
	(sve_int_op, sve_int_op_rev): Handle the above codes.
	(sve_pred_int_rhs2_operand): Likewise.
	(MULLBT, SHRNB, SHRNT): Delete.
	(SVE_INT_SHIFT_IMM): New int iterator.
	(SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
	and UNSPEC_WHILEHS for TARGET_SVE2.
	(SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
	(SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
	(SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
	(SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
	(SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
	(SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
	(SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
	(SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
	(SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
	(SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
	(SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
	(SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
	(SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
	(SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
	(SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
	(SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
	(SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
	(optab): Handle the new unspecs.
	(su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
	and UNSPEC_RSHRNT.
	(lr): Handle the new unspecs.
	(bt): Delete.
	(cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
	(sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
	(sve_int_qsub_op): New int attributes.
	(sve_fp_op, rot): Handle the new unspecs.
	* config/aarch64/aarch64-sve-builtins.h
	(function_resolver::require_matching_pointer_type): Declare.
	(function_resolver::resolve_unary): Add an optional boolean argument.
	(function_resolver::finish_opt_n_resolution): Add an optional
	type_suffix_index argument.
	(gimple_folder::redirect_call): Declare.
	(gimple_expander::prepare_gather_address_operands): Add an optional
	bool parameter.
	* config/aarch64/aarch64-sve-builtins.cc: Include
	aarch64-sve-builtins-sve2.h.
	(TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
	(TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
	(TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
	(TYPES_hsd_integer): Use TYPES_hsd_signed.
	(TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
	(TYPES_s_unsigned): Likewise.
	(TYPES_s_integer): Use TYPES_s_unsigned.
	(TYPES_sd_signed, TYPES_sd_unsigned): New macros.
	(TYPES_sd_integer): Use them.
	(TYPES_d_unsigned): New macro.
	(TYPES_d_integer): Use it.
	(TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
	(TYPES_cvt_narrow): Likewise.
	(DEF_SVE_TYPES_ARRAY): Include the new types macros above.
	(preds_mx): New variable.
	(function_builder::add_overloaded_function): Allow the new feature
	set to be more restrictive than the original one.
	(function_resolver::infer_pointer_type): Remove qualifiers from
	the pointer type before printing it.
	(function_resolver::require_matching_pointer_type): New function.
	(function_resolver::resolve_sv_displacement): Handle functions
	that don't support 32-bit vector indices or svint32_t vector offsets.
	(function_resolver::finish_opt_n_resolution): Take the inferred type
	as a separate argument.
	(function_resolver::resolve_unary): Optionally treat all forms in
	the same way as normal merging functions.
	(gimple_folder::redirect_call): New function.
	(function_expander::prepare_gather_address_operands): Add an argument
	that says whether scaled forms are available.  If they aren't,
	handle scaling of vector indices and don't add the extension and
	scaling operands.
	(function_expander::map_to_unspecs): If aarch64_sve isn't available,
	fall back to using cond_* instead.
	* config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
	Split out the member variables into...
	(rtx_code_function_base): ...this new base class.
	(rtx_code_function_rotated): Inherit rtx_code_function_base.
	(unspec_based_function): Split out the member variables into...
	(unspec_based_function_base): ...this new base class.
	(unspec_based_function_rotated): Inherit unspec_based_function_base.
	(unspec_based_function_exact_insn): New class.
	(unspec_based_add_function, unspec_based_add_lane_function)
	(unspec_based_lane_function, unspec_based_pred_function)
	(unspec_based_qadd_function, unspec_based_qadd_lane_function)
	(unspec_based_qsub_function, unspec_based_qsub_lane_function)
	(unspec_based_sub_function, unspec_based_sub_lane_function): New
	typedefs.
	(unspec_based_fused_function): New class.
	(unspec_based_mla_function, unspec_based_mls_function): New typedefs.
	(unspec_based_fused_lane_function): New class.
	(unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
	typedefs.
	(CODE_FOR_MODE1): New macro.
	(fixed_insn_function): New class.
	(while_comparison): Likewise.
	* config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
	(binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
	(binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
	(load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
	(load_gather_sv_restricted, shift_left_imm_long): Declare.
	(shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
	(shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
	(shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
	(store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
	(ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
	(ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
	(unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
	(unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
	* config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
	Also add an initial argument for unary_convert_narrowt, regardless
	of the predication type.
	(build_32_64): Allow loads and stores to specify MODE_none.
	(build_sv_index64, build_sv_uint_offset): New functions.
	(long_type_suffix): New function.
	(binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
	(binary_imm_long_base, load_gather_sv_base): Likewise.
	(shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
	(ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
	(unary_narrowb_base, unary_narrowt_base): Likewise.
	(binary_long_lane_def, binary_long_lane): New shape.
	(binary_long_opt_n_def, binary_long_opt_n): Likewise.
	(binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
	(binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
	(binary_to_uint_def, binary_to_uint): Likewise.
	(binary_wide_def, binary_wide): Likewise.
	(binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
	(compare_def, compare): Likewise.
	(compare_ptr_def, compare_ptr): Likewise.
	(load_ext_gather_index_restricted_def,
	load_ext_gather_index_restricted): Likewise.
	(load_ext_gather_offset_restricted_def,
	load_ext_gather_offset_restricted): Likewise.
	(load_gather_sv_def): Inherit from load_gather_sv_base.
	(load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
	(shift_left_imm_def, shift_left_imm): Likewise.
	(shift_left_imm_long_def, shift_left_imm_long): Likewise.
	(shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
	(store_scatter_index_restricted_def,
	store_scatter_index_restricted): Likewise.
	(store_scatter_offset_restricted_def,
	store_scatter_offset_restricted): Likewise.
	(tbl_tuple_def, tbl_tuple): Likewise.
	(ternary_long_lane_def, ternary_long_lane): Likewise.
	(ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
	(ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
	(ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
	(ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
	(ternary_qq_rotate_def, ternary_qq_rotate): New shape.
	(ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
	(ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
	(ternary_uint_def, ternary_uint): Likewise.
	(unary_convert): Fix typo in comment.
	(unary_convert_narrowt_def, unary_convert_narrowt): New shape.
	(unary_long_def, unary_long): Likewise.
	(unary_narrowb_def, unary_narrowb): Likewise.
	(unary_narrowt_def, unary_narrowt): Likewise.
	(unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
	(unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
	(unary_to_int_def, unary_to_int): Likewise.
	* config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
	(unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
	(svasrd_impl): Delete.
	(svcadd_impl::expand): Handle integer operations too.
	(svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
	new functions to derive the unspec numbers.
	(svmla_svmls_lane_impl): Replace with...
	(svmla_lane_impl, svmls_lane_impl): ...these new classes.  Handle
	integer operations too.
	(svwhile_impl): Rename to...
	(svwhilelx_impl): ...this and inherit from while_comparison.
	(svasrd): Use unspec_based_function.
	(svmla_lane): Use svmla_lane_impl.
	(svmls_lane): Use svmls_lane_impl.
	(svrecpe, svrsqrte): Handle unsigned integer operations too.
	(svwhilele, svwhilelt): Use svwhilelx_impl.
	* config/aarch64/aarch64-sve-builtins-sve2.h: New file.
	* config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
	* config/aarch64/aarch64-sve-builtins.def: Include
	aarch64-sve-builtins-sve2.def.

gcc/testsuite/
	* g++.target/aarch64/sve/acle/general-c++/mul_lane_1.c: New test.
	* g++.target/aarch64/sve2/acle: New directory.
	* gcc.target/aarch64/pragma_cpp_predefs_3.c: New test.
	* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_TYPE_CHANGE_Z)
	(TEST_DUAL_ZD, TEST_TYPE_CHANGE_ZX, TEST_TBL2, TEST_TBL2_REV): New
	macros.
	* gcc.target/aarch64/sve/acle/general-c/binary_lane_1.c: Do not
	expect an error saying that the function has no f32 form, but instead
	expect an error about SVE2 being required if the current target
	doesn't support SVE2.
	* gcc.target/aarch64/sve/acle/general-c/ternary_lane_1.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_lane_rotate_1.c Likewise.
	* gcc.target/aarch64/sve/acle/general-c/binary_long_lane_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_long_opt_n_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_narrowb_opt_n_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_narrowt_opt_n_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_wide_1.c,
	* gcc.target/aarch64/sve/acle/general-c/binary_wide_opt_n_1.c,
	* gcc.target/aarch64/sve/acle/general-c/compare_1.c,
	* gcc.target/aarch64/sve/acle/general-c/compare_ptr_1.c,
	* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_index_restricted_1.c,
	* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_1.c,
	* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_2.c,
	* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_3.c,
	* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_4.c,
	* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_1.c,
	* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_2.c,
	* gcc.target/aarch64/sve/acle/general-c/mul_lane_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_long_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_2.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_1.c,
	* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/store_scatter_index_restricted_1.c,
	* gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_restricted_1.c,
	* gcc.target/aarch64/sve/acle/general-c/tbl_tuple_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_long_lane_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_long_opt_n_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_qq_lane_rotate_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_qq_rotate_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_shift_right_imm_1.c,
	* gcc.target/aarch64/sve/acle/general-c/ternary_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_convert_narrowt_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_narrowb_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_narrowb_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_narrowt_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_narrowt_to_uint_1.c,
	* gcc.target/aarch64/sve/acle/general-c/unary_to_int_1.c: New tests.
	* gcc.target/aarch64/sve2/bcax_1.c: Likewise.
	* gcc.target/aarch64/sve2/acle: New directory.

From-SVN: r280060
2020-01-09 16:36:42 +00:00
Richard Sandiford
f3582fda78 [AArch64] Pass a mode to some SVE immediate queries
It helps the SVE2 ACLE support if aarch64_sve_arith_immediate_p and
aarch64_sve_sqadd_sqsub_immediate_p accept scalars as well as vectors.

2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
	(aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
	* config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
	(aarch64_sve_sqadd_sqsub_immediate_p): Likewise.  Handle scalar
	immediates as well as vector ones.
	* config/aarch64/predicates.md (aarch64_sve_arith_immediate)
	(aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
	(aarch64_sve_qsub_immediate): Update calls accordingly.

From-SVN: r280059
2020-01-09 16:26:47 +00:00
Richard Sandiford
df0f21028e [AArch64] Add banner comments to aarch64-sve2.md
This patch imposes the same sort of structure on aarch64-sve2.md
as we already have for aarch64-sve.md, before it grows a lot more
patterns.

2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve2.md: Add banner comments.
	(<su>mulh<r>s<mode>3): Move further up file.
	(<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
	(*aarch64_sve2_sra<mode>): Move further down file.
	* config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.

From-SVN: r280058
2020-01-09 16:24:15 +00:00