This rejects variables that are array types, array elements or derived type
members when used as the event handle inside a detach clause (in accordance
with the OpenMP specification). This would previously lead to an ICE.
2022-03-03 Kwok Cheung Yeung <kcy@codesourcery.com>
gcc/fortran/
PR fortran/104131
* openmp.cc (gfc_match_omp_detach): Move check for type of event
handle to...
(resolve_omp_clauses) ...here. Also check that the event handle is
not an array, or an array access or structure element access.
gcc/testsuite/
PR fortran/104131
* gfortran.dg/gomp/pr104131.f90: New.
* gfortran.dg/gomp/task-detach-1.f90: Update expected error message.
In gcc-5 to gcc-11, the ptx isa version was 3.1.
On trunk, the default is now 6.0, which is also what will be the value in
the libraries.
Consequently, there may be setups with an older driver that worked with
gcc-11, but will become unsupported with gcc-12.
Fix this by building the libraries with mptx=3.1.
After this, setups with an older driver still won't work out of the box
with gcc-12, because the default ptx isa version has changed, but should work
after specifying mptx=3.1.
gcc/ChangeLog:
2022-03-03 Tom de Vries <tdevries@suse.de>
* config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Add mptx=3.1.
In gcc-11, when specifying -misa=sm_30, an executable may still contain sm_35
code (due to libraries being built with the default -misa=sm_35), so it won't
run on an sm_30 board.
Fix this by building libraries with sm_30, as was the case in gcc-5 to gcc-10.
gcc/ChangeLog:
2022-03-03 Tom de Vries <tdevries@suse.de>
PR target/104758
* config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Add misa=sm_30.
In PR97348, we ran into the problem that recent CUDA dropped support for
sm_30, which inhibited the build when building with CUDA bin in the path,
because the nvptx-tools assembler uses CUDA's ptxas to do ptx verification.
To fix this, in gcc-11 the default sm_xx was moved from sm_30 to sm_35.
This however broke support for sm_30 boards: an executable build for sm_30
might contain sm_35 code from the libraries, which are build with the default
sm_xx (PR104758).
We want to fix this by going back to having the libraries build with sm_30, as
was the case for gcc-5 to gcc-10. That however reintroduces the problem from
PR97348.
Deal with PR97348 in the simplest way possible: when calling the assembler for
sm_30, specify --no-verify.
This has the unfortunate effect that after fixing PR104758 by building
libraries with sm_30, the libraries are no longer verified. This can be
improved upon by:
- adding a configure test in gcc that tests if CUDA supports sm_30, and
if so disabling this patch
- dealing with this in nvptx-tools somehow, either:
- detect at ptxas execution time that it doesn't support sm_30, or
- detect this at nvptx-tool configure time.
gcc/ChangeLog:
2022-03-03 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx.h (ASM_SPEC): Add %{misa=sm_30:--no-verify}.
With target board nvptx-none-run/-mptx=3.1 we run into:
...
cc1: error: PTX version (-mptx) needs to be at least 4.2 to support \
selected -misa (sm_53)^M
compiler exited with status 1
FAIL: gcc.target/nvptx/sm53.c (test for excess errors)
...
Fix this by adding -mptx=_ in sm53.c and similar.
Tested on nvptx.
gcc/testsuite/ChangeLog:
2022-03-03 Tom de Vries <tdevries@suse.de>
* gcc.target/nvptx/sm53.c: Add -mptx=_.
* gcc.target/nvptx/sm70.c: Same.
* gcc.target/nvptx/sm75.c: Same.
* gcc.target/nvptx/sm80.c: Same.
When offloading to nvptx is enabled, scan_omp_simd duplicates the simd
region including its clauses and body using inliner's
copy_gimple_seq_and_replace_locals. That works nicely for decls, remaps
only those that are seen in the nested bind expr vars (i.e. local variables)
and doesn't remap other vars. But for SSA_NAMEs it remaps them always, doesn't
know if their def stmt is outside of the simd (then it better shouldn't be remapped)
or inside of it (then it should) and without cfg/dominators that is pretty hard
to figure out (well, we could walk the region twice, once note SSA_NAMEs defined
by each stmt seen there and once do the remapping of only those visited SSA_NAMEs).
This patch uses a simpler way, disables temporarily into_ssa for the clauses and
body of each simd region; we already disable into_ssa e.g. in parallel/target/task
etc. regions through push_gimplify_context () but for simd we don't push
any gimplification context and appart from into_ssa I think we don't need it.
2022-03-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/104757
* gimplify.cc (gimplify_omp_loop): Call gimplify_expr rather than
gimplify_omp_for.
(gimplify_expr) <case OMP_SIMD>: Temporarily disable
gimplify_ctxp->into_ssa around call to gimplify_omp_for.
* gfortran.dg/gomp/pr104757.f90: New test.
* gcc.dg/gomp/pr104757.c: New test.
The following testcase ICEs on x86_64 when asked to use the pre-GCC 8
ABI where zero sized arguments weren't ignored.
In GCC 7 the emit_push_insn calls in store_one_arg were unconditional,
it is true that they didn't actually push anything because it had zero
size, but because arg->locate.alignment_pad is 8 in this case,
emit_push_insn at the end performs
if (alignment_pad && args_addr == 0)
anti_adjust_stack (alignment_pad);
and an assert larger on is upset if we don't do it.
The following patch keeps the emit_push_insn conditional but calls
the anti_adjust_stack when needed by hand for the zero sized arguments.
For the new x86_64 ABI where zero sized arguments are ignored
arg->locate.alignment_pad is 0 in this case, so nothing changes
- we in that case really do ignore it.
There is another emit_push_insn call earlier in store_one_arg, also made
conditional on non-zero size by Marek in GCC 8, but that one is for
arguments with non-BLKmode and the only way those can be zero size is
if they are TYPE_EMPTY_P aka when they are completely ignored. But
I believe arg->locate.alignment_pad should be 0 in that case, so IMHO
there is no need to do anything in the second spot.
2022-03-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/104558
* calls.cc (store_one_arg): When not calling emit_push_insn
because size_rtx is const0_rtx, call at least anti_adjust_stack
on arg->locate.alignment_pad if !argblock and the alignment might
be non-zero.
* gcc.dg/pr104558.c: New test.
gcc/fortran/ChangeLog:
PR fortran/104573
* resolve.cc (resolve_structure_cons): Avoid NULL pointer
dereference when there is no valid component.
gcc/testsuite/ChangeLog:
PR fortran/104573
* gfortran.dg/assumed_type_14.f90: New test.
The testcase references a vector type that elicits a psabi warning.
This patch adds the option to suppress the warning.
* c-c++-common/pr104505.c: Add -Wno-psabi.
Unlike e.g. remove_inheritance_pseudos, undo_optional_reloads didn't
deal with subregs, so instead of removing multi-word moves, it
replaced the reload pseudo with the original pseudo. Besides the
redundant move, that retained the clobber of the dest, that starts a
multi-word move. After the remap, the sequence that should have
become a no-op move starts by clobbering the original pseudo and then
moving its pieces onto themselves. The problem is the clobber: it
makes earlier sets of the original pseudo to be regarded as dead: if
the optional reload sequence was an output reload, the insn for which
the output reload was attempted may be regarded as dead and deleted.
I've arranged for undo_optional_reloads to accept SUBREGs and use
get_regno, like remove_inheritance_pseudo, adjusted its insn-removal
loop to tolerate iterating over a removed clobber, and added logic to
catch any left-over reload clobbers that could trigger the problem.
for gcc/ChangeLog
* lra-constraints.cc (undo_optional_reloads): Recognize and
drop insns of multi-word move sequences, tolerate removal
iteration on an already-removed clobber, and refuse to
substitute original pseudos into clobbers.
At the same time, adding -Wtrivial-auto-var-init and update documentation.
-Wtrivial-auto-var-init and update documentation.
for the following testing case:
1 int g(int *);
2 int f1()
3 {
4 switch (0) {
5 int x;
6 default:
7 return g(&x);
8 }
9 }
compiling with -O -ftrivial-auto-var-init causes spurious warning:
warning: statement will never be executed [-Wswitch-unreachable]
5 | int x;
| ^
This is due to the compiler-generated initialization at the point of
the declaration.
We could avoid the warning to exclude the following cases:
when
flag_auto_var_init > AUTO_INIT_UNINITIALIZED
And
1) call to .DEFERRED_INIT
2) call to __builtin_clear_padding if the 2nd argument is present and non-zero
3) a gimple assign store right after the .DEFERRED_INIT call that has the LHS
as RHS
However, we still need to warn users about the incapability of the option
-ftrivial-auto-var-init by adding a new warning option -Wtrivial-auto-var-init
to report cases when it cannot initialize the auto variable. At the same
time, update documentation for -ftrivial-auto-var-init to connect it with
the new warning option -Wtrivial-auto-var-init, and add documentation
for -Wtrivial-auto-var-init.
gcc/ChangeLog:
PR middle-end/102276
* common.opt (-Wtrivial-auto-var-init): New option.
* doc/invoke.texi (-Wtrivial-auto-var-init): Document new option.
(-ftrivial-auto-var-init): Update option;
* gimplify.cc (emit_warn_switch_unreachable): New function.
(warn_switch_unreachable_r): Rename to ...
(warn_switch_unreachable_and_auto_init_r): This.
(maybe_warn_switch_unreachable): Rename to ...
(maybe_warn_switch_unreachable_and_auto_init): This.
(gimplify_switch_expr): Update calls to renamed function.
gcc/testsuite/ChangeLog:
PR middle-end/102276
* gcc.dg/auto-init-pr102276-1.c: New test.
* gcc.dg/auto-init-pr102276-2.c: New test.
* gcc.dg/auto-init-pr102276-3.c: New test.
* gcc.dg/auto-init-pr102276-4.c: New test.
In this PR allocnos_conflict_p takes 90% of the compile-time via
the calls from update_conflict_hard_regno_costs. This is due to
the high number of conflicts recorded in the dense bitvector
representation. Fortunately we can take advantage of the bitvector
representation here and turn the O(n) conflict test into an O(1) one,
greatly speeding up the compile of the testcase from 39s to just 4s
(93% IRA time to 26% IRA time).
While for the testcase in question the first allocno is almost always
the nice one the patch tries a more systematic approach to finding
the allocno to iterate object conflicts over. That does reduce
the actual number of compares for the testcase but it doesn't make
a measurable difference wall-clock wise. That's not guaranteed
though I think so I've kept this systematic way of choosing the
cheapest allocno.
2022-03-02 Richard Biener <rguenther@suse.de>
PR rtl-optimization/104686
* ira-color.cc (object_conflicts_with_allocno_p): New function
using a bitvector test instead of iterating when possible.
(allocnos_conflict_p): Choose the best allocno to iterate over
object conflicts.
(update_conflict_hard_regno_costs): Do allocnos_conflict_p test
last.
This testcase FAILs everywhere for 3 reasons:
1) the testcase can't work on ia32, where sizeof (long double) == 12
and as it is not a power of 2, we disallow creating vectors with such
elements, -mx32 and -m64 are fine
2) the testcase emits a lot of -Wdiv-by-zero warnings, I've just added
-Wno-div-by-zero to dg-options
3) my fault, when tweaking the testcase I've missed 33 initializers of
a 32 element vector which didn't change anything on the ICE, but is
still reported
This patch fixes all of it, tested with
RUNTESTFLAGS='--target_board=unix\{-m32,-m64\} i386.exp=pr104637.c'
both without the LRA fix where it ICEs and with it where it passes
everywhere.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/104637
* gcc.target/i386/pr104637.c: Don't run on ia32. Add -Wno-div-by-zero
to dg-options.
(foo): Remove extraneous initializer.
When debugging the PR104589 issue, I've run into a problem that
goto_locus doesn't show up in the logs, so it wasn't clear if
the bug hasn't been introduced far earlier just by divergence
in goto_locus of some edge.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
* cfg.cc (dump_edge_info): Dump goto_locus if present.
This is similar to PR104237 and similarly to that, no testcase included
for the testsuite, as we don't have a framework to compile/link with
-g -flto and -g0 -flto and compare -fdump-final-insns= results from
the lto1 compilations.
With -flto, whether two location_t compare equal or not and just
express the same location is a lottery.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/104589
* cfgrtl.cc (fixup_reorder_chain): Use loc_equal instead of direct
INSN_LOCATION comparison with goto_locus.
These testcases started failing with r12-630 and one of them
got fixed with r12-4531 (aka PR102764 fix and r12-4616 further
improved the fix) and the other went latent in r12-2591 (i.e. threader
changes) and I believe was fixed for real by the PR102764 fix too.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR debug/100541
* g++.dg/opt/pr100541-1.C: New test.
* g++.dg/opt/pr100541-2.C: New test.
This fixes some comment spelling bugs in tree-ssa-strlen.cc.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
* tree-ssa-strlen.cc (strlen_pass::handle_assign,
strlen_pass::before_dom_children): Comment spelling fixes.
Use avx2-check mechanism to avoid illegal instrucion on non-avx2 target.
gcc/testsuite/ChangeLog:
PR target/104726
* gcc.target/i386/pr104551.c: Use avx2-check.h.
Use standard C type instead of __int64_t which doesn't work on Solaris.
gcc/testsuite/ChangeLog:
PR target/104724
* gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c: Use long long
instead of __int64_t.
* gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c: Ditto.
Related to:
PR tree-optimization/104715 - false dangling pointer with strstr
gcc/testsuite/ChangeLog:
PR tree-optimization/104715
* gcc.dg/Wdangling-pointer-3.c: New test.
The following testcase emits bogus -Wdangling-pointer warnings.
The bug is that when it sees that ptr immediate use is a call that
returns one of its arguments, it will assume that the return value
is based on ptr, but that is the case only if ptr is passed to the
argument that is actually returned (so e.g. for memcpy the first argument,
etc.). When the builtins guarantee e.g. that the result is based on the
first argument (either ERF_RETURNS_ARG 0 in which case it will always
just returns the first argument as is, or when it is something like
strstr or strpbrk or mempcpy that it returns some pointer based on the
first argument), it means the result is not based on second or following
argument if any. The second hunk fixes this.
The first hunk just removes an unnecessary TREE_CODE check, the code only
pushes SSA_NAMEs into the pointers vector and if it didn't, it uses
FOR_EACH_IMM_USE_FAST (use_p, iter, ptr)
a few lines below this, which of course requires that ptr is a SSA_NAME.
Tree checking on SSA_NAME_VERSION will already ensure that if it wasn't
a SSA_NAME, we'd ICE.
2022-03-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/104715
* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses): Don't
unnecessarily test if ptr is a SSA_NAME, it has to be. Only push lhs
of a call if gimple_call_return_arg is equal to ptr, not just when it
is non-NULL.
* c-c++-common/Wdangling-pointer-7.c: New test.
I've noticed various spelling bugs in comments in this file.
There is one spot I haven't fixed:
"Otherwise, VAR is the auto variable
(including an unnamed temporary such as a compound literal) whose
lifetime's rended it dangling."
I'm afraid I don't know what it wanted to say, "lifetime rendered it"
or something else?
2022-03-01 Jakub Jelinek <jakub@redhat.com>
* gimple-ssa-warn-access.cc (warn_string_no_nul,
maybe_warn_nonstring_arg, fndecl_alloc_p, new_delete_mismatch_p,
matching_alloc_calls_p, maybe_warn_alloc_args_overflow,
pass_waccess::check_alloca, pass_waccess::check_strcat,
memmodel_to_uhwi, fntype_argno_type,
pass_waccess::maybe_check_access_sizes,
pass_waccess::check_call_access,
pass_waccess::maybe_check_dealloc_call, pass_waccess::check_stmt):
Comment spelling fixes.
Limit PR 35513 tests to Linux since they fail on 32-bit Solaris/x86 with
Solaris linker.
PR testsuite/104725
* g++.target/i386/pr35513-1.C: Limit to Linux.
* g++.target/i386/pr35513-2.C: Likewise.
lto-plugin/ChangeLog:
* lto-plugin.c (process_offload_section): Use a linker as many
comments are connected to gold linker.
(process_option): Likewise.
This fixes a false positive warning seen with LTO:
12/bits/regex_compiler.tcc:443:32: error: '__last_char._M_char' may be used uninitialized [-Werror=maybe-uninitialized]
Given that the std::regex code is not very efficient anyway, the
overhead of initializing this byte should be minimal.
libstdc++-v3/ChangeLog:
PR middle-end/103984
* include/bits/regex_compiler.h (_BracketMatcher::_M_char): Use
default member initializer.
The following checks whether we can copy the loop before attempting
to do so in loop distribution. In the testcase there's a computed
goto and thus abnormal edges which we cannot redirect.
2022-03-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/104716
* tree-loop-distribution.cc (find_seed_stmts_for_distribution):
Check if we can copy the loop.
* gfortran.dg/pr104716.f: New testcase.
We need to be able to reverse a vector for negative strides.
2022-03-01 Richard Biener <rguenther@suse.de>
PR testsuite/104728
* gcc.dg/vect/pr81196-2.c: Require vect_perm.
commit a5883ba0de
Author: Michael Matz <matz@gcc.gnu.org>
Date: Tue Nov 24 15:37:32 2009 +0000
introduced currently_expanding_gimple_stmt, which was set and cleared in
expand_gimple_basic_block when expanding gimple statement to RTL. But it
isn't cleared when expand_gimple_basic_block returns inside the loop.
PR middle-end/104721
* cfgexpand.cc (expand_gimple_basic_block): Clear
currently_expanding_gimple_stmt when returning inside the loop.
Committed as obvious (in hindsight).
2022-03-01 Roger Sayle <roger@nextmovesoftware.com>
gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: Don't compile new test case on ia32.
For a test-case doing an openmp target simd reduction on a complex double:
...
DOUBLE COMPLEX :: counter_N0
...
!$OMP TARGET SIMD reduction(+: counter_N0)
...
we run into:
...
during RTL pass: expand
b.f90: In function ‘MAIN__._omp_fn.0’:
b.f90:23:32: internal compiler error: in expand_insn, at optabs.cc:8029
23 | counter_N0 = counter_N0 + 1.
| ^
0x10f1cd3 expand_insn(insn_code, unsigned int, expand_operand*)
gcc/optabs.cc:8029
0xeac435 expand_GOMP_SIMT_XCHG_BFLY
gcc/internal-fn.cc:375
...
Fix this by handling DCmode and CDImode in define_expand
"omp_simt_xchg_{bfly,idx}".
Tested on x86_64 with nvptx accelerator.
gcc/ChangeLog:
2022-02-28 Tom de Vries <tdevries@suse.de>
PR target/102429
* config/nvptx/nvptx.cc (nvptx_gen_shuffle): Handle DCmode and CDImode.
* config/nvptx/nvptx.md
(define_predicate "nvptx_register_or_complex_di_df_register_operand"):
New predicate.
(define_expand "omp_simt_xchg_bfly", define_expand "omp_simt_xchg_idx"):
Use nvptx_register_or_complex_di_df_register_operand.
Use nvptx-sm.def to generate new files nvptx-gen.h and nvptx-gen.opt, and:
- include nvptx-gen.h in nvptx.h, and
- add nvptx-gen.opt to extra_options (before nvptx.opt, in case that matters).
Tested on nvptx.
gcc/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* config.gcc (nvptx*-*-*): Add nvptx/nvptx-gen.opt to extra_options.
* config/nvptx/gen-copyright.sh: New file.
* config/nvptx/gen-h.sh: New file.
* config/nvptx/gen-opt.sh: New file.
* config/nvptx/nvptx.h (TARGET_SM35, TARGET_SM53, TARGET_SM70)
(TARGET_SM75, TARGET_SM80): Move ...
* config/nvptx/nvptx-gen.h: ... here. New file, generate.
* config/nvptx/nvptx.opt (Enum ptx_isa): Move ...
* config/nvptx/nvptx-gen.opt: ... here. New file, generate.
* config/nvptx/t-nvptx ($(srcdir)/config/nvptx/nvptx-gen.h)
($(srcdir)/config/nvptx/nvptx-gen.opt): New make target.
Add a script gen-omp-device-properties.sh that uses nvptx-sm.def to generate
omp-device-properties-nvptx.
Tested on x86_64 with nvptx accelerator.
gcc/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* config/nvptx/gen-omp-device-properties.sh: New file.
* config/nvptx/t-omp-device: Use gen-omp-device-properties.sh.
Add a file gcc/config/nvptx/nvptx-sm.def that lists all sm_xx versions used in
the port, like so:
...
NVPTX_SM(30, NVPTX_SM_SEP)
NVPTX_SM(35, NVPTX_SM_SEP)
NVPTX_SM(53, NVPTX_SM_SEP)
NVPTX_SM(70, NVPTX_SM_SEP)
NVPTX_SM(75, NVPTX_SM_SEP)
NVPTX_SM(80,)
...
and use it in various places using a pattern:
...
#define NVPTX_SM(XX, SEP) { ... }
#include "nvptx-sm.def"
#undef NVPTX_SM
...
Tested on nvptx.
gcc/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx-sm.def: New file.
* config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Use nvptx-sm.def.
* config/nvptx/nvptx-opts.h (enum ptx_isa): Same.
* config/nvptx/nvptx.cc (sm_version_to_string)
(nvptx_omp_device_kind_arch_isa): Same.
Add a few test-cases that test passing each -misa=sm_xx version and verify that
the proper __PTX_SM__ is defined.
Tested on nvptx.
gcc/testsuite/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* gcc.target/nvptx/sm30.c: New test.
* gcc.target/nvptx/sm35.c: New test.
* gcc.target/nvptx/sm53.c: New test.
* gcc.target/nvptx/sm70.c: New test.
* gcc.target/nvptx/sm75.c: New test.
* gcc.target/nvptx/sm80.c: New test.
ifcvt now passes a CC-mode "comparison" to backends. This patch
simply returns from gen_compare_reg () in that case since nothing
needs to be prepared anymore.
gcc/ChangeLog:
PR rtl-optimization/104154
* config/arc/arc.cc (gen_compare_reg): Return the CC-mode
comparison ifcvt passed us.
For V8HFmode vector init with HFmode, do not directly emits V8HF move
with subreg, which may cause reload to assign general register to move
src.
gcc/ChangeLog:
PR target/104664
* config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
Use vec_setv8hf_0 for HF to V8HFmode move instead of subreg.
gcc/testsuite/ChangeLog:
PR target/104664
* gcc.target/i386/pr104664.c: New test.
This patch is my proposed solution to PR tree-optimization/91384 which is
a missed-optimization/code quality regression on x86_64. The problematic
idiom is "if (r = -a)" which is equivalent to both "r = -a; if (r != 0)"
and alternatively "r = -a; if (a != 0)". In this particular case, on
x86_64, we prefer to use the condition codes from the negation, rather
than require an explicit testl instruction.
Unfortunately, combine can't help, as it doesn't attempt to merge pairs
of instructions that share the same operand(s), only pairs/triples of
instructions where the result of each instruction feeds the next. But
I doubt there's sufficient benefit to attempt this kind of "combination"
(that wouldn't already be caught by the tree-ssa passes).
Fortunately, it's relatively easy to fix this up (addressing the
regression) during peephole2 to eliminate the unnecessary testl in:
movl %edi, %ebx
negl %ebx
testl %edi, %edi
je .L2
2022-02-28 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR tree-optimization/91384
* config/i386/i386.md (peephole2): Eliminate final testl insn
from the sequence *movsi_internal, *negsi_1, *cmpsi_ccno_1 by
transforming using *negsi_2 for the negation.
gcc/testsuite/ChangeLog
PR tree-optimization/91384
* gcc.target/i386/pr91384.c: New test case.
This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
performing a bitfield extraction on a variable explicitly stored in a
hard register by the user causes a segmentation fault during RTL
expansion. Nearly identical source code without the "asm" qualifier
compiles fine. The point of divergence is in simplify_gen_subreg
which tries to avoid creating non-trivial SUBREGs of hard registers,
to avoid problems during register allocation. This suggests the
simple solution proposed here, to copy hard registers to a new pseudo
in extract_integral_bit_field, just before calling simplify_gen_subreg.
2022-02-28 Roger Sayle <roger@nextmovesoftware.com>
Eric Botcazou <ebotcazou@adacore.com>
gcc/ChangeLog
PR middle-end/80270
* expmed.cc (extract_integral_bit_field): If OP0 is a hard
register, copy it to a pseudo before calling simplify_gen_subreg.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: New test case.
LRA hard reg split subpass is a small subpass used as the last
resort for LRA when it can not assign a hard reg to a reload
pseudo by other ways (e.g. by spilling non-reload pseudos). For
simplicity the subpass works on one split base (as each split
changes pseudo live range info). In this case it results in
reaching maximal possible number of subpasses. The patch
implements as many non-overlapping hard reg splits
splits as possible on each subpass.
gcc/ChangeLog:
PR rtl-optimization/104637
* lra-assigns.cc (lra_split_hard_reg_for): Split hard regs as many
as possible on one subpass.
gcc/testsuite/ChangeLog:
PR rtl-optimization/104637
* gcc.target/i386/pr104637.c: New.
