PR middle-end/58564
* fold-const.c (fold_ternary_loc): For A < 0 : <sign bit of A> : 0
optimization, punt if sign_bit_p looked through any zero extension.
* gcc.c-torture/execute/pr58564.c: New test.
From-SVN: r203042
* tree-ssa-threadupdate.c (ssa_fix_duplicate_block_edges):
Update redirected out edge count in joiner case.
(ssa_redirect_edges): Common the joiner and non-joiner cases
so that joiner case gets profile updates.
* testsuite/gcc.dg/tree-ssa/ssa-dom-thread-3.c (expand_one_var):
Update for additional dump message.
From-SVN: r203041
* go-gcc.cc (Backend::error_expression): New function.
(Backend::var_expression): New function.
(Backend::indirect_expression): New function.
From-SVN: r203038
* config/msp430/msp430.c (msp430x_names): New array. Lists MCUs
that use the MSP430X ISA.
(msp430_option_override): Scan -mmcu command line option for any
MCU name that supports the MSP430X ISA.
* config/msp430/t-msp430 (MULTILIB_MATCHES): Add matches for known
-mmcu options which enable the MSP430X ISA.
From-SVN: r203026
* x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Enable for generic.
(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Likewise.
(X86_TUNE_FOUR_JUMP_LIMIT): Drop for generic and buldozer.
(X86_TUNE_PAD_RETURNS): Drop for buldozer chips.
(X86_TUNE_AVOID_VECTOR_DECODE): Drop for generic.
(X86_TUNE_REASSOC_FP_TO_PARALLEL): Enable for generic.
From-SVN: r203012
2013-09-28 Tim Shen <timshen91@gmail.com>
* include/bits/regex_scanner.tcc (_Scanner<>::_M_eat_escape_posix):
Let ordinary char escaping in POSIX be valid.
* testsuite/28_regex/basic_regex/ctors/basic/raw_string.cc: Test this
change.
From-SVN: r203005
[gcc]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
DFmode, DImode, and SFmode in the upper VSX registers based on the
-mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
if -mpower8-vector. Combine -mvsx-timode handling with the rest
of the VSX register handling.
* config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
(f32_sv): Likewise.
(zero_extendsidi2_lfiwzx): Add support for loading into the
Altivec registers with -mpower8-vector. Use wu/wv constraints to
only do VSX memory options on Altivec registers.
(extendsidi2_lfiwax): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat, SF/SD modes): Likewise.
(mov<mode>_hardfloat32, DF/DD modes): Likewise.
(mov<mode>_hardfloat64, DF/DD modes): Likewise.
(movdi_internal64): Likewise.
[gcc/testsuite]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
and -mupper-regs-df.
From-SVN: r202984
PR middle-end/58551
* tree-cfg.c (move_sese_region_to_fn): Also move loops that
are children of outermost saved_cfun's loop, and set it up to
be moved to dest_cfun's outermost loop. Fix up num_nodes adjustments
if loop != loop0 and SESE region contains bbs that belong to loop0.
* c-c++-common/gomp/pr58551.c: New test.
From-SVN: r202972
gcc/
* rtlanal.c (must_be_base_p, must_be_index_p): Delete.
(binary_scale_code_p, get_base_term, get_index_term): New functions.
(set_address_segment, set_address_base, set_address_index)
(set_address_disp): Accept the argument unconditionally.
(baseness): Remove must_be_base_p and must_be_index_p checks.
(decompose_normal_address): Classify as much as possible in the
main loop.
From-SVN: r202970
