2016-08-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/69047
* tree-ssa.c (maybe_rewrite_mem_ref_base): Handle general bitfield
extracts similar to what FRE does.
(non_rewritable_mem_ref_base): Likewise.
* gcc.dg/pr69047.c: New testcase.
From-SVN: r239778
2016-08-26 Jonathan Wakely <jwakely@redhat.com>
Pedro Alves <palves@redhat.com>
* testsuite/lib/gdb-test.exp (gdb-dg-runtest): Define wrapper to save
and restore dg-interpreter-batch-mode.
* testsuite/libstdc++-prettyprinters/prettyprinters.exp: Use
gdb-dg-runtest instead of dg-runtest.
* testsuite/libstdc++-xmethods/xmethods.exp: Likewise.
Co-Authored-By: Pedro Alves <palves@redhat.com>
From-SVN: r239776
In <https://gcc.gnu.org/ml/gcc-bugs/2016-08/msg03233.html>, Nick
reported i386-elf and ia64-elf failing to build because of
float128_type_node being NULL, but being used by the back end for
__float128.
The global float128_type_node is only available conditionally, if
target hooks indicate TFmode is not only available as a scalar mode
and of the right format, but also supported in libgcc. The back-end
support, however, expects the type always to be available for
__float128 even if the libgcc support is missing.
Although a target-specific node could be restored in the case where
libgcc support is missing, it seems better to address the missing
libgcc support. Thus, this patch enables TFmode soft-fp in libgcc
globally for all x86 targets - the only special cases needed being for
targets that use soft-fp for SFmode and DFmode, one of which already
had the support for TFmode as well (so I based the i[34567]86-*-rtems*
configuration on that present for i[34567]86-*-elfiamcu). The i386
implementation of TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P is then
removed as no longer needed.
I can provide such a patch for ia64 if useful, but am not in a
position to test it (and while I'm reasonably confident that enabling
this support would be right for ia64-elf and ia64-freebsd, I've no
real idea if enabling libgcc support for TFmode, with or without also
enabling it for XFmode, would be safe for ia64-vms).
Bootstrapped with no regressions on x86_64-pc-linux-gnu.
gcc:
* config/i386/i386.c (ix86_libgcc_floating_mode_supported_p)
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Remove.
* config/i386/i386elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
* config/i386/lynx.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
* config/i386/netbsd-elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE):
Likewise.
* config/i386/netbsd64.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
* config/i386/nto.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
* config/i386/openbsd.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
* config/i386/rtemself.h (IX86_NO_LIBGCC_TFMODE): Likewise.
* config/i386/vxworks.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Likewise.
libgcc:
* config.host (i[34567]86-*-* | x86_64-*-*): Enable TFmode soft-fp
where not already enabled.
From-SVN: r239775
2016-08-26 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
Martin Jambhor <mjambor@suse.cz>
* common.opt: New option -fipa-bit-cp.
* doc/invoke.texi: Document -fipa-bit-cp.
* opts.c (default_options_table): Add entry for -fipa-bit-cp.
(enable_fdo_optimizations): Check for flag_ipa_bit_cp.
* tree-ssa-ccp.h: New header file.
* tree-ssa-ccp.c: Include tree-ssa-ccp.h
(bit_value_binop_1): Change to bit_value_binop_1 and export it.
Replace all occurences of tree parameter by two new params: signop, int.
(bit_value_unop_1): Change to bit_value_unop and export it.
Replace all occurences of tree parameter by two new params: signop,
int.
(bit_value_binop): Change call from bit_value_binop_1 to
bit_value_binop.
(bit_value_assume_aligned): Likewise.
(bit_value_unop): Change call from bit_value_unop_1 to bit_value_unop.
(do_ssa_ccp): Pass nonzero_p || flag_ipa_cp_bit instead of nonzero_p
to ccp_finalize.
(ccp_finalize): Skip processing if val->mask == 0.
* ipa-cp.c: Include tree-ssa-ccp.h
(ipcp_bits_lattice): New class.
(ipcp_param_lattice (bits_lattice): New member.
(print_all_lattices): Call ipcp_bits_lattice::print.
(set_all_contains_variable): Call ipcp_bits_lattice::set_to_bottom.
(initialize_node_lattices): Likewise.
(propagate_bits_accross_jump_function): New function.
(propagate_constants_accross_call): Call
propagate_bits_accross_jump_function.
(ipcp_propagate_stage): Store parameter types when in_lto_p is true.
(ipcp_store_bits_results): New function.
(ipcp_driver): Call ipcp_store_bits_results.
* ipa-prop.h (ipa_bits): New struct.
(ipa_jump_func): Add new member bits of type ipa_bits.
(ipa_param_descriptor): Change decl to decl_or_type.
(ipa_get_param): Change decl to decl_or_type and assert on
PARM_DECL.
(ipa_get_type): New function.
(ipcp_transformation_summary): New member bits.
* ipa-prop.c (ipa_get_param_decl_index_1): s/decl/decl_or_type.
(ipa_populate_param_decls): Likewise.
(ipa_dump_param): Likewise.
(ipa_print_node_jump_functions_for_edge): Pretty-print ipa_bits jump
function.
(ipa_set_jf_unknown): Set ipa_bits::known to false.
(ipa_compute_jump_functions_for_edge): Compute jump function for bits
propagation.
(ipa_node_params_t::duplicate): Copy src->bits into dst->bits.
(ipa_write_jump_function): Add streaming for ipa_bits.
(ipa_read_jump_function): Add support for reading streamed ipa_bits.
(write_ipcp_transformation_info): Add streaming for ipa_bits
summary for ltrans.
(read_ipcp_transfomration_info): Add support for reading streamed ipa_bits.
(ipcp_update_bits): New function.
(ipcp_transform_function): Call ipcp_update_bits.
testsuite/
* gcc.dg/ipa/propbits-1.c: New test-case.
* gcc.dg/ipa/propbits-2.c: Likewise.
* gcc.dg/ipa/propbits-3.c: Likewise.
Co-Authored-By: Martin Jambor <mjambor@suse.cz>
From-SVN: r239769
2016-08-25 Steven g. Kargl <kargl@gcc.gnu.org>
PR fortran/77351
* frontend-passes.c (remove_trim,combine_array_constructor): Check for
NULL pointer.
2016-08-25 Steven g. Kargl <kargl@gcc.gnu.org>
PR fortran/77351
* gfortran.dg/pr77351.f90: New test.
From-SVN: r239763
2016-08-25 Richard Biener <rguenther@suse.de>
* dwarf2out.c (gen_remaining_tmpl_value_param_die_attributes):
Only add locations in late dwarf.
(gen_scheduled_generic_parms_dies): Do not set early dwarf here.
(dwarf2out_early_finish): But do it here.
From-SVN: r239753
PR c/77323
* c-decl.c (declspecs_add_type): Set typespec_word even when __intN
or _FloatN or _FloatNx is not supported.
(finish_declspecs): Set type to integer_type_node when _FloatN or
_FloatNx is not supported.
* gcc.dg/pr77323.c: New test.
From-SVN: r239752
2016-08-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/77358
* resolve.c (resolve_fl_procedure): Use the correct gfc_charlen
for deferred character length module procedures.
2016-08-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/77358
* gfortran.dg/submodule_17.f08: New test.
From-SVN: r239740
2016-08-24 Michael Collison <michael.collison@linaro.org>
Michael Collison <michael.collison@arm.com>
* config/arm/arm-modes.def: Add new condition code mode CC_V
to represent the overflow bit.
* config/arm/arm.c (maybe_get_arm_condition_code):
Add support for CC_Vmode.
(arm_gen_unlikely_cbranch): New function to generate common
rtl conditional branches for overflow patterns.
* config/arm/arm-protos.h: Add prototype for
arm_gen_unlikely_cbranch.
* config/arm/arm.md (addv<mode>4, add<mode>3_compareV,
addsi3_compareV_upper): New patterns to support signed
builtin overflow add operations.
(uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper):
New patterns to support unsigned builtin add overflow operations.
(subv<mode>4, sub<mode>3_compare1): New patterns to support signed
builtin overflow subtract operations,
(usubv<mode>4): New patterns to support unsigned builtin subtract
overflow operations.
(negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New patterns
to support builtin overflow negate operations.
* gcc.target/arm/builtin_saddl.c: New testcase.
* gcc.target/arm/builtin_saddll.c: New testcase.
* gcc.target/arm/builtin_uaddl.c: New testcase.
* gcc.target/arm/builtin_uaddll.c: New testcase.
* gcc.target/arm/builtin_ssubl.c: New testcase.
* gcc.target/arm/builtin_ssubll.c: New testcase.
* gcc.target/arm/builtin_usubl.c: New testcase.
* gcc.target/arm/builtin_usubll.c: New testcase.
Co-Authored-By: Michael Collison <michael.collison@arm.com>
From-SVN: r239739
This patch caused a bootstrap failure on AIX.
2016-08-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Revert
2016-08-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* explow.c (get_dynamic_stack_size): Take known alignment of stack
pointer + STACK_DYNAMIC_OFFSET into account when calculating the
size needed.
From-SVN: r239735
2016-08-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
* doc/fragments.texi (MULTILIB_REUSE): Mention that only options in
MULTILIB_OPTIONS should be used. Small wording fixes.
* genmultilib: Memorize set of all option combinations in
combination_space. Detect if RHS of MULTILIB_REUSE uses an option not
found in MULTILIB_OPTIONS by checking if option set is listed in
combination_space. Output new and existing error message to stderr.
From-SVN: r239734
2016-08-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/t-aprofile (MULTILIB_MATCHES): Add mapping for
-mcpu=cortex-a7, -mfpu=neon-fp16, -mfpu=fpv5-d16 and -mfpu=fp-armv8.
Fix typo in -mfpu=vfpv3-d16-fp16 mapping.
(MULTILIB_REUSE): Remove reuse rules for option set including
-mfpu=fp-armv8 and -mfpu=vfpv4
From-SVN: r239733
[gcc]
2016-08-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Set
initialization of all 0's to the 0 constant, instead of directly
generating XOR. Add support for V4SImode vector initialization on
64-bit systems with direct move, and rework the ISA 3.0 V4SImode
initialization. Change variables used in V4SFmode vector
intialization. For V4SFmode vector splat on ISA 3.0, make sure
any memory addresses are in index form. Add support for using
VSPLTH/VSPLTB to initialize vector short and vector char vectors
with all of the same element.
(regno_or_subregno): New helper function to return a register
number for either REG or SUBREG.
(rs6000_adjust_vec_address): Do not generate ADDI <reg>,R0,<num>.
Use regno_or_subregno where possible.
(rs6000_split_v4si_init_di_reg): New helper function to build up a
DImode value from two SImode values in order to generate V4SImode
vector initialization on 64-bit systems with direct move.
(rs6000_split_v4si_init): Split up the insns for a V4SImode vector
initialization.
(rtx_is_swappable_p): V4SImode vector initialization insn is not
swappable.
* config/rs6000/rs6000-protos.h (rs6000_split_v4si_init): Add
declaration.
* config/rs6000/vsx.md (VSX_SPLAT_I): New mode iterators and
attributes to initialize V8HImode and V16QImode vectors with the
same element.
(VSX_SPLAT_COUNT): Likewise.
(VSX_SPLAT_SUFFIX): Likewise.
(UNSPEC_VSX_VEC_INIT): New unspec.
(vsx_concat_v2sf): Eliminate using 'preferred' register classes.
Allow SFmode values to come from Altivec registers.
(vsx_init_v4si): New insn/split for V4SImode vector initialization
on 64-bit systems with direct move.
(vsx_splat_<mode>, VSX_W iterator): Rework V4SImode and V4SFmode
vector initializations, to allow V4SImode vector initializations
on 64-bit systems with direct move.
(vsx_splat_v4si): Likewise.
(vsx_splat_v4si_di): Likewise.
(vsx_splat_v4sf): Likewise.
(vsx_splat_v4sf_internal): Likewise.
(vsx_xxspltw_<mode>, VSX_W iterator): Eliminate using 'preferred'
register classes.
(vsx_xxspltw_<mode>_direct, VSX_W iterator): Likewise.
(vsx_vsplt<VSX_SPLAT_SUFFIX>_di): New insns to support
initializing V8HImode and V16QImode vectors with the same
element.
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE_64BIT): Disallow
optimization if -maltivec=be.
[gcc/testsuite]
2016-08-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-init-1.c: Add tests where the vector is
being created from pointers to memory locations.
* gcc.target/powerpc/vec-init-2.c: Likewise.
From-SVN: r239712
Switch to a new method for determining the order in which import init
functions are invoked: build an init fcn dependence DAG and walk the DAG
to rewrite/adjust priorities to account for discrepancies introduced by
"go test".
This patch includes a change to the export data format generated
by gccgo. Older versions of gccgo will not be able to read object files
produced by a newer gccgo, but the new gcc will still be able to read
old object files.
Fixesgolang/go#15738.
Reviewed-on: https://go-review.googlesource.com/25301
From-SVN: r239708
2016-08-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/77286
* tree-vect-loop.c (vect_analyze_loop_form_1): Do not modify
the CFG here.
(vect_transform_loop): Split exit edges of loop and scalar
loop if required and at the appropriate time.
From-SVN: r239700
PR libstdc++/71771
* include/bits/stl_iterator.h
(operator-(reverse_iterator<Iter>, reverse_iterator<Iter>): Only
define for C++98 mode.
(operator-(move_iterator<Iter>, move_iterator<Iter>): Don't define.
* testsuite/24_iterators/headers/iterator/synopsis.cc: Use
-std=gnu++98.
* testsuite/24_iterators/headers/iterator/synopsis_c++11.cc: New test.
* testsuite/24_iterators/headers/iterator/synopsis_c++14.cc: New test.
* testsuite/24_iterators/headers/iterator/synopsis_c++17.cc: New test.
* testsuite/24_iterators/move_iterator/greedy_ops.cc: Don't test
difference operator.
* testsuite/24_iterators/reverse_iterator/greedy_ops.cc: Only test
difference operator for C++98.
* testsuite/24_iterators/reverse_iterator/71771.cc: New test.
From-SVN: r239691
* get_dynamic_stack_size is passed a SIZE of a data block (which is
allocated elsewhere), the SIZE_ALIGN of the SIZE (i.e. the alignment
of the underlying memory units (e.g. 32 bytes split into 4 times 8
bytes = 64 bit alignment) and the REQUIRED_ALIGN of the data portion
of the allocated memory.
* Assuming the function is called with SIZE = 2, SIZE_ALIGN = 8 and
REQUIRED_ALIGN = 64 it first adds 7 bytes to SIZE -> 9. This is
what is needed to have two bytes 8-byte-aligned at some memory
location without any known alignment.
* Finally round_push is called to round up SIZE to a multiple of the
stack slot size.
The key to understanding this is that the function assumes that
STACK_DYNMAIC_OFFSET is completely unknown at the time its called
and therefore it does not make assumptions about the alignment of
STACKPOINTER + STACK_DYNMAIC_OFFSET. The latest patch simply
hard-codes that SP + SDO is supposed to be aligned to at least
stack slot size (and does that in a very complicated way). Since
there is no guarantee that this is the case on all targets, the
patch is broken. It may miscalculate a SIZE that is too small in
some cases.
However, on many targets there is some guarantee about the
alignment of SP + SDO even if the actual value of SDO is unknown.
On s390x it's always 8-byte-aligned (stack slot size). So the
right fix should be to add knowledge about the target's guaranteed
alignment of SP + SDO to the function. I'm right now testing a
much simpler patch that uses
REGNO_POINTER_ALIGN(VIRTUAL_STACK_DYNAMIC_REGNUM) as the
alignment.
gcc/ChangeLog:
2016-08-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* explow.c (get_dynamic_stack_size): Take known alignment of stack
pointer + STACK_DYNAMIC_OFFSET into account when calculating the
size needed. Correct a typo in a comment.
From-SVN: r239688
gcc/testsuite/ChangeLog:
2016-08-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gcc.target/s390/insv-1.c: Fix test when running with -m31.
From-SVN: r239687
Jason Merrill
Jonathan Wakely
Nathan Sidwell
Richard Biener
Joseph Myers
Kyrylo Tkachov
Prathamesh Kulkarni
GCC Administrator
Steven G. Kargl
Szabolcs Nagy
Marek Polacek
David Edelsohn
Paul Thomas
Michael Collison
Uros Bizjak
Andreas Krebbel
Thomas Preud'homme
Senthil Kumar Selvaraj
Aditya Kumar
Robert Suchanek
Sebastian Huber
Ian Lance Taylor
Michael Meissner
David Malcolm
Christophe Lyon
Fritz Reese
Ian Lance Taylor
Dominik Vogt