* expmed.c (struct init_expmed_rtl): Change all fields but
pow2 and cint from struct rtx_def to rtx.
(init_expmed_one_conv, init_expmed_one_mode): Adjust for that change.
(init_expmed): Likewise. Allocate all the 18 rtxes and ggc_free them
at the end again.
From-SVN: r212325
* cgraph.c (cgraph_create_indirect_edge): Update call of
get_polymorphic_call_info.
* ipa-utils.h (get_polymorphic_call_info): Add parameter CALL.
(possible_polymorphic_call_targets): Add parameter call.
(decl_maybe_in_construction_p): New predicate.
(get_polymorphic_call_info): Add parameter call;
use decl_maybe_in_construction_p.
* gimple-fold.c (fold_gimple_assign): Update use of
possible_polymorphic_call_targets.
(gimple_fold_call): Likewise.
* ipa-prop.c: Inlcude calls.h
(ipa_binfo_from_known_type_jfunc): Check that known type is record.
(param_type_may_change_p): New predicate.
(detect_type_change_from_memory_writes): Break out from ...
(detect_type_change): ... this one; use
param_type_may_change_p.
(detect_type_change_ssa): Use param_type_may_change_p.
(compute_known_type_jump_func): Use decl_maybe_in_construction_p.
* g++.dg/ipa/devirt-26.C: Update testcase.
* g++.dg/ipa/imm-devirt-1.C: Update testcase.
* g++.dg/ipa/imm-devirt-2.C: Update testcase.
From-SVN: r212304
2014-07-04 Tom de Vries <tom@codesourcery.com>
* doc/md.texi (@subsection Constraint Modifier Characters): Clarify
combination of earlyclobber and read/write modifiers.
From-SVN: r212297
PR tree-optimization/61684
* tree-ssa-ifcombine.c (recognize_single_bit_test): Make sure
rhs1 of conversion is a SSA_NAME before using SSA_NAME_DEF_STMT on it.
* gcc.c-torture/compile/pr61684.c: New test.
From-SVN: r212290
gcc/
* config/nds32/nds32-pipelines-auxiliary.c: Add comment to describe
the purpose of this file.
Co-Authored-By: Ling-Hua Tseng <uranus@tinlans.org>
From-SVN: r212285
that are going to be separated from nds32.c source.
gcc/
* config.gcc (nds32*): Add new modules to extra_objs.
(nds32le-*-*): Use t-nds32 makefile fragment for new modules.
(nds32be-*-*): Likewise.
* config/nds32/nds32-cost.c: New file.
* config/nds32/nds32-fp-as-gp.c: New file.
* config/nds32/nds32-intrinsic.c: New file.
* config/nds32/nds32-isr.c: New file.
* config/nds32/nds32-md-auxiliary.c: New file.
* config/nds32/nds32-memory-manipulation.c: New file.
* config/nds32/nds32-pipelines-auxiliary.c: New file.
* config/nds32/nds32-predicates.c: New file.
* config/nds32/t-nds32: New file.
Co-Authored-By: Kito Cheng <kito@0xlab.org>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>
From-SVN: r212280
PR tree-optimization/61682
* wide-int.cc (wi::mul_internal): Handle high correctly
for umul_ppmm using cases and when one of the operands is
equal to 1.
* gcc.c-torture/execute/pr61682.c: New test.
From-SVN: r212273
Firstly, it adds back the split conditions that I accidentally removed.
Without it the dot insns are never generated, or rather, always split
back to a separate compare instruction.
Secondly, the shift amount should be SI always, not GPR, or GCC will
insert a zero-extend at expand time that it cannot get rid of later.
The test tests whether dot-form instructions are generated for both
"dot" and "dot2" cases, that is, with just a CC output or also a GPR
output; for all four basic shifts, with a register amount or an
immediate amount. It also tests for superfluous zero-extends. This
also tests if combine "simplifies" the rotates to right-rotates, which
it shouldn't do anymore.
From-SVN: r212267
* arm.md (arch): Add armv6_or_vfpv3.
(arch_enabled): Add test for the above.
* vfp.md (divsf_vfp, divdf_vfp): Add earlyclobber when code can run
on VFP9.
(sqrtsf_vfp, sqrtdf_vfp): Likewise.
From-SVN: r212265
* gcov-io.c (gcov_read_words): Don't call memmove if excess is 0.
* data-streamer-in.c (streamer_read_hwi): Shift UHWI 1 instead of
HWI 1 and negate the unsigned value.
* expmed.c (expand_sdiv_pow2): For modes wider than word always
use AND instead of shift.
* wide-int-print.cc (print_decs): Negate UHWI instead of HWI.
c-family/
* c-ada-spec.c (dump_ada_nodes): Don't call qsort if
comments->count <= 1, as comments->entries might be NULL.
From-SVN: r212264
* config/rs6000/rs6000.c (rs6000_adjust_atomic_subword): Use
BYTES_BIG_ENDIAN rather than WORDS_BIG_ENDIAN to check for byte
endianness.
From-SVN: r212258
Many targets do not have both rotate and rotatert. Of the 47 targets
in the tree, 17 have both, 9 have only rotate, 2 have only rotatert, and
19 have neither (this is based on "grep -wil" so it can be slightly off).
rs6000 has only rotate, and mips has only rotatert. For such targets
simplifying rotate to rotatert and vice versa is not simplifying things
at all. rs6000 has already way too many rotate patterns (some days it
seems like two thousand, but it is somewhat less in reality still); I
would prefer not to double that again.
So, this patch makes genrecog define HAVE_rotate and HAVE_rotatert if
those RTL codes are mentioned anywhere in the machine description, and
then does the transformation in simplify-rtx.c only if both these flags
are set.
From-SVN: r212239
PR go/61620
runtime: Don't free tiny blocks in map deletion.
The memory allocator now has a special case for tiny blocks
(smaller than 16 bytes) and they can not be explicitly freed.
From-SVN: r212233
