Commit Graph

550 Commits

Author SHA1 Message Date
Claudiu Zissulescu
c4192ad702 [ARC] Fix divdf3 emulation for arcem.
libgcc/
2017-02-27  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/ieee-754/divdf3.S (__divdf3): Use __ARCEM__.

From-SVN: r246498
2017-03-27 12:56:35 +02:00
John Marino
4ccfdb287e freebsd-unwind.h: New file.
2017-03-10  John Marino  <gnugcc@marino.st>

    * config/aarch64/freebsd-unwind.h: New file.
    * config.host: Add aarch64-*-freebsd unwinder.

From-SVN: r246052
2017-03-10 20:33:27 +01:00
Segher Boessenkool
4144e4e301 Build crt*vr.S with AltiVec enabled
These files won't build on targets that do not have AltiVec enabled,
breaking the build, unless we tell GAS that Altivec insns are fine.
The alternative is to not build these files in that case, which is much
more complicated.


libgcc/
	* config/rs6000/crtrestvr.s: Use .machine altivec.
	* config/rs6000/crtsavevr.s: Ditto.

From-SVN: r246051
2017-03-10 20:29:48 +01:00
Jonathan Yong
db9f7f657e gthr-win32.h: Define NOGDI before windows.h include to prevent w32api CC_NONE macro clash...
* config/i386/gthr-win32.h: Define NOGDI before
        windows.h include to prevent w32api CC_NONE macro
        clash with libgfortran.

From-SVN: r245835
2017-03-02 11:03:23 +00:00
Andrew Pinski
31927af6c7 value-unwind.h: New file.
* config/aarch64/value-unwind.h: New file.
	* config.host (aarch64*-*-*): Add aarch64/value-unwind.h
	to tm_file.

From-SVN: r245508
2017-02-16 16:27:42 +00:00
Palmer Dabbelt
0bd99911ee RISC-V Port: libgcc
libgcc/ChangeLog:

2017-02-06  Palmer Dabbelt <palmer@dabbelt.com>

        * config.host: Add RISC-V tuples.
        * config/riscv/atomic.c: New file.
        * config/riscv/crti.S: Likewise.
        * config/riscv/crtn.S: Likewise.
        * config/riscv/div.S: Likewise.
        * config/riscv/linux-unwind.h: Likewise.
        * config/riscv/muldi3.S: Likewise.
        * config/riscv/multi3.S: Likewise.
        * config/riscv/save-restore.S: Likewise.
        * config/riscv/sfp-machine.h: Likewise.
        * config/riscv/t-elf: Likewise.
        * config/riscv/t-elf32: Likewise.
        * config/riscv/t-elf64: Likewise.
        * config/riscv/t-softfp32: Likewise.
        * config/riscv/t-softfp64: Likewise.

From-SVN: r245226
2017-02-06 21:38:51 +00:00
Gerald Pfeifer
c6c82710ed * config/i386/cygming-crtbegin.c (LIBGCJ_SONAME): No longer #define.
From-SVN: r244743
2017-01-21 08:52:32 +00:00
Jiong Wang
a876231c40 [AArch64] Only build & test pauth code for LP64
gcc/
	* config/aarch64/aarch64-builtins.c (aarch64_init_builtins): Register
	register pauth builtins for LP64 only.

libgcc/
	* config/aarch64/aarch64-unwind.h: Empty this file on ILP32.
	* unwind-dw2.c (execute_cfa_program):  Only multiplexing
	DW_CFA_GNU_window_save for AArch64 and LP64.

gcc/testsuite/
	* testsuite/gcc.target/aarch64/return_address_sign_1.c: Enable on LP64
	only.
	* testsuite/gcc.target/aarch64/return_address_sign_2.c: Likewise.
	* testsuite/gcc.target/aarch64/return_address_sign_3.c: Likewise.

From-SVN: r244732
2017-01-20 21:03:41 +00:00
Jiong Wang
aa348be2b0 [AArch64] Always include linux-unwind.h
libgcc/
        * config/aarch64/linux-unwind.h: Always include aarch64-unwind.h.

From-SVN: r244710
2017-01-20 12:27:46 +00:00
Jiong Wang
f2f6dece0e [AArch64, libgcc] Add missing file, forget "svn add"
From-SVN: r244674
2017-01-20 00:21:34 +00:00
Jiong Wang
5636faf2bc [AArch64][4/4] libgcc unwinder support for return address signing
libgcc/
	* config/aarch64/aarch64-unwind.h: New file.
	(DWARF_REGNUM_AARCH64_RA_STATE): Define.
	(MD_POST_EXTRACT_ROOT_ADDR): New target marcro and define it on AArch64.
	(MD_POST_EXTRACT_FRAME_ADDR): Likewise.
	(MD_POST_FROB_EH_HANDLER_ADDR): Likewise.
	(MD_FROB_UPDATE_CONTEXT): Define it on AArch64.
	(aarch64_post_extract_frame_addr): New function.
	(aarch64_post_frob_eh_handler_addr): New function.
	(aarch64_frob_update_context): New function.
	* config/aarch64/linux-unwind.h: Include aarch64-unwind.h
	* config.host (aarch64*-*-elf, aarch64*-*-rtems*,
	aarch64*-*-freebsd*):
	Initialize md_unwind_header to include aarch64-unwind.h.
	* unwind-dw2.c (struct _Unwind_Context): Define "RA_A_SIGNED_BIT".
	(execute_cfa_program): Multiplex DW_CFA_GNU_window_save for
	__aarch64__.
	(uw_update_context): Honor MD_POST_EXTRACT_FRAME_ADDR.
	(uw_init_context_1): Honor MD_POST_EXTRACT_ROOT_ADDR.
	(uw_frob_return_addr): New function.
	(uw_install_context): Use uw_frob_return_addr.

From-SVN: r244673
2017-01-20 00:19:01 +00:00
Joe Seymour
4701fba31c t-msp430 (LIB2ADD): Remove mpy.c
libgcc/
	* config/msp430/t-msp430 (LIB2ADD): Remove mpy.c
	(mpy.o): New rule.
	(libmul_none.a): Add mpy.o

	gcc/testsuite/
	* gcc.target/msp430/mul_f5_muldef.c: New test.

From-SVN: r244564
2017-01-17 22:56:10 -05:00
Joe Seymour
829afb8f05 t-msp430 (libmul_none.a, [...]): Filter archived prerequisites.
2017-01-13  Joe Seymour  <joe.s@somniumtech.com>
* config/msp430/t-msp430 (libmul_none.a, libmul_16.a, libmul_32.a,
libmul_f5.a): Filter archived prerequisites.

From-SVN: r244455
2017-01-13 17:18:07 -05:00
Uros Bizjak
fbed6f3695 builtin_target.c (check_features): Check all supported __builtin_cpu_supports options.
* gcc.target/i386/builtin_target.c (check_features): Check all
	supported __builtin_cpu_supports options.

From-SVN: r244375
2017-01-12 18:30:03 +01:00
Andrew Senkevich
79fc8ffe6c Enable AVX-512 VPOPCNTD/VPOPCNTQ instructions.
gcc/
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET,
	OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET): New.
	* config.gcc: Add avx512vpopcntdqintrin.h.
	* config/i386/avx512vpopcntdqintrin.h: New.
	* config/i386/cpuid.h (bit_AVX512VPOPCNTDQ): New.
	* config/i386/i386-builtin-types.def: Add new types.
	* config/i386/i386-builtin.def (__builtin_ia32_vpopcountd_v16si,
	__builtin_ia32_vpopcountd_v16si_mask, __builtin_ia32_vpopcountq_v8di,
	__builtin_ia32_vpopcountq_v8di_mask): New.
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__AVX512VPOPCNTDQ__.
	* config/i386/i386.c (ix86_target_string): Add -mavx512vpopcntdq.
	(PTA_AVX512VPOPCNTDQ): Define.
	* config/i386/i386.h (TARGET_AVX512VPOPCNTDQ,
	TARGET_AVX512VPOPCNTDQ_P): Define.
	* config/i386/i386.opt: Add mavx512vpopcntdq.
	* config/i386/immintrin.h: Include avx512vpopcntdqintrin.h.
	* config/i386/sse.md (define_insn "vpopcount<mode><mask_name>"): New.

libgcc/
	* config/i386/cpuinfo.h (processor_features): Add
	FEATURE_AVX512VPOPCNTDQ.
	* config/i386/cpuinfo.c (get_available_features): Habdle new
	feature.

gcc/testsuite/
	* g++.dg/other/i386-2.C: Add -mavx512vpopcntdq.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/sse-12.c: Ditto.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/builtin_target.c: Handle new option.
	* gcc.target/i386/funcspec-56.inc: Test new attributes.
	* gcc.target/i386/avx512vpopcntdq-vpopcntd.c: New test.
	* gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto.

From-SVN: r244263
2017-01-10 12:55:41 +00:00
Joseph Myers
fec5f4e041 Make MIPS soft-fp preserve NaN payloads for NAN2008.
The MIPS sfp-machine.h has an _FP_CHOOSENAN implementation which
emulates hardware semantics of not preserving signaling NaN payloads
for an operation with two NaN arguments (although that doesn't suffice
to avoid sNaN payload preservation in any case with just one NaN
argument).

However, those are only hardware semantics in the legacy NaN case; in
the NAN2008 case, the architecture documentation says hardware
preserves payloads in such cases.  Furthermore, this implementation
assumes legacy NaN semantics, so in the NAN2008 case the
implementation actually has the effect of preserving sNaN payloads but
not preserving qNaN payloads, when both should be preserved.

This patch fixes the code just to copy from the first argument (at the
level of libgcc, it's not meaningful which argument is the first and
which is the second).

Tested for mips64-linux-gnu (soft float, NAN2008) with the glibc math/
tests.

	* config/mips/sfp-machine.h (_FP_CHOOSENAN): Always preserve NaN
	payload if [__mips_nan2008].

From-SVN: r244059
2017-01-04 17:06:33 +00:00
Jakub Jelinek
cbe34bb5ed Update copyright years.
From-SVN: r243994
2017-01-01 13:07:43 +01:00
Claudiu Zissulescu
e04ea1daa9 [ARC] Rework code for profiling.
gcc/
2016-12-16  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (LINK_SPEC): Tidy up.
	(ENDFILE_SPEC): Likewise.
	(LIB_SPEC): Likewise.
	(STARTFILE_SPEC): Include gcrt0 when profiling.
	(FUNCTION_PROFILER): Use __mcount.
	* config/arc/arc.opt (mucb-mcount): Remove.
	* doc/invoke.texi (ARC): Remove mucb-mcount doc.
	* arc/arc-protos.h (arc_profile_call): Remove.
	* config/arc/arc.c (write_profile_sections): Likewise.
	(arc_profile_call): Likewise.
	(unspec_prof_hash): Likewise.
	(unspec_prof_htab_eq): Likewise.
	(arc_legitimate_constant_p): Remove UNSPEC_PROF.
	(arc_reorg): Remove call to write_profile_sections.
	* config/arc/arc.md (call): Remove call to arc_profile_call.
	(call_value): Likewise.
	(sibcall): Likewise.
	(sibcall_value): Likewise.
	(define_constants): Remove UNSPEC_PROF.

libgcc/
	* config.host (arc*-*-linux-uclibc*): Remove libgmon, crtg, and
	crtgend.
	(arc*-*-elf*): Likewise.
	* config/arc/t-arc: Remove old gmon lib targets.
	* config/arc/crtg.S: Remove.
	* config/arc/crtgend.S: Likewise.
	* config/arc/gmon/atomic.h: Likewise.
	* config/arc/gmon/auxreg.h: Likewise.
	* config/arc/gmon/dcache_linesz.S: Likewise.
	* config/arc/gmon/gmon.c: Likewise.
	* config/arc/gmon/machine-gmon.h: Likewise.
	* config/arc/gmon/mcount.c: Likewise.
	* config/arc/gmon/prof-freq-stub.S: Likewise.
	* config/arc/gmon/prof-freq.c: Likewise.
	* config/arc/gmon/profil.S: Likewise.
	* config/arc/gmon/sys/gmon.h: Likewise.
	* config/arc/gmon/sys/gmon_out.h: Likewise.
	* config/arc/t-arc-newlib: Likewise.
	* config/arc/t-arc700-uClibc: Renamed to t-arc-uClibc.

From-SVN: r243742
2016-12-16 13:56:21 +01:00
George Spelvin
8ae1c2c129 lib1funcs.S (__ashrdi3): Fix typo from r243545.
libgcc/
	* config/avr/lib1funcs.S (__ashrdi3): Fix typo from r243545.

From-SVN: r243546
2016-12-12 11:57:33 +00:00
George Spelvin
a5b947fa66 lib1funcs.S (__ashldi3): Use __tmp_reg__ to restore R16 instead of push + pop.
libgcc/
	2016-12-12  George Spelvin  <linux@sciencehorizons.net>
	* config/avr/lib1funcs.S (__ashldi3): Use __tmp_reg__ to restore
	R16 instead of push + pop.
	(__ashrdi3, __lshrdi3): Same. And use __zero_reg__ for signs.

From-SVN: r243545
2016-12-12 11:25:51 +00:00
Cupertino Miranda
62440b4f0e [ARC] Fix PIE.
gcc/
2016-12-05  Cupertino Miranda  <cmiranda@synopsys.com>

	* config/arc/arc.h (STARTFILE_SPEC): Use default linux specs.
	(ENDFILE_SPEC): Likewise.

libgcc/
2016-12-05  Cupertino Miranda  <cmiranda@synopsys.com>

	* config.host (arc*-*-linux-uclibc*): Use default extra
	objects. Include linux-android header.
	* config/arc/crti.S (_init): Declare symbol as function.
	(_fini): Likewise.

From-SVN: r243245
2016-12-05 12:16:52 +01:00
Thomas Koenig
31cfd83286 re PR libfortran/78379 (Processor-specific versions for matmul)
2016-12-03  Thomas Koenig  <tkoenig@gcc.gnu.org>

        PR fortran/78379
        * config/i386/cpuinfo.c:  Move denums for processor vendors,
        processor type, processor subtypes and declaration of
        struct __processor_model into
        * config/i386/cpuinfo.h:  New header file.
        * Makefile.am:  Add dependence of m4/matmul_internal_m4 to
        mamtul files..
        * Makefile.in:  Regenerated.
        * acinclude.m4:  Check for AVX, AVX2 and AVX512F.
        * config.h.in:  Add HAVE_AVX, HAVE_AVX2 and HAVE_AVX512F.
        * configure:  Regenerated.
        * configure.ac:  Use checks for AVX, AVX2 and AVX_512F.
        * m4/matmul_internal.m4:  New file. working part of matmul.m4.
        * m4/matmul.m4:  Implement architecture-specific switching
        for AVX, AVX2 and AVX512F by including matmul_internal.m4
        multiple times.
        * generated/matmul_c10.c: Regenerated.
        * generated/matmul_c16.c: Regenerated.
        * generated/matmul_c4.c: Regenerated.
        * generated/matmul_c8.c: Regenerated.
        * generated/matmul_i1.c: Regenerated.
        * generated/matmul_i16.c: Regenerated.
        * generated/matmul_i2.c: Regenerated.
        * generated/matmul_i4.c: Regenerated.
        * generated/matmul_i8.c: Regenerated.
        * generated/matmul_r10.c: Regenerated.
        * generated/matmul_r16.c: Regenerated.
        * generated/matmul_r4.c: Regenerated.
        * generated/matmul_r8.c: Regenerated.

From-SVN: r243219
2016-12-03 09:44:35 +00:00
Andre Vieira
c92e08e3d7 ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call
gcc/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
		Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (detect_cmse_nonsecure_call): New.
	(cmse_nonsecure_call_clear_caller_saved): New.
	(arm_reorg): Use cmse_nonsecure_call_clear_caller_saved.
	(arm_function_ok_for_sibcall): Disable sibcalls for
	cmse_nonsecure_call.
	* config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
	* config/arm/arm.md (call): Handle cmse_nonsecure_entry.
	(call_value): Likewise.
	(nonsecure_call_internal): New.
	(nonsecure_call_value_internal): New.
	* config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
	(*nonsecure_call_value_reg_thumb1_v5): New.
	* config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
	(*nonsecure_call_value_reg_thumb2): New.
	* config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.

    libgcc/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	       Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/cmse_nonsecure_call.S: New.
	* config/arm/t-arm: Compile cmse_nonsecure_call.S

    gcc/testsuite/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
		Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir.
	* gcc.target/arm/cmse/cmse-9.c: Added some extra tests.
	* gcc.target/arm/cmse/cmse-14.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-4.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-5.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-6.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-7.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-8.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-9.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New.
	* gcc.target/arm/cmse/baseline/cmse-11.c: New.
	* gcc.target/arm/cmse/baseline/cmse-13.c: New.
	* gcc.target/arm/cmse/baseline/cmse-6.c: New.
	* gcc.target/arm/cmse/baseline/union-1.c: New.
	* gcc.target/arm/cmse/baseline/union-2.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-4.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-5.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-6.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-7.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-8.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-9.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: New.
	* gcc.target/arm/cmse/mainline/union-1.c: New.
	* gcc.target/arm/cmse/mainline/union-2.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.


Co-Authored-By: Thomas Preud'homme <thomas.preudhomme@arm.com>

From-SVN: r243192
2016-12-02 15:33:26 +00:00
Andre Vieira
de7b572345 Add support for ARMv8-M's Secure Extensions flag and intrinsics
gcc/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	        Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config.gcc (extra_headers): Added arm_cmse.h.
	* config/arm/arm-arches.def (ARM_ARCH):
	(armv8-m): Add FL2_CMSE.
	(armv8-m.main): Likewise.
	(armv8-m.main+dsp): Likewise.
	* config/arm/arm-c.c
	(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
	* config/arm/arm-flags.h: Define FL2_CMSE.
	* config/arm.c (arm_arch_cmse): New.
	(arm_option_override): New error for unsupported cmse target.
	* config/arm/arm.h (arm_arch_cmse): New.
	* config/arm/arm.opt (mcmse): New.
	* config/arm/arm_cmse.h: New file.
	* doc/invoke.texi (ARM Options): Add -mcmse.
	* doc/sourcebuild.texi (arm_cmse_ok): Add new effective target.
	* doc/extend.texi: Add ARMv8-M Security Extensions entry.

    gcc/testsuite/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	        Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse.exp: New.
	* gcc.target/arm/cmse/cmse-1.c: New.
	* gcc.target/arm/cmse/cmse-12.c: New.
	* lib/target-supports.exp
	(check_effective_target_arm_cmse_ok): New.

    libgcc/ChangeLog:
    2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/t-arm (HAVE_CMSE): New.
	* config/arm/cmse.c: New.


Co-Authored-By: Thomas Preud'homme <thomas.preudhomme@arm.com>

From-SVN: r243187
2016-12-02 15:22:43 +00:00
Thomas Petazzoni
b3a5bff4d7 re PR target/74748 (libgcc_s.so.1 isn't created correctly for Blackfin FDPIC)
PR gcc/74748
	* libgcc/config/bfin/libgcc-glibc.ver, libgcc/config/bfin/t-linux:
	use generic linker version information on Blackfin.

2016-11-27  Iain Sandoe  <iain@codesourcery.com>

From-SVN: r242934
2016-11-28 14:30:40 -07:00
Iain Sandoe
b410cf1dc0 [Darwin] fix PR67710 by updating 'as' specs to handle newer assembler versions.
A/ Newer versions of ld64 check the min_version command, and newer versions of
   the system assembler inserts this in response to "-mmacosx-version-min=" on
   the assembler line. Unless one makes sensible versions, some object is bound
   to conflict.

B/ Additionally, there's a difference in behaviour between "as" and "ld" when
   presented with xx.yy.zz (ld truncates to xx.yy, as doesn't); net result is
   that one needs to pass a truncated version to "as".

So (if the assembler supports minversion commands)
(a) provide a truncated minversion (as asm_macosx_version_min, which is a
    driver-only var).
(b) pass this to "as"
(c) Update tests to determine 'HAVE_AS_MMACOSX_VERSION_MIN_OPTION'
    (Rainer's patch)
(d) For some reason the testcases are "run" (it's not obvious they need to be,
    they are checking compile-time issues)
  - anyway, to preserve the status quo, I've left them as exec.  However, the
    minimum version that can be code-gened for is target-dependent (there are no
    released x86 versions before 10.4, for example).  To avoid conflicts where
    the "as" is assuming some minimum, I've set the testversion to 10.5 (which
    is supported by all the archs we have)
(e) We need to ensure that libgcc and crts are generated with a sufficiently
    old minversion not to conflict.

gcc/

2016-11-27  Iain Sandoe  <iain@codesourcery.com>
	    Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	PR target/67710
	* config.in: Regenerate
	* config/darwin-driver.c (darwin_driver_init): Emit a version string
	for the assembler.
	* config/darwin.h(ASM_MMACOSX_VERSION_MIN_SPEC): New, new tests.
	* config/darwin.opt(asm_macosx_version_min): New.
	* config/i386/darwin.h: Handle ASM_MMACOSX_VERSION_MIN_SPEC.
	* configure: Regenerate
	* configure.ac: Check for mmacosx-version-min handling.

gcc/testsuite/

2016-11-27  Iain Sandoe  <iain@codesourcery.com>
	    Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
	    Dominique d'Humieres  <dominiq@lps.ens.fr>

	PR target/67710
	*  gcc.dg/darwin-minversion-1.c: Update min version check.
	*  gcc.dg/darwin-minversion-2.c: Likewise.
	*  gcc.dg/darwin-minversion-3.c: Likewise.

libgcc/

2016-11-27  Iain Sandoe  <iain@codesourcery.com>
	    Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	PR target/67710
	*  config/t-darwin: Default builds to 10.5 codegen.


Co-Authored-By: Dominique d'Humieres <dominiq@lps.ens.fr>
Co-Authored-By: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

From-SVN: r242898
2016-11-27 15:07:22 +00:00
James Greenhalgh
2e5f8203d2 [Patch libgcc AArch64 12/17] Enable hfmode soft-float conversions and truncations
gcc/

	* config/aarch64/aarch64-c.c (aarch64_scalar_mode_supported_p): New.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Define.

libgcc/

	* config/aarch64/sfp-machine.h (_FP_NANFRAC_H): Define.
	(_FP_NANSIGN_H): Likewise.
	* config/aarch64/t-softfp (softfp_extensions): Add hftf.
	(softfp_truncations): Add tfhf.
	(softfp_extras): Add required conversion functions.

From-SVN: r242844
2016-11-24 18:16:55 +00:00
James Greenhalgh
bea64ca303 [Patch 15/17 libgcc ARM] Add double to half conversions.
libgcc/

	* config/arm/fp16.c (binary64): New.
	(__gnu_d2h_internal): New.
	(__gnu_d2h_ieee): New.
	(__gnu_d2h_alternative): New.



Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com>

From-SVN: r242782
2016-11-23 17:31:25 +00:00
James Greenhalgh
8630cadbc5 [Patch 14/17] [libgcc, ARM] Generalise float-to-half conversion function.
libgcc/

	* config/arm/fp16.c (struct format): New.
	(binary32): New.
	(__gnu_float2h_internal): New.  Body moved from
	__gnu_f2h_internal and generalize.
	(_gnu_f2h_internal): Move body to function __gnu_float2h_internal.
	Call it with binary32.



Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com>

From-SVN: r242781
2016-11-23 17:30:02 +00:00
H.J. Lu
9775c1a5ea Add avx5124vnniw/avx5124fmaps to target attributes
gcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/i386.c (processor_features): Add F_AVX5124VNNIW,
	F_AVX5124FMAPS.
	(isa_names_table): Handle new features.

gcc/testsuite/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* gcc.target/i386/builtin_target.c: Handle new "avx5124vnniw",
	"avx5124fmaps".
	* gcc.target/i386/funcspec-56.inc: Test new attributes.

libgcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/cpuinfo.c (processor_features): Add
	FEATURE_AVX5124VNNIW, FEATURE_AVX5124FMAPS.

From-SVN: r242570
2016-11-17 14:18:23 -08:00
Claudiu Zissulescu
48c842ab84 [ARC][libgcc] Add support for QuarkSE processor.
libgcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/dp-hack.h (ARC_OPTFPE): Define.
	(__ARC_NORM__): Use instead ARC_OPTFPE.
	* config/arc/fp-hack.h: Likewise.
	* config/arc/lib1funcs.S (ARC_OPTFPE): Define.
	(__ARC_MPY__): Use it insetead of __ARC700__ and __HS__.

From-SVN: r242547
2016-11-17 14:43:43 +01:00
Alexander Monakov
5012919d0b nvptx backend prerequisites for OpenMP offloading
gcc/
	* config/nvptx/mkoffload.c (main): Check that either OpenACC or OpenMP
	is selected.  Pass -mgomp to offload compiler in OpenMP case.
	* config/nvptx/nvptx-protos.h (nvptx_shuffle_kind): Move enum
	declaration from nvptx.c.
	(nvptx_gen_shuffle): Declare.
	(nvptx_output_set_softstack): Declare.
	* config/nvptx/nvptx.c (nvptx_shuffle_kind): Move to nvptx-protos.h.
	(need_softstack_decl): New variable.
	(need_unisimt_decl): New variable.
	(diagnose_openacc_conflict): New.  Use it...
	(nvptx_option_override): ...here.  Handle TARGET_GOMP.
	(nvptx_encode_section_info): Handle "shared" attribute.
	(write_as_kernel): Restrict to OpenACC target regions.
	(init_softstack_frame): New.
	(nvptx_init_unisimt_predicate): New.
	(write_omp_entry): New.  Use it...
	(nvptx_declare_function_name): ...here to emit OpenMP target region
	entrypoints.  Handle TARGET_SOFT_STACK.  Call
	nvptx_init_unisimt_predicate.
	(nvptx_output_set_softstack): New.
	(nvptx_get_drap_rtx): Return %argp as the DRAP if needed.
	(nvptx_gen_shuffle): Export.
	(nvptx_output_call_insn): Handle COND_EXEC patterns.  Emit instruction
	predicate.
	(nvptx_print_operand): Fix handling of instruction predicates.
	(nvptx_get_unisimt_master): New helper function.
	(nvptx_get_unisimt_predicate): Ditto.
	(nvptx_call_insn_is_syscall_p): Ditto.
	(nvptx_unisimt_handle_set): Ditto.
	(nvptx_reorg_uniform_simt): New.  Transform code for -muniform-simt.
	(nvptx_reorg): Call nvptx_reorg_uniform_simt.
	(nvptx_handle_shared_attribute): New.  Use it...
	(nvptx_attribute_table): ... here (new entry).
	(nvptx_record_offload_symbol): Handle NULL attributes.
	(nvptx_file_end): Handle need_softstack_decl and need_unisimt_decl.
	(nvptx_simt_vf): New.
	(TARGET_SIMT_VF): Define.
	* config/nvptx/nvptx.h (TARGET_CPU_CPP_BUILTINS): Define
	__nvptx_softstack or __nvptx_unisimt__ when -msoft-stack, or resp.
	-muniform-simt option is active.
	(STACK_SIZE_MODE): Define.
	(FIXED_REGISTERS): Adjust.
	(SOFTSTACK_SLOT_REGNUM): New.
	(SOFTSTACK_PREV_REGNUM): New.
	(REGISTER_NAMES): Adjust.
	(struct machine_function): New fields.
	* config/nvptx/nvptx.md (UNSPEC_SET_SOFTSTACK): New.
	(UNSPEC_VOTE_BALLOT): Ditto.
	(UNSPEC_LANEID): Ditto.
	(UNSPECV_NOUNROLL): Ditto.
	(atomic): New attribute.
	(predicable): New attribute.  Generate predicated forms via
	define_cond_exec.
	(br_true): Mark as not predicable.
	(br_false): Ditto.
	(br_true_uni): Ditto.
	(br_false_uni): Ditto.
	(return): Ditto.
	(trap_if_true): Ditto.
	(trap_if_false): Ditto.
	(nvptx_fork): Ditto.
	(nvptx_forked): Ditto.
	(nvptx_joining): Ditto.
	(nvptx_join): Ditto.
	(nvptx_barsync): Ditto.
	(epilogue): Emit stack restore if TARGET_SOFT_STACK.
	(allocate_stack): Implement for TARGET_SOFT_STACK.  Remove unused code.
	(allocate_stack_<mode>): Remove unused pattern.
	(set_softstack_insn): New pattern.
	(restore_stack_block): Handle for TARGET_SOFT_STACK.
	(nvptx_vote_ballot): New pattern.
	(omp_simt_lane): Ditto.
	(omp_simt_last_lane): Ditto.
	(omp_simt_ordered): Ditto.
	(omp_simt_vote_any): Ditto.
	(omp_simt_xchg_bfly): Ditto.
	(omp_simt_xchg_idx): Ditto.
	(nvptx_nounroll): Ditto.
	(atomic_compare_and_swap<mode>_1): Mark with atomic attribute.
	(atomic_exchange<mode>): Ditto.
	(atomic_fetch_add<mode>): Ditto.
	(atomic_fetch_addsf): Ditto.
	(atomic_fetch_<logic><mode>): Ditto.
	* config/nvptx/nvptx.opt: (msoft-stack): New option.
	(muniform-simt): Ditto.
	(mgomp): Ditto.
	* config/nvptx/t-nvptx (MULTILIB_OPTIONS): New.
	* doc/extend.texi (Nvidia PTX Variable Attributes): New section.
	* doc/invoke.texi (msoft-stack): Document.
	(muniform-simt): Document
	(mgomp): Document.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in: (TARGET_SIMT_VF): New hook.
	* target.def: Define it.
	* target-insns.def (omp_simt_lane): New.
	(omp_simt_last_lane): New.
	(omp_simt_ordered): New.
	(omp_simt_vote_any): New.
	(omp_simt_xchg_bfly): New.
	(omp_simt_xchg_idx): New.

libgcc/
	* config/nvptx/crt0.c (__main): Setup __nvptx_stacks and __nvptx_uni.
	* config/nvptx/mgomp.c: New file.
	* config/nvptx/t-nvptx: Add mgomp.c

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_alloca): Use a
	compile test.
	* gcc.target/nvptx/softstack.c: New test.
	* gcc.target/nvptx/decl-shared.c: New test.
	* gcc.target/nvptx/decl-shared-init.c: New test.

From-SVN: r242503
2016-11-16 20:17:00 +03:00
Claudiu Zissulescu
d64af69fd5 [ARC] [libgcc] Fix defines
libgcc/
2016-11-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/lib1funcs.S (__mulsi3): Use feature defines instead
	of checking for cpus.
	(__umulsidi3, __umulsi3_highpart, __udivmodsi4, __divsi3)
	(__modsi3, __clzsi2): Likewise.

From-SVN: r242428
2016-11-15 16:42:17 +01:00
Szabolcs Nagy
9d8f95deca [i386][musl] Add cpuinfo to static libgcc only on *-musl*
The __cpu_indicator_init and __cpu_model symbols are not safe to use
from shared libgcc_s.so from ifunc resolvers, so since gcc-6, only
the definitions from static libgcc.a are used, however the symbols
are kept in libgcc_s as well for backward compatibility (with
appropriate symbol version).  On targets without such backward
compatibility concern add cpuinfo to the static library only (this
avoids running the ctor, reduces libgcc_s size and elf abi concerns
about the versioned symbols).

libgcc/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config.host (i[3456]86-*-musl*, x86_64-*-musl*): Use
	i386/t-cpuinfo-static instead of i386/t-cpuinfo.
	* config/i386/t-cpuinfo-static: New.

From-SVN: r242268
2016-11-11 17:31:07 +00:00
John David Anglin
4c6d7494fc pa64-hpux-lib.h: New file.
libgcc/
	* config/pa/pa64-hpux-lib.h: New file.  
	(EH_FRAME_SECTION_NAME): Rename to __LIBGCC_EH_FRAME_SECTION_NAME__.
	(DTORS_SECTION_ASM_OP): Rename to __LIBGCC_DTORS_SECTION_ASM_OP__.
	* config.host (tm_file): Add pa/pa64-hpux-lib.h to tm_file on
	hppa*64*-*-hpux11*.
gcc/
	* config/pa/pa64-hpux.h (PA_INIT_FRAME_DUMMY_ASM_OP): Move to
	config/pa/pa64-hpux-lib.h.
	(PA_CRTBEGIN_HACK): Likewise.
	(DTOR_LIST_BEGIN): Likewise.

From-SVN: r241356
2016-10-19 22:52:21 +00:00
Max Filippov
2a26adf1d8 xtensa: don't use unwind-dw2-fde-dip with elf targets
Define LIB2ADDEH_XTENSA_UNWIND_DW2_FDE to unwind-dw2-fde.c in
xtensa/t-elf and to unwind-dw2-fde-dip.c in xtensa/t-linux and use
LIB2ADDEH_XTENSA_UNWIND_DW2_FDE in LIB2ADDEH definition.

This fixes build for elf target with windowed xtensa core that currently
breaks with the following error message:
    
  unwind-dw2-fde-dip.c:36:40: fatal error: elf.h: No such file or directory

2016-10-18  Max Filippov  <jcmvbkbc@gmail.com>
libgcc/
	* config/xtensa/t-elf (LIB2ADDEH_XTENSA_UNWIND_DW2_FDE): New
	definition.
	* config/xtensa/t-linux (LIB2ADDEH_XTENSA_UNWIND_DW2_FDE): New
	definition.
	* config/xtensa/t-windowed (LIB2ADDEH): Use
	LIB2ADDEH_XTENSA_UNWIND_DW2_FDE defined by either xtensa/t-elf
	or xtensa/t-linux.

From-SVN: r241313
2016-10-18 19:12:19 +00:00
Ding-Kai Chen
66192aa129 xtensa: add HW FPU sequences for DIV/SQRT/RECIP/RSQRT
Use new FPU instruction sequences documented in the ISA book to
implement __divsf3, __divdf3, __recipsf2, __recipdf2, __rsqrtsf2,
__rsqrtdf2 and __ieee754_sqrtf and __ieee754_sqrt.

2016-10-18  Ding-Kai Chen  <dkchen@cadence.com>
libgcc/
	* config/xtensa/ieee754-df.S (__recipdf2, __rsqrtdf2,
	__ieee754_sqrt): New functions.
	(__divdf3): Add implementation with new FPU instructions under
	#if XCHAL_HAVE_DFP_DIV.
	* config/xtensa/ieee754-sf.S (__recipsf2, __rsqrtsf2,
	__ieee754_sqrtf): New functions.
	(__divsf3): Add implementation with new FPU instructions under
	#if XCHAL_HAVE_FP_DIV.
	* config/xtensa/t-xtensa (LIB1ASMFUNCS): Add _sqrtf, _recipsf2
	_rsqrtsf2, _sqrt, _recipdf2 and _rsqrtdf2.

From-SVN: r241312
2016-10-18 19:06:33 +00:00
Thomas Preud'homme
4d0cdd0ce6 Move MEMMODEL_* from coretypes.h to memmodel.h
2016-10-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * coretypes.h: Move MEMMODEL_* macros and enum memmodel definition
    into ...
    * memmodel.h: This file.
    * alias.c, asan.c, auto-inc-dec.c, bb-reorder.c, bt-load.c,
      caller-save.c, calls.c, ccmp.c, cfgbuild.c, cfgcleanup.c,
      cfgexpand.c, cfgloopanal.c, cfgrtl.c, cilk-common.c, combine.c,
      combine-stack-adj.c, common/config/aarch64/aarch64-common.c,
      common/config/arm/arm-common.c, common/config/bfin/bfin-common.c,
      common/config/c6x/c6x-common.c, common/config/i386/i386-common.c,
      common/config/ia64/ia64-common.c, common/config/nvptx/nvptx-common.c,
      compare-elim.c, config/aarch64/aarch64-builtins.c,
      config/aarch64/aarch64-c.c, config/aarch64/cortex-a57-fma-steering.c,
      config/arc/arc.c, config/arc/arc-c.c, config/arm/arm-builtins.c,
      config/arm/arm-c.c, config/avr/avr.c, config/avr/avr-c.c,
      config/avr/avr-log.c, config/bfin/bfin.c, config/c6x/c6x.c,
      config/cr16/cr16.c, config/cris/cris.c, config/darwin-c.c,
      config/darwin.c, config/epiphany/epiphany.c,
      config/epiphany/mode-switch-use.c,
      config/epiphany/resolve-sw-modes.c, config/fr30/fr30.c,
      config/frv/frv.c, config/ft32/ft32.c, config/h8300/h8300.c,
      config/i386/i386-c.c, config/i386/winnt.c, config/iq2000/iq2000.c,
      config/lm32/lm32.c, config/m32c/m32c.c, config/m32r/m32r.c,
      config/m68k/m68k.c, config/mcore/mcore.c,
      config/microblaze/microblaze.c, config/mmix/mmix.c,
      config/mn10300/mn10300.c, config/moxie/moxie.c,
      config/msp430/msp430.c, config/nds32/nds32-cost.c,
      config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
      config/nds32/nds32-memory-manipulation.c,
      config/nds32/nds32-predicates.c, config/nds32/nds32.c,
      config/nios2/nios2.c, config/nvptx/nvptx.c, config/pa/pa.c,
      config/pdp11/pdp11.c, config/rl78/rl78.c, config/rs6000/rs6000-c.c,
      config/rx/rx.c, config/s390/s390-c.c, config/s390/s390.c,
      config/sh/sh.c, config/sh/sh-c.c, config/sh/sh-mem.cc,
      config/sh/sh_treg_combine.cc, config/sol2.c, config/spu/spu.c,
      config/stormy16/stormy16.c, config/tilegx/tilegx.c,
      config/tilepro/tilepro.c, config/v850/v850.c, config/vax/vax.c,
      config/visium/visium.c, config/vms/vms-c.c, config/xtensa/xtensa.c,
      coverage.c, cppbuiltin.c, cprop.c, cse.c, cselib.c, dbxout.c, dce.c,
      df-core.c, df-problems.c, df-scan.c, dojump.c, dse.c, dwarf2asm.c,
      dwarf2cfi.c, dwarf2out.c, emit-rtl.c, except.c, explow.c, expmed.c,
      expr.c, final.c, fold-const.c, function.c, fwprop.c, gcse.c,
      ggc-page.c, haifa-sched.c, hsa-brig.c, hsa-gen.c, hw-doloop.c,
      ifcvt.c, init-regs.c, internal-fn.c, ira-build.c, ira-color.c,
      ira-conflicts.c, ira-costs.c, ira-emit.c, ira-lives.c, ira.c, jump.c,
      loop-doloop.c, loop-invariant.c, loop-iv.c, loop-unroll.c,
      lower-subreg.c, lra.c, lra-assigns.c, lra-coalesce.c,
      lra-constraints.c, lra-eliminations.c, lra-lives.c, lra-remat.c,
      lra-spills.c, mode-switching.c, modulo-sched.c, omp-low.c, passes.c,
      postreload-gcse.c, postreload.c, predict.c, print-rtl-function.c,
      recog.c, ree.c, reg-stack.c, regcprop.c, reginfo.c, regrename.c,
      reload.c, reload1.c, reorg.c, resource.c, rtl-chkp.c, rtl-tests.c,
      rtlanal.c, rtlhooks.c, sched-deps.c, sched-rgn.c, sdbout.c,
      sel-sched-ir.c, sel-sched.c, shrink-wrap.c, simplify-rtx.c,
      stack-ptr-mod.c, stmt.c, stor-layout.c, target-globals.c,
      targhooks.c, toplev.c, tree-nested.c, tree-outof-ssa.c,
      tree-profile.c, tree-ssa-coalesce.c, tree-ssa-ifcombine.c,
      tree-ssa-loop-ivopts.c, tree-ssa-loop.c, tree-ssa-reassoc.c,
      tree-ssa-sccvn.c, tree-vect-data-refs.c, ubsan.c, valtrack.c,
      var-tracking.c, varasm.c: Include memmodel.h.
    * genattrtab.c (write_header): Include memmodel.h in generated file.
    * genautomata.c (main): Likewise.
    * gengtype.c (open_base_files): Likewise.
    * genopinit.c (main): Likewise.
    * genconditions.c (write_header): Include memmodel.h earlier in
    generated file.
    * genemit.c (main): Likewise.
    * genoutput.c (output_prologue): Likewise.
    * genpeep.c (main): Likewise.
    * genpreds.c (write_insn_preds_c): Likewise.
    * genrecog.c (write_header): Likewise.
    * Makefile.in (PLUGIN_HEADERS): Include memmodel.h

    gcc/ada/
    * gcc-interface/utils2.c: Include memmodel.h.

    gcc/c-family/
    * c-cppbuiltin.c: Include memmodel.h.
    * c-opts.c: Likewise.
    * c-pragma.c: Likewise.
    * c-warn.c: Likewise.

    gcc/c/
    * c-typeck.c: Include memmodel.h.

    gcc/cp/
    * decl2.c: Include memmodel.h.
    * rtti.c: Likewise.

    gcc/fortran/
    * trans-intrinsic.c: Include memmodel.h.

    gcc/go/
    * go-backend.c: Include memmodel.h.

    libgcc/
    * libgcov-profiler.c: Replace MEMMODEL_* macros by their __ATOMIC_*
    equivalent.
    * config/tilepro/atomic.c: Likewise and stop casting model to
    enum memmodel.

From-SVN: r241121
2016-10-13 14:17:52 +00:00
Andreas Schwab
a786cec431 crtbegin.S (__do_jv_register_classes): Remove.
* config/ia64/crtbegin.S (__do_jv_register_classes): Remove.
(.section .init_array): Don't call __do_jv_register_classes.
(.section .init): Likewise.

From-SVN: r240771
2016-10-05 07:50:34 +00:00
Jakub Jelinek
5a79befbf4 defaults.h (JCR_SECTION_NAME, [...]): Remove.
gcc/
	* defaults.h (JCR_SECTION_NAME, TARGET_USE_JCR_SECTION): Remove.
	* system.h (JCR_SECTION_NAME, TARGET_USE_JCR_SECTION): Poison.
	* doc/tm.texi.in (TARGET_USE_JCR_SECTION): Remove.
	* doc/tm.texi: Regenerated.
	* config/i386/mingw32.h (TARGET_USE_JCR_SECTION): Remove.
	* config/i386/cygming.h (TARGET_USE_JCR_SECTION): Remove.
	* config/darwin.h (JCR_SECTION_NAME): Remove.
	* config/pa/pa64-hpux.h (JCR_SECTION_NAME): Remove.
	* config/rs6000/aix71.h (TARGET_USE_JCR_SECTION): Remove.
	* config/rs6000/aix51.h (TARGET_USE_JCR_SECTION): Remove.
	* config/rs6000/aix52.h (TARGET_USE_JCR_SECTION): Remove.
	* config/rs6000/aix53.h (TARGET_USE_JCR_SECTION): Remove.
	* config/rs6000/aix61.h (TARGET_USE_JCR_SECTION): Remove.
gcc/c-family/
	* c-cppbuiltin.c (c_cpp_builtins): Don't define
	__LIBGCC_JCR_SECTION_NAME__.
libgcc/
	* config/i386/cygming-crtbegin.c (_Jv_RegisterClasses): Remove.
	(__JCR_LIST__): Remove.
	(__gcc_register_frame): Don't attempt to _Jv_RegisterClasses.
	* config/i386/cygming-crtend.c (__JCR_END__): Remove.
	* config/ia64/crtbegin.S (__JCR_LIST__): Remove.
	* config/ia64/crtend.S (__JCR_END__): Remove.
	* crtstuff.c: Remove __LIBGCC_JCR_SECTION_NAME__ from preprocessor
	conditionals.
	(__JCR_LIST__, __JCR_END__): Remove.
	(frame_dummy): Don't attempt to _Jv_RegisterClasses.
	(__do_global_ctors_1): Likewise.

From-SVN: r240739
2016-10-04 09:49:44 +02:00
Uros Bizjak
e0ab375340 cpuinfo.c (__get_cpuid_output): Remove.
* config/i386/cpuinfo.c (__get_cpuid_output): Remove.
	(__cpu_indicator_init): Call __get_cpuid, not __get_cpuid_output.

From-SVN: r240590
2016-09-28 20:22:16 +02:00
Szabolcs Nagy
726f49c3d9 [mips] Fix linux header use in libgcc
libgcc/
	* config/mips/linux-unwind.h: Use sys/syscall.h.

From-SVN: r239759
2016-08-25 14:08:27 +00:00
Bill Schmidt
d6e69705e2 _divkc3.c: Add copyright/license boilerplate.
2016-07-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/_divkc3.c: Add copyright/license boilerplate.
	* config/rs6000/_mulkc3.c: Likewise.

From-SVN: r238894
2016-07-29 20:15:54 +00:00
Georg-Johann Lay
96aa1f9558 lib1funcs.S (__muldi3): No need to clear zero_reg as previous call to __umulhisi3 already cleared it.
* config/avr/lib1funcs.S (__muldi3) [have MUL]: No need to clear
	zero_reg as previous call to __umulhisi3 already cleared it.

From-SVN: r238850
2016-07-29 09:14:02 +00:00
Aurelien Jarno
a1b01d3403 [ARM] Fix PR target/59833
For Aurelien Jarno <aurelien@aurel32.net>

On ARM soft-float, the float to double conversion doesn't convert a sNaN
to qNaN as the IEEE Std 754 standard mandates:

"Under default exception handling, any operation signaling an invalid
operation exception and for which a floating-point result is to be
delivered shall deliver a quiet NaN."

Given the soft float ARM code ignores exceptions and always provides a
result, a float to double conversion of a signaling NaN should return a
quiet NaN. Fix this in extendsfdf2.

gcc/ChangeLog:

	PR target/59833
	* config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN.

gcc/testsuite/ChangeLog:

	* gcc.dg/pr59833.c: New testcase.

From-SVN: r238584
2016-07-21 08:27:47 +00:00
Bill Schmidt
f906f5edd3 _divkc3.c: New.
[libgcc]

2016-07-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/_divkc3.c: New.
	* config/rs6000/_mulkc3.c: New.
	* config/rs6000/quad-float128.h: Define TFtype; declare _mulkc3
	and _divkc3.
	* config/rs6000/t-float128: Add _mulkc3 and _divkc3 to
	fp128_ppc_funcs.

[gcc/testsuite]

2016-07-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/divkc3-1.c: New.
	* gcc.target/powerpc/mulkc3-1.c: New.

From-SVN: r238253
2016-07-12 16:05:18 +00:00
Hale Wang
827424041e lib1funcs.S: Add new wrapper.
2016-07-11  Hale Wang  <hale.wang@arm.com>
	    Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/lib1funcs.S: Add new wrapper.

Co-Authored-By: Andre Vieira <andre.simoesdiasvieira@arm.com>

From-SVN: r238215
2016-07-11 17:11:31 +00:00
Thomas Preud'homme
05a437c1f3 arm-arches.def (armv8-m.base): Define new architecture.
2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-arches.def (armv8-m.base): Define new architecture.
    (armv8-m.main): Likewise.
    (armv8-m.main+dsp): Likewise.
    * config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define.
    (FL_FOR_ARCH8M_MAIN): Likewise.
    * config/arm/arm-tables.opt: Regenerate.
    * config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and
    armv8-m.main+dsp to BE8_LINK_SPEC.
    * config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M.
    (enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN.
    * config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M
    Baseline and Mainline.
    (arm_option_override_internal): Also disable arm_restrict_it when
    !arm_arch_notm.  Update comment for -munaligned-access to also cover
    ARMv8-M Baseline.
    (arm_file_start): Increase buffer size for printing architecture name.
    * doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main
    and armv8-m.main+dsp.
    (mno-unaligned-access): Clarify that this is disabled by default for
    ARMv8-M Baseline architectures as well.

    gcc/testsuite/
    * lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and
    check_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and
    ARMv8-M Mainline architectures.

    libgcc/
    * config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M.

From-SVN: r238081
2016-07-07 08:54:40 +00:00
Thomas Preud'homme
3d16d9ec3c lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later and ARMv5t* rather than for a fixed list of...
2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    libgcc/
    * config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later
    and ARMv5t* rather than for a fixed list of architectures.

From-SVN: r238080
2016-07-07 08:54:28 +00:00
Thomas Preud'homme
6f49395177 elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to decide whether to prevent...
2016-07-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to
    decide whether to prevent some libgcc routines being included for some
    multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the
    link between this condition and the one in
    libgcc/config/arm/lib1func.S.

    gcc/testsuite/
    * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use
    __ARM_ARCH_ISA_ARM to test for Cortex-M devices.

    libgcc/
    * config/arm/bpabi-v6m.S: Clarify what architectures is the
    implementation suitable for.
    * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases
    for all Thumb-1 only targets.
    (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets.
    (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than
    __ARM_ARCH_6M__.
    (EQUIV): Likewise.
    (ARM_FUNC_ALIAS): Likewise.
    (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv
    version.
    (modsi3): Likewise.
    (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__.
    (clzdi2): Likewise.
    (ctzsi2): Likewise.
    (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than
    __ARM_ARCH_6M__ in guard for checking whether it is defined.
    (final includes): Test for NOT_ISA_TARGET_32BIT rather than
    __ARM_ARCH_6M__ and add comment to indicate the connection between
    this condition and the one in gcc/config/arm/elf.h.
    * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and
    __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.
    * config/arm/t-softfp: Likewise.

From-SVN: r238079
2016-07-07 08:54:18 +00:00