Commit Graph

184651 Commits

Author SHA1 Message Date
Tobias Burnus e4aefface2 Fortran/OpenMP: Fix var-list expr parsing with array/dt
gcc/fortran/ChangeLog:

	* openmp.c (gfc_match_omp_variable_list): Gobble whitespace before
	checking whether a '%' or parenthesis-open follows as next character.

gcc/testsuite/ChangeLog:

	* gfortran.dg/gomp/map-5.f90: New test.
2021-04-28 22:36:30 +02:00
Jonathan Wright c99f374713 aarch64: Remove unspecs from [su]qmovn RTL pattern
Saturating truncation can be expressed using the RTL expressions
ss_truncate and us_truncate. This patch changes the implementation
of the vqmovn_* intrinsics to use these RTL expressions rather than
a pair of unspecs. The redundant unspecs are removed along with their
code iterator.

gcc/ChangeLog:

2021-04-12  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Modify comment to
	make consistent with updated RTL pattern.
	* config/aarch64/aarch64-simd.md (aarch64_<sur>qmovn<mode>):
	Implement using ss_truncate and us_truncate rather than
	unspecs.
	* config/aarch64/iterators.md: Remove redundant unspecs and
	iterator: UNSPEC_[SU]QXTN and SUQMOVN respectively.
2021-04-28 21:14:03 +01:00
Jonathan Wright 6a82f012c4 aarch64: Update attributes of arm_acle.h intrinsics
Update the attributes of all intrinsics defined in arm_acle.h to be
consistent with the attributes of the intrinsics defined in
arm_neon.h. Specifically, this means updating the attributes from:
  __extension__ static __inline <type>
  __attribute__ ((__always_inline__))
to:
  __extension__ extern __inline <type>
  __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

gcc/ChangeLog:

2021-03-18  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/arm_acle.h (__attribute__): Make intrinsic
	attributes consistent with those defined in arm_neon.h.
2021-04-28 21:13:50 +01:00
Jonathan Wright 67cf12a817 aarch64: Update attributes of arm_fp16.h intrinsics
Update the attributes of all intrinsics defined in arm_fp16.h to be
consistent with the attributes of the intrinsics defined in
arm_neon.h. Specifically, this means updating the attributes from:
  __extension__ static __inline <type>
  __attribute__ ((__always_inline__))
to:
  __extension__ extern __inline <type>
  __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

gcc/ChangeLog:

2021-03-18  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/arm_fp16.h (__attribute__): Make intrinsic
	attributes consistent with those defined in arm_neon.h.
2021-04-28 21:13:37 +01:00
Jonathan Wright 8456a4cd96 aarch64: Use RTL builtins for vcvtx intrinsics
Rewrite vcvtx Neon intrinsics to use RTL builtins rather than inline
assembly code, allowing for better scheduling and optimization.

gcc/ChangeLog:

2021-02-18  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add
	float_trunc_rodd builtin generator macros.
	* config/aarch64/aarch64-simd.md (aarch64_float_trunc_rodd_df):
	Define.
	(aarch64_float_trunc_rodd_lo_v2sf): Define.
	(aarch64_float_trunc_rodd_hi_v4sf_le): Define.
	(aarch64_float_trunc_rodd_hi_v4sf_be): Define.
	(aarch64_float_trunc_rodd_hi_v4sf): Define.
	* config/aarch64/arm_neon.h (vcvtx_f32_f64): Use RTL builtin
	instead of inline asm.
	(vcvtx_high_f32_f64): Likewise.
	(vcvtxd_f32_f64): Likewise.
	* config/aarch64/iterators.md: Add FCVTXN unspec.
2021-04-28 21:13:23 +01:00
Jonathan Wright 4362c9c88d aarch64: Use RTL builtins for v[q]tbx intrinsics
Rewrite v[q]tbx Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-12  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add tbx1 builtin
	generator macros.
	* config/aarch64/aarch64-simd.md (aarch64_tbx1<mode>):
	Define.
	* config/aarch64/arm_neon.h (vqtbx1_s8): USE RTL builtin
	instead of inline asm.
	(vqtbx1_u8): Likewise.
	(vqtbx1_p8): Likewise.
	(vqtbx1q_s8): Likewise.
	(vqtbx1q_u8): Likewise.
	(vqtbx1q_p8): Likewise.
	(vtbx2_s8): Likewise.
	(vtbx2_u8): Likewise.
	(vtbx2_p8): Likewise.
2021-04-28 21:13:07 +01:00
Jonathan Wright ffb1122894 aarch64: Use RTL builtins for v[q]tbl intrinsics
Rewrite v[q]tbl Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-12  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add tbl1 builtin
	generator macros.
	* config/aarch64/arm_neon.h (vqtbl1_p8): Use RTL builtin
	instead of inline asm.
	(vqtbl1_s8): Likewise.
	(vqtbl1_u8): Likewise.
	(vqtbl1q_p8): Likewise.
	(vqtbl1q_s8): Likewise.
	(vqtbl1q_u8): Likewise.
	(vtbl1_s8): Likewise.
	(vtbl1_u8): Likewise.
	(vtbl1_p8): Likewise.
	(vtbl2_s8): Likewise.
	(vtbl2_u8): Likewise.
	(vtbl2_p8): Likewise.
2021-04-28 21:12:46 +01:00
Jonathan Wright 1d66367a71 aarch64: Use RTL builtins for polynomial vsri[q]_n intrinsics
Rewrite vsri[q]_n_p* Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-10  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add polynomial
	ssri_n buitin generator macro.
	* config/aarch64/arm_neon.h (vsri_n_p8): Use RTL builtin
	instead of inline asm.
	(vsri_n_p16): Likewise.
	(vsri_n_p64): Likewise.
	(vsriq_n_p8): Likewise.
	(vsriq_n_p16): Likewise.
	(vsriq_n_p64): Likewise.
2021-04-28 21:12:18 +01:00
Jonathan Wright 6372b05e5b aarch64: Use RTL builtins for polynomial vsli[q]_n intrinsics
Rewrite vsli[q]_n_p* Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-10  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Use VALLP mode
	iterator for polynomial ssli_n builtin generator macro.
	* config/aarch64/arm_neon.h (vsli_n_p8): Use RTL builtin
	instead of inline asm.
	(vsli_n_p16): Likewise.
	(vsliq_n_p8): Likewise.
	(vsliq_n_p16): Likewise.
	* config/aarch64/iterators.md: Define VALLP mode iterator.
2021-04-28 21:11:58 +01:00
Jonathan Wright 8e7f6e0395 aarch64: Use RTL builtins for vpadal_[su]32 intrinsics
Rewrite vpadal_[su]32 Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-09  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Use VDQV_L
	iterator to generate [su]adalp RTL builtins.
	* config/aarch64/aarch64-simd.md: Use VDQV_L iterator in
	[su]adalp RTL pattern.
	* config/aarch64/arm_neon.h (vpadal_s32): Use RTL builtin
	instead of inline asm.
	(vpadal_u32): Likewise.
2021-04-28 21:11:35 +01:00
Jonathan Wright fa18085a32 aarch64: Use RTL builtins for [su]paddl[q] intrinsics
Rewrite [su]paddl[q] Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add [su]addlp
	builtin generator macros.
	* config/aarch64/aarch64-simd.md (aarch64_<su>addlp<mode>):
	Define.
	* config/aarch64/arm_neon.h (vpaddl_s8): Use RTL builtin
	instead of inline asm.
	(vpaddl_s16): Likewise.
	(vpaddl_s32): Likewise.
	(vpaddl_u8): Likewise.
	(vpaddl_u16): Likewise.
	(vpaddl_u32): Likewise.
	(vpaddlq_s8): Likewise.
	(vpaddlq_s16): Likewise.
	(vpaddlq_s32): Likewise.
	(vpaddlq_u8): Likewise.
	(vpaddlq_u16): Likewise.
	(vpaddlq_u32): Liwewise.
	* config/aarch64/iterators.md: Define [SU]ADDLP unspecs with
	appropriate attributes.
2021-04-28 21:11:13 +01:00
Jonathan Wright eb2b36024c aarch64: Use RTL builtins for vpaddq intrinsics
Rewrite vpaddq Neon intrinsics to use RTL builtins rather than inline
assembly code, allowing for better scheduling and optimization.

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Use VDQ_I iterator
	for aarch64_addp<mode> builtin macro generator.
	* config/aarch64/aarch64-simd.md: Use VDQ_I iterator in
	aarch64_addp<mode> RTL pattern.
	* config/aarch64/arm_neon.h (vpaddq_s8): Use RTL builtin
	instead of inline asm.
	(vpaddq_s16): Likewise.
	(vpaddq_s32): Likewise.
	(vpaddq_s64): Likewise.
	(vpaddq_u8): Likewise.
	(vpaddq_u16): Likewise.
	(vpaddq_u32): Likewise.
	(vpaddq_u64): Likewise.
2021-04-28 21:10:58 +01:00
Jonathan Wright a53b8229e6 aarch64: Use RTL builtins for vq[r]dmulh[q]_n intrinsics
Rewrite vq[r]dmulh[q]_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add sq[r]dmulh_n
	builtin generator macros.
	* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_n<mode>):
	Define.
	* config/aarch64/arm_neon.h (vqdmulh_n_s16): Use RTL builtin
	instead of inline asm.
	(vqdmulh_n_s32): Likewise.
	(vqdmulhq_n_s16): Likewise.
	(vqdmulhq_n_s32): Likewise.
	(vqrdmulh_n_s16): Likewise.
	(vqrdmulh_n_s32): Likewise.
	(vqrdmulhq_n_s16): Likewise.
	(vqrdmulhq_n_s32): Likewise.
2021-04-28 21:10:41 +01:00
Joseph Myers a9cb8b6c1f Update gcc .po files.
* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
	ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
	zh_TW.po: Update.
2021-04-28 19:57:04 +00:00
Patrick McGehearty 54f0224d55 Practical improvement to libgcc complex divide
Correctness and performance test programs used during development of
this project may be found in the attachment to:
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg254210.html

Summary of Purpose

This patch to libgcc/libgcc2.c __divdc3 provides an
opportunity to gain important improvements to the quality of answers
for the default complex divide routine (half, float, double, extended,
long double precisions) when dealing with very large or very small exponents.

The current code correctly implements Smith's method (1962) [2]
further modified by c99's requirements for dealing with NaN (not a
number) results. When working with input values where the exponents
are greater than *_MAX_EXP/2 or less than -(*_MAX_EXP)/2, results are
substantially different from the answers provided by quad precision
more than 1% of the time. This error rate may be unacceptable for many
applications that cannot a priori restrict their computations to the
safe range. The proposed method reduces the frequency of
"substantially different" answers by more than 99% for double
precision at a modest cost of performance.

Differences between current gcc methods and the new method will be
described. Then accuracy and performance differences will be discussed.

Background

This project started with an investigation related to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59714.  Study of Beebe[1]
provided an overview of past and recent practice for computing complex
divide. The current glibc implementation is based on Robert Smith's
algorithm [2] from 1962.  A google search found the paper by Baudin
and Smith [3] (same Robert Smith) published in 2012. Elen Kalda's
proposed patch [4] is based on that paper.

I developed two sets of test data by randomly distributing values over
a restricted range and the full range of input values. The current
complex divide handled the restricted range well enough, but failed on
the full range more than 1% of the time. Baudin and Smith's primary
test for "ratio" equals zero reduced the cases with 16 or more error
bits by a factor of 5, but still left too many flawed answers. Adding
debug print out to cases with substantial errors allowed me to see the
intermediate calculations for test values that failed. I noted that
for many of the failures, "ratio" was a subnormal. Changing the
"ratio" test from check for zero to check for subnormal reduced the 16
bit error rate by another factor of 12. This single modified test
provides the greatest benefit for the least cost, but the percentage
of cases with greater than 16 bit errors (double precision data) is
still greater than 0.027% (2.7 in 10,000).

Continued examination of remaining errors and their intermediate
computations led to the various tests of input value tests and scaling
to avoid under/overflow. The current patch does not handle some of the
rare and most extreme combinations of input values, but the random
test data is only showing 1 case in 10 million that has an error of
greater than 12 bits. That case has 18 bits of error and is due to
subtraction cancellation. These results are significantly better
than the results reported by Baudin and Smith.

Support for half, float, double, extended, and long double precision
is included as all are handled with suitable preprocessor symbols in a
single source routine. Since half precision is computed with float
precision as per current libgcc practice, the enhanced algorithm
provides no benefit for half precision and would cost performance.
Further investigation showed changing the half precision algorithm
to use the simple formula (real=a*c+b*d imag=b*c-a*d) caused no
loss of precision and modest improvement in performance.

The existing constants for each precision:
float: FLT_MAX, FLT_MIN;
double: DBL_MAX, DBL_MIN;
extended and/or long double: LDBL_MAX, LDBL_MIN
are used for avoiding the more common overflow/underflow cases.  This
use is made generic by defining appropriate __LIBGCC2_* macros in
c-cppbuiltin.c.

Tests are added for when both parts of the denominator have exponents
small enough to allow shifting any subnormal values to normal values
all input values could be scaled up without risking overflow. That
gained a clear improvement in accuracy. Similarly, when either
numerator was subnormal and the other numerator and both denominator
values were not too large, scaling could be used to reduce risk of
computing with subnormals.  The test and scaling values used all fit
within the allowed exponent range for each precision required by the C
standard.

Float precision has more difficulty with getting correct answers than
double precision. When hardware for double precision floating point
operations is available, float precision is now handled in double
precision intermediate calculations with the simple algorithm the same
as the half-precision method of using float precision for intermediate
calculations. Using the higher precision yields exact results for all
tested input values (64-bit double, 32-bit float) with the only
performance cost being the requirement to convert the four input
values from float to double. If double precision hardware is not
available, then float complex divide will use the same improved
algorithm as the other precisions with similar change in performance.

Further Improvement

The most common remaining substantial errors are due to accuracy loss
when subtracting nearly equal values. This patch makes no attempt to
improve that situation.

NOTATION

For all of the following, the notation is:
Input complex values:
  a+bi  (a= real part, b= imaginary part)
  c+di
Output complex value:
  e+fi = (a+bi)/(c+di)

For the result tables:
current = current method (SMITH)
b1div = method proposed by Elen Kalda
b2div = alternate method considered by Elen Kalda
new = new method proposed by this patch

DESCRIPTIONS of different complex divide methods:

NAIVE COMPUTATION (-fcx-limited-range):
  e = (a*c + b*d)/(c*c + d*d)
  f = (b*c - a*d)/(c*c + d*d)

Note that c*c and d*d will overflow or underflow if either
c or d is outside the range 2^-538 to 2^512.

This method is available in gcc when the switch -fcx-limited-range is
used. That switch is also enabled by -ffast-math. Only one who has a
clear understanding of the maximum range of all intermediate values
generated by an application should consider using this switch.

SMITH's METHOD (current libgcc):
  if(fabs(c)<fabs(d) {
    r = c/d;
    denom = (c*r) + d;
    e = (a*r + b) / denom;
    f = (b*r - a) / denom;
  } else {
    r = d/c;
    denom = c + (d*r);
    e = (a + b*r) / denom;
    f = (b - a*r) / denom;
  }

Smith's method is the current default method available with __divdc3.

Elen Kalda's METHOD

Elen Kalda proposed a patch about a year ago, also based on Baudin and
Smith, but not including tests for subnormals:
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-08/msg01629.html [4]
It is compared here for accuracy with this patch.

This method applies the most significant part of the algorithm
proposed by Baudin&Smith (2012) in the paper "A Robust Complex
Division in Scilab" [3]. Elen's method also replaces two divides by
one divide and two multiplies due to the high cost of divide on
aarch64. In the comparison sections, this method will be labeled
b1div. A variation discussed in that patch which does not replace the
two divides will be labeled b2div.

  inline void improved_internal (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
  {
    r = d/c;
    t = 1.0 / (c + (d * r));
    if (r != 0) {
        x = (a + (b * r)) * t;
        y = (b - (a * r)) * t;
    }  else {
    /* Changing the order of operations avoids the underflow of r impacting
     the result. */
        x = (a + (d * (b / c))) * t;
        y = (b - (d * (a / c))) * t;
    }
  }

  if (FABS (d) < FABS (c)) {
      improved_internal (a, b, c, d);
  } else {
      improved_internal (b, a, d, c);
      y = -y;
  }

NEW METHOD (proposed by patch) to replace the current default method:

The proposed method starts with an algorithm proposed by Baudin&Smith
(2012) in the paper "A Robust Complex Division in Scilab" [3]. The
patch makes additional modifications to that method for further
reductions in the error rate. The following code shows the #define
values for double precision. See the patch for #define values used
for other precisions.

  #define RBIG ((DBL_MAX)/2.0)
  #define RMIN (DBL_MIN)
  #define RMIN2 (0x1.0p-53)
  #define RMINSCAL (0x1.0p+51)
  #define RMAX2  ((RBIG)*(RMIN2))

  if (FABS(c) < FABS(d)) {
  /* prevent overflow when arguments are near max representable */
  if ((FABS (d) > RBIG) || (FABS (a) > RBIG) || (FABS (b) > RBIG) ) {
      a = a * 0.5;
      b = b * 0.5;
      c = c * 0.5;
      d = d * 0.5;
  }
  /* minimize overflow/underflow issues when c and d are small */
  else if (FABS (d) < RMIN2) {
      a = a * RMINSCAL;
      b = b * RMINSCAL;
      c = c * RMINSCAL;
      d = d * RMINSCAL;
  }
  else {
    if(((FABS (a) < RMIN) && (FABS (b) < RMAX2) && (FABS (d) < RMAX2)) ||
       ((FABS (b) < RMIN) && (FABS (a) < RMAX2) && (FABS (d) < RMAX2))) {
        a = a * RMINSCAL;
        b = b * RMINSCAL;
        c = c * RMINSCAL;
        d = d * RMINSCAL;
    }
  }
  r = c/d; denom = (c*r) + d;
  if( r > RMIN ) {
      e = (a*r + b) / denom   ;
      f = (b*r - a) / denom
  } else {
      e = (c * (a/d) + b) / denom;
      f = (c * (b/d) - a) / denom;
  }
  }
[ only presenting the fabs(c) < fabs(d) case here, full code in patch. ]

Before any computation of the answer, the code checks for any input
values near maximum to allow down scaling to avoid overflow.  These
scalings almost never harm the accuracy since they are by 2. Values that
are over RBIG are relatively rare but it is easy to test for them and
allow aviodance of overflows.

Testing for RMIN2 reveals when both c and d are less than [FLT|DBL]_EPSILON.
By scaling all values by 1/EPSILON, the code converts subnormals to normals,
avoids loss of accuracy and underflows in intermediate computations
that otherwise might occur. If scaling a and b by 1/EPSILON causes either
to overflow, then the computation will overflow whatever method is used.

Finally, we test for either a or b being subnormal (RMIN) and if so,
for the other three values being small enough to allow scaling.  We
only need to test a single denominator value since we have already
determined which of c and d is larger.

Next, r (the ratio of c to d) is checked for being near zero. Baudin
and Smith checked r for zero. This code improves that approach by
checking for values less than DBL_MIN (subnormal) covers roughly 12
times as many cases and substantially improves overall accuracy. If r
is too small, then when it is used in a multiplication, there is a
high chance that the result will underflow to zero, losing significant
accuracy. That underflow is avoided by reordering the computation.
When r is subnormal, the code replaces a*r (= a*(c/d)) with ((a/d)*c)
which is mathematically the same but avoids the unnecessary underflow.

TEST Data

Two sets of data are presented to test these methods. Both sets
contain 10 million pairs of complex values.  The exponents and
mantissas are generated using multiple calls to random() and then
combining the results. Only values which give results to complex
divide that are representable in the appropriate precision after
being computed in quad precision are used.

The first data set is labeled "moderate exponents".
The exponent range is limited to -DBL_MAX_EXP/2 to DBL_MAX_EXP/2
for Double Precision (use FLT_MAX_EXP or LDBL_MAX_EXP for the
appropriate precisions.
The second data set is labeled "full exponents".
The exponent range for these cases is the full exponent range
including subnormals for a given precision.

ACCURACY Test results:

Note: The following accuracy tests are based on IEEE-754 arithmetic.

Note: All results reporteed are based on use of fused multiply-add. If
fused multiply-add is not used, the error rate increases, giving more
1 and 2 bit errors for both current and new complex divide.
Differences between using fused multiply and not using it that are
greater than 2 bits are less than 1 in a million.

The complex divide methods are evaluated by determining the percentage
of values that exceed differences in low order bits.  If a "2 bit"
test results show 1%, that would mean that 1% of 10,000,000 values
(100,000) have either a real or imaginary part that differs from the
quad precision result by more than the last 2 bits.

Results are reported for differences greater than or equal to 1 bit, 2
bits, 8 bits, 16 bits, 24 bits, and 52 bits for double precision.  Even
when the patch avoids overflows and underflows, some input values are
expected to have errors due to the potential for catastrophic roundoff
from floating point subtraction. For example, when b*c and a*d are
nearly equal, the result of subtraction may lose several places of
accuracy. This patch does not attempt to detect or minimize this type
of error, but neither does it increase them.

I only show the results for Elen Kalda's method (with both 1 and
2 divides) and the new method for only 1 divide in the double
precision table.

In the following charts, lower values are better.

current - current complex divide in libgcc
b1div - Elen Kalda's method from Baudin & Smith with one divide
b2div - Elen Kalda's method from Baudin & Smith with two divides
new   - This patch which uses 2 divides

===================================================
Errors   Moderate Dataset
gtr eq     current    b1div      b2div        new
======    ========   ========   ========   ========
 1 bit    0.24707%   0.92986%   0.24707%   0.24707%
 2 bits   0.01762%   0.01770%   0.01762%   0.01762%
 8 bits   0.00026%   0.00026%   0.00026%   0.00026%
16 bits   0.00000%   0.00000%   0.00000%   0.00000%
24 bits         0%         0%         0%         0%
52 bits         0%         0%         0%         0%
===================================================
Table 1: Errors with Moderate Dataset (Double Precision)

Note in Table 1 that both the old and new methods give identical error
rates for data with moderate exponents. Errors exceeding 16 bits are
exceedingly rare. There are substantial increases in the 1 bit error
rates for b1div (the 1 divide/2 multiplys method) as compared to b2div
(the 2 divides method). These differences are minimal for 2 bits and
larger error measurements.

===================================================
Errors   Full Dataset
gtr eq     current    b1div      b2div        new
======    ========   ========   ========   ========
 1 bit      2.05%   1.23842%    0.67130%   0.16664%
 2 bits     1.88%   0.51615%    0.50354%   0.00900%
 8 bits     1.77%   0.42856%    0.42168%   0.00011%
16 bits     1.63%   0.33840%    0.32879%   0.00001%
24 bits     1.51%   0.25583%    0.24405%   0.00000%
52 bits     1.13%   0.01886%    0.00350%   0.00000%
===================================================
Table 2: Errors with Full Dataset (Double Precision)

Table 2 shows significant differences in error rates. First, the
difference between b1div and b2div show a significantly higher error
rate for the b1div method both for single bit errros and well
beyond. Even for 52 bits, we see the b1div method gets completely
wrong answers more than 5 times as often as b2div. To retain
comparable accuracy with current complex divide results for small
exponents and due to the increase in errors for large exponents, I
choose to use the more accurate method of two divides.

The current method has more 1.6% of cases where it is getting results
where the low 24 bits of the mantissa differ from the correct
answer. More than 1.1% of cases where the answer is completely wrong.
The new method shows less than one case in 10,000 with greater than
two bits of error and only one case in 10 million with greater than
16 bits of errors. The new patch reduces 8 bit errors by
a factor of 16,000 and virtually eliminates completely wrong
answers.

As noted above, for architectures with double precision
hardware, the new method uses that hardware for the
intermediate calculations before returning the
result in float precision. Testing of the new patch
has shown zero errors found as seen in Tables 3 and 4.

Correctness for float
=============================
Errors   Moderate Dataset
gtr eq     current     new
======    ========   ========
 1 bit   28.68070%         0%
 2 bits   0.64386%         0%
 8 bits   0.00401%         0%
16 bits   0.00001%         0%
24 bits         0%         0%
=============================
Table 3: Errors with Moderate Dataset (float)

=============================
Errors   Full Dataset
gtr eq     current     new
======    ========   ========
 1 bit     19.98%         0%
 2 bits     3.20%         0%
 8 bits     1.97%         0%
16 bits     1.08%         0%
24 bits     0.55%         0%
=============================
Table 4: Errors with Full Dataset (float)

As before, the current method shows an troubling rate of extreme
errors.

There very minor changes in accuracy for half-precision since the code
changes from Smith's method to the simple method. 5 out of 1 million
test cases show correct answers instead of 1 or 2 bit errors.
libgcc computes half-precision functions in float precision
allowing the existing methods to avoid overflow/underflow issues
for the allowed range of exponents for half-precision.

Extended precision (using x87 80-bit format on x86) and Long double
(using IEEE-754 128-bit on x86 and aarch64) both have 15-bit exponents
as compared to 11-bit exponents in double precision. We note that the
C standard also allows Long Double to be implemented in the equivalent
range of Double. The RMIN2 and RMINSCAL constants are selected to work
within the Double range as well as with extended and 128-bit ranges.
We will limit our performance and accurancy discussions to the 80-bit
and 128-bit formats as seen on x86 here.

The extended and long double precision investigations were more
limited. Aarch64 does not support extended precision but does support
the software implementation of 128-bit long double precision. For x86,
long double defaults to the 80-bit precision but using the
-mlong-double-128 flag switches to using the software implementation
of 128-bit precision. Both 80-bit and 128-bit precisions have the same
exponent range, with the 128-bit precision has extended mantissas.
Since this change is only aimed at avoiding underflow/overflow for
extreme exponents, I studied the extended precision results on x86 for
100,000 values. The limited exponent dataset showed no differences.
For the dataset with full exponent range, the current and new values
showed major differences (greater than 32 bits) in 567 cases out of
100,000 (0.56%). In every one of these cases, the ratio of c/d or d/c
(as appropriate) was zero or subnormal, indicating the advantage of
the new method and its continued correctness where needed.

PERFORMANCE Test results

In order for a library change to be practical, it is necessary to show
the slowdown is tolerable. The slowdowns observed are much less than
would be seen by (for example) switching from hardware double precison
to a software quad precision, which on the tested machines causes a
slowdown of around 100x).

The actual slowdown depends on the machine architecture. It also
depends on the nature of the input data. If underflow/overflow is
rare, then implementations that have strong branch prediction will
only slowdown by a few cycles. If underflow/overflow is common, then
the branch predictors will be less accurate and the cost will be
higher.

Results from two machines are presented as examples of the overhead
for the new method. The one labeled x86 is a 5 year old Intel x86
processor and the one labeled aarch64 is a 3 year old arm64 processor.

In the following chart, the times are averaged over a one million
value data set. All values are scaled to set the time of the current
method to be 1.0. Lower values are better. A value of less than 1.0
would be faster than the current method and a value greater than 1.0
would be slower than the current method.

================================================
               Moderate set          full set
               x86  aarch64        x86  aarch64
========     ===============     ===============
float         0.59    0.79        0.45    0.81
double        1.04    1.24        1.38    1.56
long double   1.13    1.24        1.29    1.25
================================================
Table 5: Performance Comparisons (ratio new/current)

The above tables omit the timing for the 1 divide and 2 multiply
comparison with the 2 divide approach.

The float results show clear performance improvement due to using the
simple method with double precision for intermediate calculations.

The double results with the newer method show less overhead for the
moderate dataset than for the full dataset. That's because the moderate
dataset does not ever take the new branches which protect from
under/overflow. The better the branch predictor, the lower the cost
for these untaken branches. Both platforms are somewhat dated, with
the x86 having a better branch predictor which reduces the cost of the
additional branches in the new code. Of course, the relative slowdown
may be greater for some architectures, especially those with limited
branch prediction combined with a high cost of misprediction.

The long double results are fairly consistent in showing the moderate
additional cost of the extra branches and calculations for all cases.

The observed cost for all precisions is claimed to be tolerable on the
grounds that:

(a) the cost is worthwhile considering the accuracy improvement shown.
(b) most applications will only spend a small fraction of their time
    calculating complex divide.
(c) it is much less than the cost of extended precision
(d) users are not forced to use it (as described below)

Those users who find this degree of slowdown unsatisfactory may use
the gcc switch -fcx-fortran-rules which does not use the library
routine, instead inlining Smith's method without the C99 requirement
for dealing with NaN results. The proposed patch for libgcc complex
divide does not affect the code generated by -fcx-fortran-rules.

SUMMARY

When input data to complex divide has exponents whose absolute value
is less than half of *_MAX_EXP, this patch makes no changes in
accuracy and has only a modest effect on performance.  When input data
contains values outside those ranges, the patch eliminates more than
99.9% of major errors with a tolerable cost in performance.

In comparison to Elen Kalda's method, this patch introduces more
performance overhead but reduces major errors by a factor of
greater than 4000.

REFERENCES

[1] Nelson H.F. Beebe, "The Mathematical-Function Computation Handbook.
Springer International Publishing AG, 2017.

[2] Robert L. Smith. Algorithm 116: Complex division.  Commun. ACM,
 5(8):435, 1962.

[3] Michael Baudin and Robert L. Smith. "A robust complex division in
Scilab," October 2012, available at http://arxiv.org/abs/1210.4539.

[4] Elen Kalda: Complex division improvements in libgcc
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-08/msg01629.html

2020-12-08  Patrick McGehearty  <patrick.mcgehearty@oracle.com>

gcc/c-family/
	* c-cppbuiltin.c (c_cpp_builtins): Add supporting macros for new
	complex divide
libgcc/
	* libgcc2.c (XMTYPE, XCTYPE, RBIG, RMIN, RMIN2, RMINSCAL, RMAX2):
	Define.
	(__divsc3, __divdc3, __divxc3, __divtc3): Improve complex divide.
	* config/rs6000/_divkc3.c (RBIG, RMIN, RMIN2, RMINSCAL, RMAX2):
	Define.
	(__divkc3): Improve complex divide.
gcc/testsuite/
	* gcc.c-torture/execute/ieee/cdivchkd.c: New test.
	* gcc.c-torture/execute/ieee/cdivchkf.c: Likewise.
	* gcc.c-torture/execute/ieee/cdivchkld.c: Likewise.
2021-04-28 21:54:44 +02:00
Tobias Burnus 4c84c45d8a doc/install.texi: Document --enable-offload-defaulted config option
Document configure --enable-offload-defaulted option added in
commit r12-218-gfe5bfa6704179f8db7d1ae0b485439e9896df8eb

gcc/ChangeLog:

	* doc/install.texi (--enable-offload-defaulted): Document.
2021-04-28 21:15:16 +02:00
Senthil Kumar Selvaraj 3ba781d3b5 AVR cc0 conversion
See https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html
for background.

This patch converts the avr backend to MODE_CC. It addresses some of
the comments made in the previous submission over here
(https://gcc.gnu.org/pipermail/gcc-patches/2020-December/561757.html).

Specifically, this patch has

1. Automatic clobber of REG_CC in inline asm statements, via
TARGET_MD_ASM_ADJUST hook.

2. Direct clobber of REG_CC in insns emitted after reload (pro and
epilogue).

3. Regression testing done on atmega8, atmega128, attiny40 and
atxmega128a3 devices (more details below).

4. Verification and fixes for casesi and avr_compare_pattern related
code that inspects insns, by looking at avr-casesi and mach RTL dumps.

5. Use length of parallel instead of passing in operand counts when
generating code for shift patterns.

6. Fixes for indentation glitches.

7. Removal of CC_xxx stuff in avr-protos.h. In the places where the
macros were still used (cond_string), I've replaced them with a bool
hardcoded to false. I expect this will go away/get fixed when I
eventually add specific CC modes.

Things still to do:

1. Adjustment of peepholes/define_splits to match against patterns
   with REG_CC clobber.
2. Model effect of non-compare insns on REG_CC using additional CC
   modes. I'm hoping to use of a modified version of the cc attribute
   and define_subst (again inspired by the cris port), to do this.
3. RTX cost adjustment.

gcc/
	* config/avr/avr-dimode.md: Turn existing patterns into
	define_insn_and_split style patterns where the splitter
	adds a clobber of the condition code register.  Drop "cc"
	attribute.  Add new patterns to match output of
	the splitters.
	* config/avr/avr-fixed.md: Likewise.
	* config/avr/avr.c (cc_reg_rtx): New.
	(avr_parallel_insn_from_insns): Adjust insn count
	for removal of set of cc0.
	(avr_is_casesi_sequence): Likewise.
	(avr_casei_sequence_check_operands): Likewise.
	(avr_optimize_casesi): Likewise. Also insert
	new insns after jump_insn.
	(avr_pass_casesi::avr_rest_of_handle_casesi): Adjust
	for removal of set of cc0.
	(avr_init_expanders): Initialize cc_reg_rtx.
	(avr_regno_reg_class): Handle REG_CC.
	(cond_string): Remove usage of CC_OVERFLOW_UNUSABLE.
	(avr_notice_update_cc): Remove function.
	(ret_cond_branch): Remove usage of CC_OVERFLOW_UNUSABLE.
	(compare_condition): Adjust for PARALLEL with
	REG_CC clobber.
	(out_shift_with_cnt): Likewise.
	(ashlhi3_out): Likewise.
	(ashrhi3_out): Likewise.
	(lshrhi3_out): Likewise.
	(avr_class_max_nregs): Return single reg for REG_CC.
	(avr_compare_pattern): Check for REG_CC instead
	of cc0_rtx.
	(avr_reorg_remove_redundant_compare): Likewise.
	(avr_reorg):Adjust for PARALLEL with REG_CC clobber.
	(avr_hard_regno_nregs): Return single reg for REG_CC.
	(avr_hard_regno_mode_ok): Allow only CCmode for REG_CC.
	(avr_md_asm_adjust): Clobber REG_CC.
	(TARGET_HARD_REGNO_NREGS): Define.
	(TARGET_CLASS_MAX_NREGS): Define.
	(TARGET_MD_ASM_ADJUST): Define.
	* config/avr/avr.h (FIRST_PSEUDO_REGISTER): Adjust
	for REG_CC.
	(enum reg_class): Add CC_REG class.
	(NOTICE_UPDATE_CC): Remove.
	(CC_OVERFLOW_UNUSABLE): Remove.
	(CC_NO_CARRY): Remove.
	* config/avr/avr.md: Turn existing patterns into
	define_insn_and_split style patterns where the splitter
	adds a clobber of the condition code register.  Drop "cc"
	attribute.  Add new patterns to match output of
	the splitters.
	(sez): Remove unused pattern.
2021-04-28 17:42:01 +00:00
Jonathan Wakely c8767ee9f9 libstdc++: Add testcase for std::pair as a structural type [PR 97930]
This PR was fixed by r12-221-ge1543e694dadf1ea70eb72325219bc0cdc914a35
(for compilers that support C++20 Concepts) so this adds the testcase.

libstdc++-v3/ChangeLog:

	PR libstdc++/97930
	* testsuite/20_util/pair/requirements/structural.cc: New test.
2021-04-28 18:17:40 +01:00
Alexandre Oliva da4a0817be omit frame pointer in pr89676
This i386 test expects only two movl instructions.

In configurations that --enable-frame-pointer, -O2 won't implicitly
enable -fomit-frame-pointer, so we end up with a third movl to set up
the frame pointer.

This patch enables -fomit-frame-pointer explicitly, so that the result
no longer depends on that configuration option.


for  gcc/testsuite/ChangeLog

	* gcc.target/i386/pr89676.c: Add -fomit-frame-pointer.
2021-04-28 14:08:48 -03:00
Alexandre Oliva 16683cefc6 fix asm-not pattern in dwarf2/inline5.c
The test is supposed to check that the abstract lexical block of a
function that was inlined doesn't have attributes, and that the
concrete inlined lexical block does.

There are two patterns to verify the absence of attributes in the
abstract lexical block, one for the case in which the concrete block
appears after the abstract one, and another for the case in which it's
before.

The former has a problem that is not visible when asm comments start
with a single character, but that becomes apparent when they start
with "/ ".

The pattern starts by matching the abstract DW_TAG_lexical_block DIE
header, and checking that the next line has, after any of the
comment-starter characters (e.g. '/'), there are one or more blanks '
+', and then a character other than the '(' that would start another
DIE.

The problem is that '[.../...]+ +[^(].*' matches '/  (DIE...', because
'[^(]' may match the second blank, and after that anything goes.  So
we end up recognizing the pattern, as if it was an abstract lexical
block with an attribute.

This could be minimally fixed by changing '[^(]' to '[^ (]', but the
pattern that matches concrete before abstract checks for an explicit
DW_AT after the abstract DIE, so I'm using that in the other pattern
as well.

For reference, the lines that start the unwanted match are:
	.uleb128 0xc	/  (DIE (0xa4) DW_TAG_lexical_block)
	.uleb128 0xd	/  (DIE (0xa5) DW_TAG_variable)


for  gcc/testsuite/ChangeLog

	* gcc.dg/debug/dwarf2/inline5.c: Adjust pattern to avoid
	mismatch when asm comments start with "/ ".
2021-04-28 14:07:41 -03:00
Richard Earnshaw 59f5d16f2c arm: fix UB due to missing mode check [PR100311]
Some places in the compiler iterate over all the fixed registers to
check if that register can be used in a particular mode.  The idiom is
to iterate over the register and then for that register, if it
supports the current mode to check all that register and any
additional registers needed (HARD_REGNO_NREGS).  If these two checks
are not fully aligned then it is possible to generate a buffer overrun
when testing data objects that are sized by the number of hard regs in
the machine.

The VPR register is a case where these checks were not consistent and
because this is the last HARD register the result was that we ended up
overflowing the fixed_regs array.

gcc:
	PR target/100311
	* config/arm/arm.c (arm_hard_regno_mode_ok): Only allow VPR to be
	used in HImode.
2021-04-28 17:57:57 +01:00
Jonathan Wakely e1543e694d libstdc++: Simplify std::pair constraints using concepts
This re-implements the constraints on the std::pair constructors and
assignment operators in C++20 mode, to use concepts.

The non-standard constructors deprecated for PR 99957 are no longer
supported in C++20 mode, which requires some minor testsuite changes.
Otherwise all tests pass in C++20 mode.

libstdc++-v3/ChangeLog:

	* include/bits/stl_pair.h (pair) [__cplusplus > 202002]: Add
	new definitions for constructors and assignment operators using
	concepts for constraints.
	* testsuite/20_util/pair/cons/99957.cc: Disable for C++20 and
	later.
	* testsuite/20_util/pair/cons/explicit_construct.cc: Adjust
	expected error messages to also match C++20 errors.
2021-04-28 17:56:51 +01:00
Jonathan Wakely d96db15967 libstdc++: Deprecate non-standard std::pair constructors [PR 99957]
This deprecates the non-standard std::pair constructors that support
construction from an rvalue and a literal zero used as a null pointer
constant. We can't just add the deprecated attribute to those
constructors, because they're currently used by correct code when they
are a better match than the constructors required by the standard e.g.

  int i = 0;
  const int j = 0;
  std::pair<int, int> p(i, j); // uses pair(U1&&, const int&)

This patch adjusts the parameter types and constraints of those
constructors so that they only get used for literal zeros, and the
pair(U1&&, U2&&) constructor gets used otherwise. Once they're only used
for initializations that should be ill-formed we can add the deprecated
attribute.

The deprecated attribute is used to suggest that the user code uses
nullptr, which avoids the problem of 0 deducing as int instead of a null
pointer constant.

libstdc++-v3/ChangeLog:

	PR libstdc++/99957
	* include/bits/stl_pair.h (_PCC::_MoveCopyPair, _PCC::_CopyMovePair):
	Combine and replace with ...
	(_PCC::_DeprConsPair): New SFINAE helper function.
	(pair): Merge preprocessor blocks so that all C++03 members
	are defined together at the end.
	(pair::pair(const _T1&, _U2&&), pair::pair(_U1&&, const _T2&)):
	Replace _T1 and _T2 parameters with __null_ptr_constant and
	adjust constraints.
	* testsuite/20_util/pair/40925.cc: Use nullptr instead of 0.
	* testsuite/20_util/pair/cons/explicit_construct.cc: Likewise.
	* testsuite/20_util/pair/cons/99957.cc: New test.
2021-04-28 17:56:50 +01:00
Richard Sandiford 668df9e769 aarch64: Fix address mode for vec_concat pattern [PR100305]
The load_pair_lanes<mode> patterns match a vec_concat of two
adjacent 64-bit memory locations as a single 128-bit load.
The Utq constraint made sure that the address was suitable
for a 128-bit vector, but this meant that it allowed some
addresses that aren't valid for the 64-bit element mode.

Two obvious fixes were:

(1) Continue to accept addresses that aren't valid for the element
    modes.  This would mean changing the mode of operands[1] before
    printing it.  It would also mean using a custom predicate instead
    of the current memory_operand.

(2) Restrict addresses to the intersection of those that are valid
    element and vector addresses.

The problem with (1) is that, as well as being more complicated,
it doesn't deal with the fact that we still have a memory_operand
for the second element.  If we encourage the first operand to be
outside the range of a normal element memory_operand, we'll have
to reload the second operand to make it valid.  This reload will
often be dead code, but will be kept around because the RTL
pattern makes it look as though the second element address
is still needed.

This patch therefore does (2) instead.

As mentioned in the PR notes, I think we have a general problem
with the way that the aarch64 port deals with paired addresses.
There's nothing to guarantee that the two addresses will be
reloaded in a way that keeps them “obviously” adjacent, so the
rtx_equal_p conditions could fail if something rechecked them
later.

For this particular pattern, I think it would be better to teach
simplify-rtx.c to fold the vec_concat to a normal vector memory
reference, to remove any suggestion that targets should try to
match the unsimplified form.  That obviously wouldn't be suitable
for backports though.

gcc/
	PR target/100305
	* config/aarch64/constraints.md (Utq): Require the address to
	be valid for both the element mode and for V2DImode.

gcc/testsuite/
	PR target/100305
	* gcc.c-torture/compile/pr100305.c: New test.
2021-04-28 17:54:52 +01:00
Tobias Burnus fe5bfa6704 offload-defaulted: Config option to silently ignore uninstalled offload compilers
If configured with --enable-offload-defaulted, configured but not installed
offload compilers and libgomp plugins are silently ignored.  Useful for
distribution compilers where those are in separate optional packages.

2021-04-28  Jakub Jelinek  <jakub@redhat.com>
	    Tobias Burnus  <tobias@codesourcery.com>

ChangeLog:

	* configure.ac (--enable-offload-defaulted): New.
	* configure: Regenerate.

gcc/ChangeLog:

	* configure.ac (OFFLOAD_DEFAULTED): AC_DEFINE if offload-defaulted.
	* gcc.c (process_command): New variable.
	(driver::maybe_putenv_OFFLOAD_TARGETS): If OFFLOAD_DEFAULTED,
	set it if -foffload is defaulted.
	* lto-wrapper.c (OFFLOAD_TARGET_DEFAULT_ENV): Define.
	(compile_offload_image): If OFFLOAD_DEFAULTED and
	OFFLOAD_TARGET_DEFAULT is in the environment, don't fail
	if corresponding mkoffload can't be found.
	(compile_images_for_offload_targets): Likewise.  Free and clear
	offload_names if no valid offload is found.
	* config.in: Regenerate.
	* configure: Regenerate.

libgomp/ChangeLog:

	* configure.ac (OFFLOAD_DEFAULTED): AC_DEFINE if offload-defaulted.
	* target.c (gomp_load_plugin_for_device): If set and if a plugin
	can't be dlopened, silently assume it has no devices.
	* Makefile.in: Regenerate.
	* config.h.in: Regenerate.
	* configure: Regenerate.
2021-04-28 18:46:47 +02:00
Jonathan Wakely 3da80ed7ef libstdc++: Define __cpp_lib_constexpr_string macro
As noted in r11-1339-gb6ab9ecd550227684643b41e9e33a4d3466724d8 we define
a non-standard __cpp_lib_constexpr_char_traits feature test macro to
indicate support for P0426R1 and P1032R1. At some point last year the
__cpp_lib_constexpr_string macro was retconned to indicate support for
those papers. This adds the new macro (which we didn't previously
define, because it referred to P0980R1 "Making std::string constexpr"
which we don't support).

libstdc++-v3/ChangeLog:

	* include/bits/basic_string.h (__cpp_lib_constexpr_string): Define.
	* include/std/version (__cpp_lib_constexpr_string): Define.
	* testsuite/21_strings/char_traits/requirements/constexpr_functions_c++17.cc:
	Check for __cpp_lib_constexpr_string.
	* testsuite/21_strings/char_traits/requirements/constexpr_functions_c++20.cc:
	Likewise.
	* testsuite/21_strings/char_traits/requirements/version.cc: New test.
2021-04-28 15:56:04 +01:00
Jonathan Wakely 43a35b26e2 libstdc++: Reduce output of 'make doc-pdf-doxygen'
Use '@' to prevent Make from echoing the recipe, so that users don't see
this every time:

  if [ -f ${doxygen_pdf} ]; then
    mv ${doxygen_pdf} ${api_pdf} ;
    echo ":: PDF file is ${api_pdf}";
  else
    echo "... error";
    grep -F 'LaTeX Error' ${doxygen_outdir}/latex/refman.log;
    grep -F 'TeX capacity exceeded, sorry' ${doxygen_outdir}/latex/refman.log;
    exit 12;
  fi

The presence of the "error" strings in the output makes it look like an
error happened. By suppressing the echoing user's will only see "error"
if the 'else' branch is taken.

libstdc++-v3/ChangeLog:

	* doc/Makefile.am (stamp-pdf-doxygen): Improve comment about
	dealing with errors. Use '@' to prevent shell command being
	echoed.
	* doc/Makefile.in: Regenerate.
2021-04-28 14:49:28 +01:00
Jonathan Wakely 5cc28000cf libstdc++: Add missing noexcept on std::thread member function [PR 100298]
The new inline definition of std:🧵:hardware_concurrency() for
non-gthreads targets is missing the noexcept-specifier that is on the
declaration.

libstdc++-v3/ChangeLog:

	PR libstdc++/100298
	* include/bits/std_thread.h (thread::hardware_concurrency): Add
	missing noexcept to inline definition for non-gthreads targets.
2021-04-28 12:45:49 +01:00
José Rui Faustino de Sousa b020cee5af Fortran: Fix double function call with -fcheck=pointer [PR]
gcc/fortran/ChangeLog:

	PR fortran/82376
	* trans-expr.c (gfc_conv_procedure_call): Evaluate function result
	and then pass a pointer.

gcc/testsuite/ChangeLog:

	PR fortran/82376
	* gfortran.dg/PR82376.f90: New test.
2021-04-28 11:20:25 +00:00
Jakub Jelinek ea3d2e3c16 c++: Remove #error for release builds
* module.cc: Remove #error that triggers if DEV-PHASE is empty.
2021-04-28 13:05:04 +02:00
Richard Biener f7ee6a1e8a tree-optimization/100292 - avoid invalid GIMPLE from vector lowering
We have to avoid folding the condition when building a COND_EXPR
since we no longer gimplify the whole thing.  The folding done
at COND_EXPR build time will deal with possible simplifications.

2021-04-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/100292
	* tree-vect-generic.c (expand_vector_condition): Do not fold
	the comparisons.

	* gcc.dg/pr100292.c: New testcase.
2021-04-28 12:03:49 +02:00
Piotr Trojanek f9d670128f [Ada] Style fixes related to calls to List_Length
gcc/ada/

	* sem_ch13.adb, sem_util.adb: Fix style.
2021-04-28 05:38:20 -04:00
Piotr Trojanek ba344f1ba6 [Ada] Adjust List_Length description
gcc/ada/

	* nlists.ads (List_Length): Adapt comment to match the
	behaviour.
2021-04-28 05:38:19 -04:00
Arnaud Charlet 5485d0e556 [Ada] Fix recent optimization in evaluation of selected component for GNATprove
gcc/ada/

	* sem_eval.adb (Eval_Selected_Component): Only consider compile
	time known aggregates.
2021-04-28 05:38:18 -04:00
Eric Botcazou 4e60fea920 [Ada] Fix computation of Prec/Succ of zero without denormals
gcc/ada/

	* libgnat/s-fatgen.adb: Add use clause for Interfaces.Unsigned_16
	and Interfaces.Unsigned_32.
	(Small16): New constant.
	(Small32): Likewise.
	(Small64): Likewise.
	(Small80): Likewise.
	(Pred): Declare a local overlay for Small and return it negated
	for zero if the type does not support denormalized numbers.
	(Succ): Likewise, but return it directly.
2021-04-28 05:38:17 -04:00
Piotr Trojanek 33d1be8739 [Ada] Remove redundant assignment in Formal_Is_Used_Once
gcc/ada/

	* inline.adb (Formal_Is_Used_Once): Refine type of the counter
	variable; remove redundant assignment.
2021-04-28 05:38:16 -04:00
Patrick Bernardi bed6154a5a [Ada] Install_Restricted_Handlers: define Prio parameter as Interrupt_Priority
gcc/ada/

	* libgnarl/s-interr.adb (Install_Restricted_Handlers): Change
	Prio parameter to type Interrupt_Priority.
	* libgnarl/s-interr.ads (Install_Restricted_Handlers): Likewise.
	* libgnarl/s-interr__dummy.adb (Install_Restricted_Handlers):
	Likewise.
	* libgnarl/s-interr__hwint.adb (Install_Restricted_Handlers):
	Likewise.
	* libgnarl/s-interr__sigaction.adb (Install_Restricted_Handlers):
	Likewise.
	* libgnarl/s-interr__vxworks.adb (Install_Restricted_Handlers):
	Likewise.
2021-04-28 05:38:15 -04:00
Piotr Trojanek 894376c44d [Ada] Simplify data structures for overloaded interpretations
gcc/ada/

	* sem_type.ads (Write_Interp_Ref): Removed; no longer needed.
	* sem_type.adb (Headers): Removed; now the hash table is
	directly in the Interp_Map alone.
	(Interp_Map): Now an instance of the GNAT.HTable.Simple_HTable.
	(Last_Overloaded): New variable to emulate Interp_Map.Last.
	(Add_One_Interp): Adapt to new data structure.
	(Get_First_Interp): Likewise.
	(Hash): Likewise.
	(Init_Interp_Tables): Likewise.
	(New_Interps): Likewise.
	(Save_Interps): Likewise; handle O_N variable like in
	Get_First_Interp.
	(Write_Interp_Ref): Removed; no longer needed.
2021-04-28 05:38:15 -04:00
Piotr Trojanek f358e5c177 [Ada] Replace dubious use of Traverse_Func with Traverse_Proc
gcc/ada/

	* inline.adb (Do_Reset_Calls): Now an instance of Traverse_Proc.
2021-04-28 05:38:14 -04:00
Piotr Trojanek 88fd22e721 [Ada] Consistent diagnostic on missing -gnat2020 switch for aspects
gcc/ada/

	* sem_ch13.adb (Analyze_Aspect_Static): Reuse
	Error_Msg_Ada_2020_Feature for aspect Static.
	(Analyze_One_Aspect): Likewise for aspect Full_Access.
2021-04-28 05:38:13 -04:00
Piotr Trojanek 189c58042d [Ada] Refactor repeated checks for the expression of aspect Static
gcc/ada/

	* sem_ch13.adb (Analyze_Aspect_Static): Refactor to have a
	single check for the expression being present; adapt comments.
2021-04-28 05:38:12 -04:00
Piotr Trojanek 12e67086ad [Ada] More precise error about aspects conflicting with Static
gcc/ada/

	* sem_ch13.adb (Analyze_Aspect_Static): Use aspect name in the
	error message.
2021-04-28 05:38:11 -04:00
Piotr Trojanek 43d5138227 [Ada] Simplify folding of selected components with qualified prefixes
gcc/ada/

	* sem_eval.adb (Eval_Selected_Component): Simplify with
	Unqualify.
2021-04-28 05:38:10 -04:00
Eric Botcazou 35e3a1f670 [Ada] Eliminate early roundoff error for Long_Long_Float on x86
gcc/ada/

	* libgnat/s-valrea.adb (Fast2Sum): New function.
	(Integer_to_Real): Use it in an iterated addition with exact
	error handling for the case where an extra digit is needed.
	Move local variable now only used in the exponentiation case.
2021-04-28 05:38:09 -04:00
Yannick Moy 9d5f3b7a69 [Ada] Use spans instead of locations for compiler diagnostics
gcc/ada/

	* errout.adb: (Error_Msg_Internal): Use span instead of
	location.
	(Error_Msg, Error_Msg_NEL): Add versions with span parameter.
	(Error_Msg_F, Error_Msg_FE, Error_Msg_N, Error_Msg_NE,
	Error_Msg_NW): Retrieve span from node.
	(First_Node): Use the new First_And_Last_Nodes.
	(First_And_Last_Nodes): Expand on previous First_Node. Apply to
	other nodes than expressions.
	(First_Sloc): Protect against inconsistent locations.
	(Last_Node): New function based on First_And_Last_Nodes.
	(Last_Sloc): New function similar to First_Sloc.
	(Output_Messages): Update output when -gnatdF is used. Use
	character ~ for making the span visible, similar to what is done
	in GCC and Clang.
	* errout.ads (Error_Msg, Error_Msg_NEL): Add versions with span
	parameter.
	(First_And_Last_Nodes, Last_Node, Last_Sloc): New subprograms.
	* erroutc.adb: Adapt to Sptr field being a span.
	* erroutc.ads (Error_Msg_Object): Change field Sptr from
	location to span.
	* errutil.adb: Adapt to Sptr field being a span.
	* freeze.adb: Use Errout reporting procedures for nodes to get
	spans.
	* par-ch3.adb: Likewise.
	* par-prag.adb: Likewise.
	* par-util.adb: Likewise.
	* sem_case.adb: Likewise.
	* sem_ch13.adb: Likewise.
	* sem_ch3.adb: Likewise.
	* sem_prag.adb: Likewise.
	* types.ads: (Source_Span): New type for spans.
	(To_Span): Basic constructors for spans.
2021-04-28 05:38:08 -04:00
Arnaud Charlet ae77b299e9 [Ada] Assert failure on complex code with private type and discriminant
gcc/ada/

	* einfo.adb (Discriminant_Constraint): Refine assertion.
2021-04-28 05:38:07 -04:00
Gary Dismukes d2e59934c4 [Ada] AI12-0397: Default_Initial_Condition expressions for derived types
gcc/ada/

	* exp_util.adb (Add_Own_DIC): Suppress expansion of a DIC pragma
	when the pragma occurs for an abstract type, since that could
	lead to a call to an abstract function, and such DIC checks can
	never be performed for abstract types in any case.
	* sem_disp.adb (Check_Dispatching_Context): Suppress the check
	for illegal calls to abstract subprograms when the call occurs
	within a Default_Initial_Condition aspect and the call is passed
	the current instance as an actual.
	(Has_Controlling_Current_Instance_Actual): New function to test
	a call to see if it has any actuals given by direct references
	to a current instance of a type
	* sem_res.adb (Resolve_Actuals): Issue an error for a call
	within a DIC aspect to a nonprimitive subprogram with an actual
	given by the name of the DIC type's current instance (which will
	show up as a reference to the formal parameter of a DIC
	procedure).
2021-04-28 05:38:06 -04:00
Ed Schonberg bb60efc5c7 [Ada] Crash on inherited component in type extension in generic unit.
gcc/ada/

	* exp_ch3.adb (Expand_Record_Extension): Set Parent_Subtype on
	the type extension when within a generic unit, even though
	expansion is disabled, to allow for proper resolution of
	selected components inherited from an ancestor.
2021-04-28 05:38:05 -04:00
Arnaud Charlet ff683f9f03 [Ada] Crash with declare expression used in a postcondition
gcc/ada/

	* sem_aux.adb (Is_Limited_Type): Fix logic to check Is_Type
	before assuming Ent is a typo.
	* sem_ch4.adb (Analyze_Expression_With_Actions): Update
	comments, minor reformatting.
	* sem_res.adb (Resolve_Declare_Expression): Add protection
	against no type.
2021-04-28 05:38:04 -04:00
Arnaud Charlet df5f901ce8 [Ada] Incorrect discriminant check on call to access to subprogram
gcc/ada/

	* exp_ch6.adb: Fix typo in comment.
	* sem_ch3.adb (Access_Subprogram_Declaration): Add missing call
	to Create_Extra_Formals. Remove obsolete bootstrap check.
	* sem_eval.adb (Eval_Selected_Component): Simplify a
	selected_component on an aggregate.
2021-04-28 05:38:03 -04:00