* config/i386/i386.c (enum pta_flags): Move out of struct scope...
(struct pta): ...from here. Change flags to unsigned to avoid excessive
casting (as it is used as a bit mask).
(override_options): Add casts according to the coding convenventions.
(x86_64_elf_unique_section): Likewise.
(examine_argument): Avoid using C++ keywords as variable names.
(construct_container): Likewise.
(legitimize_pic_address): Likewise.
(get_dllimport_decl): Cast according to the coding conventions. Use
type safe memory macros.
(legitimize_address): Cast according to the coding conventions.
(emit_i387_cw_initialization): Corrected the type of slot to enum
ix86_stack_slot.
(ix86_init_machine_status): Use type safe memory macros.
(bdesc_pcmpestr): Use UNKNOWN instead of integer 0.
(bdesc_pcmpistr): Likewise.
(bdesc_crc32): Likewise.
(bdesc_sse_3arg): Likewise.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(ix86_expand_sse_pcmpestr): Cast according to the coding conventions.
(ix86_expand_sse_pcmpistr): Likewise.
(ix86_expand_vec_set_builtin): Use EXPAND_NORMAL instead of integer 0.
(ix86_builtin_vectorized_function): Change the type of fn to unsigned
int to match the langhook definition.
(ix86_builtin_conversion): Change the type of code to unsigned init to
match the langhook definition.
(ix86_preferred_reload_class): Avoid using C++ keywords as variable
names.
(ix86_preferred_output_reload_class): Likewise.
(ix86_cannot_change_mode_class): Likewise.
(ix86_memory_move_cost): Likewise.
(ix86_rtx_costs): Cast the outer_code parameter to enum rtx_code to
avoid excessive casting later on.
(x86_output_mi_thunk): Avoid using C++ keywords as variable names.
From-SVN: r125357
* config/i386/sse.md (sse4_2_pcmpestr_cconly): Prefer pcmpestrm
as flags setting insn.
(sse4_2_pcmpistr_cconly): Prefer pcmpistrm as flags setting insn.
* config/i386/i386.md (UNSPEC_ROUNDP, UNSPEC_ROUNDS): Remove.
(UNSPEC_ROUND): New.
("sse4_1_round<mode>2"): New insn pattern.
("rint<mode>2"): Expand using "sse4_1_round<mode>2" pattern for
SSE4.1 targets.
("floor<mode>2"): Rename from floordf2 and floorsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
("ceil<mode>2"): Rename from ceildf2 and ceilsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
("btrunc<mode>2"): Rename from btruncdf2 and btruncsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
* config/i386/sse.md ("sse4_1_roundpd", "sse4_1_roundps"): Use
UNSPEC_ROUND instead of UNSPEC_ROUNDP.
("sse4_1_roundsd", "sse4_1_roundss"): Use UNSPEC_ROUND instead of
UNSPEC_ROUNDS.
From-SVN: r125356
* lambda.h (build_linear_expr): New.
* lambda-code.c (lbv_to_gcc_expression, lle_to_gcc_expression):
Use build_linear_expr, call fold and force_gimple_operand.
(lambda_loopnest_to_gcc_loopnest): Check that there is
something to insert.
* testsuite/gcc.dg/tree-ssa/ltrans-6.c: New.
Co-Authored-By: Sebastian Pop <sebpop@gmail.com>
From-SVN: r125355
PR tree-optimization/32215
* tree-vectorizer.c (supportable_widening_operation): Return false
for unsupported FIX_TRUNC_EXPR tree code.
(supportable_narrowing_operation): Ditto for FLOAT_EXPR tree code.
From-SVN: r125343
* config/rs6000/rs6000.h (FIXED_SCRATCH): Use r0 as a scratch
register on SPE targets. Change documentation to reflect
reality.
* config/rs6000/rs6000.c (rs6000_conditional_register_usage):
Change FIXED_SCRATCH to 14 and document why we're keeping r14
out of the register allocation pool.
(rs6000_reg_live_or_pic_offset_p): New function.
(rs6000_emit_prologue): Move the actual saving of LR up to free
r0 for holding r11. Split saving of SPE 64-bit registers into
its own case. Ensure that offsets will always be in-range for
'evstdd' by using r11 as a scratch register to point at the start
of the SPE save area. Save r11 if necessary, as it is the static
chain register.
(rs6000_emit_epilogue): Split restoring of SPE 64-bit registers
into its own case. Ensure that offsets will always be in-range
for 'evldd' by using r11 as a scratch register to point at the
start of the SPE save area. Also adjust r11 when restoring
the stack pointer to compensate for pre-loading r11.
From-SVN: r125340
./: * tree-vrp.c (compare_values_warnv): Check TREE_NO_WARNING on a
PLUS_EXPR or MINUS_EXPR node before setting *strict_overflow_p.
(extract_range_from_assert): Set TREE_NO_WARNING when creating an
expression.
(test_for_singularity): Likewise.
testsuite/:
* gcc.dg/Wstrict-overflow-19.c: New test.
From-SVN: r125334
* config/i386/predicates/md (reg_not_xmm0_operand): New predicate.
(nonimm_not_xmm0_operand): Ditto.
* config/i386/sse.md ("sse4_1_blendvpd"): Use "reg_not_xmm0_operand"
as operand[0] and operand[1] predicate. Use "nonimm_not_xmm0_operand"
as operand[2] predicate. Require "z" class XMM register for
operand[3]. Adjust asm template.
("sse4_1_blendvpd"): Ditto.
("sse4_1_pblendvb"): Ditto.
* config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Do not
force op2 into xmm0 register for variable blend instructions.
From-SVN: r125327
./: * tree-vrp.c (adjust_range_with_scev): When loop is not expected
to overflow, reduce overflow infinity to regular infinity.
(vrp_var_may_overflow): New static function.
(vrp_visit_phi_node): Check vrp_var_may_overflow.
testsuite/:
* gcc.dg/Wstrict-overflow-18.c: New test.
From-SVN: r125319
* config/m68k/m68k.c (override_options): Don't override
REAL_MODE_FORMAT.
* config/m68k/m68k-modes.def (SF, DF): Define to use
motorola_single_format and motorola_double_format, resp.
* real.c (motorola_single_format): Renamed from
coldfire_single_format.
(motorola_double_format): Renamed from coldfire_double_format.
(encode_ieee_extended): Generate a proper canonical NaN image
respecting canonical_nan_lsbs_set.
(ieee_extended_motorola_format): Set canonical_nan_lsbs_set to
true.
* real.h: Adjust declarations.
From-SVN: r125295
* config/i386/i386.md ("sse4_1_blendvpd"): Require "z" class XMM
register for operand[3]. Adjust asm template.
("sse4_1_blendvpd"): Ditto.
("sse4_1_pblendvb"): Ditto.
* config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Call
safe_vector_operand() if input operand is VECTOR_MODE_P operand. Do not
force operands[3] into xmm0 register for variable blend instructions.
(ix86_expand_sse_pcmpestr): Do not check operands for
"register_operand", when insn operand predicate is "register_operand".
(ix86_expand_sse_pcmpistr): Ditto.
From-SVN: r125280
./: * tree-vrp.c (compare_name_with_value): Always set
used_strict_overflow if we get a result from the variable itself.
testsuite/:
* gcc.dg/Wstrict-overflow-17.c: New test.
From-SVN: r125269
PR rtl-optimization/31455
* lower-subreg.c (find_decomposable_subregs): Don't decompose
subregs which have a cast between modes which are not tieable.
From-SVN: r125265
2007-05-31 Eric Christopher <echristo@apple.com>
* expr.c (convert_move): Assert that we don't have a BLKmode
operand.
(store_expr): Handle BLKmode moves by calling emit_block_move.
From-SVN: r125246
in gcc/
2007-05-31 Daniel Berlin <dberlin@dberlin.org>
* c-typeck.c (build_indirect_ref): Include type in error message.
(build_binary_op): Pass types to binary_op_error.
* c-common.c (binary_op_error): Take two type arguments, print out
types with error.
* c-common.h (binary_op_error): Update prototype.
In gcc/cp
2007-05-31 Daniel Berlin <dberlin@dberlin.org>
* typeck.c (build_binary_op): Include types in error.
From-SVN: r125239
PR tree-optimization/32160
* tree-predcom.c (predcom_tmp_var): New function. Mark created
variable as gimple reg.
(initialize_root_vars, initialize_root_vars_lm): Use predcom_tmp_var.
* gfortran.dg/predcom-1.f: New test.
From-SVN: r125228
gcc/
* config.gcc (arm-wrs-vxworks): Remove dbxelf.h from tm_file.
Add vx-common.h. Include vxworks.h between vx-common.h and
arm/vxworks.h.
* config/vx-common.h (DWARF2_UNWIND_INFO): Undefine before
redefining.
* config/vxworks.h (TARGET_ASM_CONSTRUCTOR): Likewise.
(TARGET_ASM_DESTRUCTOR): Likewise.
* config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Check arm_arch_xscale
instead of arm_is_xscale. Use VXWORKS_OS_CPP_BUILTINS.
(OVERRIDE_OPTIONS, SUBTARGET_CPP_SPEC): Define.
(CC1_SPEC): Add -tstrongarm. Line up backslashes.
(VXWORKS_ENDIAN_SPEC): Define.
(ASM_SPEC): Add VXWORKS_ENDIAN_SPEC.
(LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Redefine to their
VXWORKS_* equivalents.
(LINK_SPEC): Likewise, but add VXWORKS_ENDIAN_SPEC.
(ASM_FILE_START): Delete.
(TARGET_VERSION): Reformat.
(FPUTYPE_DEFAULT, FUNCTION_PROFILER): Define.
(DEFAULT_STRUCTURE_SIZE_BOUNDARY): Define.
* config/arm/t-vxworks (LIB1ASMSRC, LIB1ASMFUNCS): Define.
(FPBIT, DPBIT): Define.
(fp-bit.c, dp-bit.c): New rules.
(MULTILIB_OPTIONS): Add strongarm, -mrtp and -mrtp/-fPIC multilibs.
(MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Define.
* config/arm/arm-protos.h (arm_emit_call_insn): Declare.
* config/arm/arm.h: Include vxworks-dummy.h.
* config/arm/arm.c (arm_elf_asm_constructor, arm_elf_asm_destructor):
Mark with ATTRIBUTE_UNUSED.
(arm_override_options): Do not allow VxWorks RTP PIC to be used
for Thumb. Force r9 to be the PIC register for VxWorks RTPs and
make it incompatible with -msingle-pic-base.
(arm_function_ok_for_sibcall): Return false for calls that might
go through a VxWorks PIC PLT entry.
(require_pic_register): New function, split out from...
(legitimize_pic_address): ...here. Do not use GOTOFF accesses
for VxWorks RTPs.
(arm_load_pic_register): Handle the VxWorks RTP initialization
sequence. Use pic_reg as a shorthand for cfun->machine->pic_reg.
(arm_emit_call_insn): New function.
(arm_assemble_integer): Do not use GOTOFF accesses for VxWorks RTP.
* config/arm/arm.md (UNSPEC_PIC_OFFSET): New unspec number.
(pic_offset_arm): New pattern.
(call, call_value): Use arm_emit_call_insn.
(call_internal, call_value_internal): New expanders.
* config/arm/lib1funcs.asm (__PLT__): Define to empty for
VxWorks unless __PIC__.
From-SVN: r125196
PR tree-optimization/31769
* except.c (duplicate_eh_regions): Clear prev_try if
ERT_MUST_NOT_THROW region is inside of ERT_TRY region.
* g++.dg/gomp/pr31769.C: New test.
From-SVN: r125183