gcc/ChangeLog:
2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
Do not emit FLAGS_REG clobber for TFmode.
* config/i386/i386.md (*<code>tf2_1): Rewrite as
define_insn_and_split. Mark operands 1 and 2 commutative.
(*nabstf2_1): Ditto.
(absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF.
Do not swap memory operands. Simplify RTX generation.
(neg abs SSE splitter): Ditto.
* config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
commutative. Do not swap operands. Simplify RTX generation.
(*nabs<mode>2): Ditto.
This adjusts the way we compute the stmt insert location for
invariants in BB vectorization context to deal with eventually
sharing invariant SLP nodes for multiple uses. We can no longer
use a single use stmt location then but there's a simple way out.
2020-05-18 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_slp_bb): Start after labels.
(vect_get_constant_vectors): Really place init stmt after scalar defs.
* tree-vect-stmts.c (vect_init_vector_1): Insert before
region begin.
Add cpu model numbers for Intel Airmont, Tremont, Comet Lake, Ice Lake
and Tiger Lake processor families.
* config/i386/driver-i386.c (host_detect_local_cpu): Support
Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake
processor families.
This fixes always-inlining across -fnon-call-exception boundaries
for conditions which we do not allow to throw.
2020-05-18 Richard Biener <rguenther@suse.de>
PR middle-end/95171
* tree-inline.c (remap_gimple_stmt): Split out trapping compares
when inlining into a non-call EH function.
* gcc.dg/pr95171.c: New testcase.
The following testcase shows a missed optimization that then leads to
wrong-code when issueing SMed stores on exits. When we were able to
compute an ordered sequence of stores for an exit we need to emit
that in the correct order and we can emit it disregarding to any
conditional for whether a store actually happened (we know it did).
We can also improve detection as of whether we need conditional
processing at all. Both parts fix the testcase.
2020-05-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/95172
* tree-ssa-loop-im.c (execute_sm): Get flag whether we
eventually need the conditional processing.
(execute_sm_exit): When processing an orderd sequence
avoid doing any conditional processing.
(hoist_memory_references): Pass down whether all edges
have ordered processing for a ref to execute_sm.
* gcc.dg/torture/pr95172.c: New testcase.
This avoids a (bogus) warning that occurs with some bootstrap
compilers.
gcc/cp/ChangeLog:
2020-05-17 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (morph_fn_to_coro): Initialize the
gro variable.
* config/h8300/predicates.md (pc_or_label_operand): New predicate.
* config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
into a single pattern using pc_or_label_operand.
* config/h8300/combiner.md (bit branch patterns): Likewise.
* config/h8300/peepholes.md (HImode and SImode branches): Likewise.
Add V1TI vector register push and split it after reload to a sequence
of:
(set (reg:P SP_REG) (plus:P SP_REG) (const_int -8)))
(set (match_dup 0) (match_dup 1))
so that STV pass can convert TI mode integer push to V1TI vector register
push. Rename has_non_address_hard_reg to pseudo_reg_set, combine calls
of single_set and has_non_address_hard_reg to pseudo_reg_set, to ignore
pseudo register push.
Remove c-c++-common/dfp/func-vararg-mixed-2.c since it is compiled with
-mpreferred-stack-boundary=2 and leads to segfault:
Dump of assembler code for function __bid_nesd2:
0x08049210 <+0>: endbr32
0x08049214 <+4>: push %esi
0x08049215 <+5>: push %ebx
0x08049216 <+6>: call 0x8049130 <__x86.get_pc_thunk.bx>
0x0804921b <+11>: add $0x8de5,%ebx
0x08049221 <+17>: sub $0x20,%esp
0x08049224 <+20>: mov 0x30(%esp),%esi
0x08049228 <+24>: pushl 0x2c(%esp)
0x0804922c <+28>: call 0x804e600 <__bid32_to_bid64>
0x08049231 <+33>: mov %esi,(%esp)
0x08049234 <+36>: movd %edx,%xmm1
0x08049238 <+40>: movd %eax,%xmm0
0x0804923c <+44>: punpckldq %xmm1,%xmm0
=> 0x08049240 <+48>: movaps %xmm0,0x10(%esp)
0x08049245 <+53>: call 0x804e600 <__bid32_to_bid64>
0x0804924a <+58>: push %edx
0x0804924b <+59>: push %eax
0x0804924c <+60>: pushl 0x1c(%esp)
0x08049250 <+64>: pushl 0x1c(%esp)
0x08049254 <+68>: call 0x804b260 <__bid64_quiet_not_equal>
0x08049259 <+73>: add $0x34,%esp
0x0804925c <+76>: pop %ebx
0x0804925d <+77>: pop %esi
0x0804925e <+78>: ret
when libgcc is compiled with -msse2. According to GCC manual:
'-mpreferred-stack-boundary=NUM'
Attempt to keep the stack boundary aligned to a 2 raised to NUM
byte boundary. If '-mpreferred-stack-boundary' is not specified,
the default is 4 (16 bytes or 128-bits).
*Warning:* If you use this switch, then you must build all modules
with the same value, including any libraries. This includes the
system libraries and startup modules.
c-c++-common/dfp/func-vararg-mixed-2.c, which was added by
commit 3b2488ca6e
Author: H.J. Lu <hongjiu.lu@intel.com>
Date: Wed Jul 30 19:24:02 2008 +0000
func-vararg-alternate-d128-2.c: New.
2008-07-30 H.J. Lu <hongjiu.lu@intel.com>
Joey Ye <joey.ye@intel.com>
* gcc.dg/dfp/func-vararg-alternate-d128-2.c: New.
* gcc.dg/dfp/func-vararg-mixed-2.c: Likewise.
isn't expected to work with libgcc.
gcc/
PR target/95021
* config/i386/i386-features.c (has_non_address_hard_reg):
Renamed to ...
(pseudo_reg_set): This. Return the SET expression. Ignore
pseudo register push.
(general_scalar_to_vector_candidate_p): Combine single_set and
has_non_address_hard_reg calls to pseudo_reg_set.
(timode_scalar_to_vector_candidate_p): Likewise.
* config/i386/i386.md (*pushv1ti2): New pattern.
gcc/testsuite/
PR target/95021
* c-c++-common/dfp/func-vararg-mixed-2.c: Removed.
* gcc.target/i386/pr95021-1.c: New test.
* gcc.target/i386/pr95021-2.c: Likewise.
* gcc.target/i386/pr95021-3.c: Likewise.
* gcc.target/i386/pr95021-4.c: Likewise.
* gcc.target/i386/pr95021-5.c: Likewise.
- core.cpuid has been fixed to not use i7 detection on AMD processors.
- std.net.curl has been fixed to correctly handle HTTP/2 status lines.
- std.zip has had a test fixed to not rely on unzip being installed.
Fixes: PR d/95166
PR d/95167
PR d/95168
Reviewed-on: https://github.com/dlang/druntime/pull/3107https://github.com/dlang/phobos/pull/7486
Add a strncmp test for the cmpstrn pattern with neither of the strings
is a constant string. We can expand the cmpstrn pattern to "repz cmpsb"
only if one of the strings is a constant so that expand_builtin_strncmp()
can write the length argument to be the minimum of the const string
length and the actual length argument. Otherwise, "repz cmpsb" may pass
the 0 byte.
* gcc.target/i386/strncmp-1.c: New test.
New class live_names to maintain the set of SSA names live.
Fix whitespace in vrp_insert.
Move a few more methods related to ASSERT_EXPR insertion into vrp_insert.
This is a case where the standard contains conflicting information.
after discussion between implementators, the accepted intent is of
[class.copy.elision]. This amends the handling of co_return statements
to follow that.
gcc/cp/ChangeLog:
2020-05-16 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (finish_co_return_stmt): Implement rules
from [class.copy.elision] /3.
gcc/testsuite/ChangeLog:
2020-05-16 Iain Sandoe <iain@sandoe.co.uk>
* g++.dg/coroutines/co-return-syntax-10-movable.C: New test.
* config/h8300/h8300.md (SFI iterator): New iterator for
SFmode and SImode.
* config/h8300/peepholes.md (memory comparison): Use mode
iterator to consolidate 3 patterns into one.
(stack allocation and stack store): Handle SFmode. Handle
8 byte allocations.
We sometimes fail to reject an invalid non-dependent operand to decltype
when inside a template, because finish_decltype_type resolves the
decltype to the TREE_TYPE of the operand before we ever instantiate and
fully process the operand. Fix this by adding a call to
instantiate_non_dependent_expr_sfinae in finish_decltype_type.
gcc/cp/ChangeLog:
PR c++/57943
* semantics.c (finish_decltype_type): Call
instantiate_non_dependent_expr_sfinae on the expression.
gcc/testsuite/ChangeLog:
PR c++/57943
* g++.dg/cpp0x/decltype76.C: New test.
Now that GCC 10 is out it seems time. People can still choose to disable
coroutines with -fno-coroutines.
This also switches the coroutines testsuite to run in C++20 mode. The
change to coro.h is only necessary for co-await-11-forwarding.C; we could
alternatively #include <utility> just in that file.
gcc/c-family/ChangeLog
2020-05-15 Jason Merrill <jason@redhat.com>
* c-opts.c (set_std_cxx20): Set flag_coroutines.
gcc/testsuite/ChangeLog
2020-05-15 Jason Merrill <jason@redhat.com>
* g++.dg/coroutines/coro.h: Always #include <utility>.
* g++.dg/coroutines/coroutines.exp (DEFAULT_COROFLAGS): Use
-std=c++20.
BU_FUTURE_MISC_2 is (currently) only used for instructions that require
64-bit registers.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
RS6000_BTM_POWERPC64.
Tests that use the __int128 type need to use the int128 selector.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/vec-gnb-0.c: Use int128 effective target.
* gcc.target/powerpc/vec-gnb-1.c: Ditto.
* gcc.target/powerpc/vec-gnb-2.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-8.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-9.c: Ditto.
* gcc.target/powerpc/vec-ternarylogic-10.c: Ditto.
The powerpc64 effective target unfortunately does not mean the target
has 64-bit instructions enabled (i.e., -mpowerpc64): instead, it means
that the assembler supports it.
Let's use the lp64 effective target instead for these tests.
2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/cntlzdm-0.c: Use lp64 instead of powerpc64.
* gcc.target/powerpc/cntlzdm-1.c: Ditto.
* gcc.target/powerpc/cnttzdm-1.c: Ditto.
* gcc.target/powerpc/pdep-0.c: Ditto.
* gcc.target/powerpc/pdep-1.c: Ditto.
* gcc.target/powerpc/pextd-0.c: Ditto.
* gcc.target/powerpc/pextd-1.c: Ditto.
The process_init_constructor_array part of my PR90996 patch turns out to
be neither necessary nor sufficient to make the pr90996.C testcase work,
and I wasn't able to come up with a testcase that demonstrates this part
is ever necessary.
gcc/cp/ChangeLog:
Revert:
2020-04-07 Patrick Palka <ppalka@redhat.com>
PR c++/90996
* typeck2.c (process_init_constructor_array): Propagate
CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element
initializer to the array initializer.
gcc/testsuite/ChangeLog:
PR c++/90996
* g++.dg/cpp1y/pr90996.C: Turn into execution test to verify
that each PLACEHOLDER_EXPR gets correctly resolved.
My GCC 10 patch for 93286 fixed the missing piece in tsubst's handling of
lists vs. that in tsubst_copy_and_build, but it would be better to share the
code between them.
gcc/cp/ChangeLog
2020-05-15 Jason Merrill <jason@redhat.com>
PR c++/93286 - ICE with __is_constructible and variadic template.
* pt.c (tsubst_tree_list): New.
(tsubst, tsubst_copy_and_build): Use it.
* decl2.c (is_late_template_attribute): Handle error_mark_node args.
Arseny Solokha noticed I'd flubbed this patch, and it was not saying
what I thought it was saying. Unfortunately that didn't break
anything (otherwise I'd've noticed). Fixed thusly.
* pt.c (template_args_equal): Fix thinkos in previous 'cleanup'.
This improves the fix for PR92260 changing the number of vector
computation to the canonical one, not needing to look at the
using stmt.
2020-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/92260
* tree-vect-slp.c (vect_get_constant_vectors): Compute
the number of vector stmts in a canonical way.
This fixes a wrong-code logic error in a previous patch.
Detected by gcc.c-torture/execute/pr53645-2.c.
2020-05-15 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
This commit is for the benefit of GDB, but as the binutils-gdb
repository shares the contrib/ directory with gcc, this commit must
first be applied to gcc then copied back to binutils-gdb.
This commit extends the two scripts contrib/dg-extract-results.{py,sh}
to handle some new, GDB specific test result types. These test
results types should never appear in GCC, or any other tool that
shares the contrib/ directly, so this change should be harmless.
In this patch series:
https://sourceware.org/pipermail/gdb-patches/2020-April/167847.html
changes were made in GDB's use of Dejagnu so that two additional
conditions could be detected, these are:
1. Test names that contain either the build or source paths. Such
test names make it difficult to compare the results of two test runs
of GDB from two different directories, and
2. Duplicate test names. Duplicates make it difficult to track down
exactly which test has failed.
When running Dejagnu on GDB we can now (sometimes) see two additional
test result types matching the above conditions, these are '# of paths
in test names' and '# of duplicate test names'.
If the test is run in parallel mode (make -j...) then these extra test
results will appear in the individual test summary files, but are not
merged into the final summary file.
Additionally, within the summary file there are now two new types of
test summary line, these are 'PATH: ...' and 'DUPLICATE: ...', these
allow users to quickly search the test summary to track down where the
offending test names are. These lines are similarly not merged into
the unified gdb.sum file after a parallel test run.
This commit extends the dg-extract-results.* scripts to calculate the
totals for the two new result types, and to copy the new test summary
lines into the unified summary file.
contrib/ChangeLog:
* dg-extract-results.py: Handle GDB specific test types.
* dg-extract-results.sh: Likewise.
When path splitting tries to detect a CFG diamond make sure it
is composed of normal (non-EH, not abnormal) edges. Otherwise
CFG manipulation later may fail.
2020-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/95133
* gimple-ssa-split-paths.c
(find_block_to_duplicate_for_splitting_paths): Check for
normal edges.
* gcc.dg/pr95133.c: New testcase.
reg_needs_saving_p is only used when dealing with non-interrupt
routines, but it makes sense to extend it to support that context too,
and make arm_compute_save_reg0_reg12_mask use it.
Save only live registers for non-leaf functions, but assume a callee
could clobber any register.
2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
routines.
(arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
gcc/
PR middle-end/94635
* gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
item is 'delete:'.
gcc/testsuite
PR middle-end/94635
* gfortran.dg/gomp/target-exit-data.f90: New.
Adds support for demangling D functions annotated with the new
ownership/borrowing system attribute.
libiberty/ChangeLog:
* d-demangle.c (dlang_attributes): Add @live attribute.
* testsuite/d-demangle-expected: Add new tests.
PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative
in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which
implies SSE2. These instructions are only generated via builtins, and
since several 3dNow! insns have no corresponding SSE alternative,
we can't avoid MMX registers with 3dNow! builtins anyway.
Add SSE3/AVX alternatives to the insn pattern, so compiler will be able
to use XMM registers when available, but don't prevent MMX registers,
since they are needed when SSE3 is not active.
Add additional generic insn patterns, used by the combiner to
synthesize horizontal V2SFmode add/sub instructions. These patterns
are active for TARGET_MMX_WITH_SSE only, and use only XMM registers.
gcc/ChangeLog:
PR target/95046
* config/i386/i386.md (isa): Add sse3_noavx.
(enabled): Handle sse3_noavx.
* config/i386/mmx.md (mmx_haddv2sf3): New expander.
(*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
alternatives. Match commutative vec_select selector operands.
(*mmx_haddv2sf3_low): New insn pattern.
(*mmx_hsubv2sf3): Add SSE/AVX alternatives.
(*mmx_hsubv2sf3_low): New insn pattern.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-8.c: New test.
PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative
in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which
implies SSE2. These instructions are only generated via builtins, and
since several 3dNow! insns have no corresponding SSE alternative,
we can't avoid MMX registers with 3dNow! builtins anyway.
Add SSE3/AVX alternatives to the insn pattern, so compiler will be able
to use XMM registers when available, but don't prevent MMX registers,
since they are needed when SSE3 is not active.
Add additional generic insn patterns, used by the combiner to
synthesize horizontal V2SFmode add/sub instructions. These patterns
are active for TARGET_MMX_WITH_SSE only, and use only XMM registers.
gcc/ChangeLog:
PR target/95046
* config/i386/i386.md (isa): Add sse3_noavx.
(enabled): Handle sse3_noavx.
* config/i386/mmx.md (mmx_haddv2sf3): New expander.
(*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
alternatives. Match commutative vec_select selector operands.
(*mmx_haddv2sf3_low): New insn pattern.
(*mmx_hsubv2sf3): Add SSE/AVX alternatives.
(*mmx_hsubv2sf3_low): New insn pattern.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-8.c: New test.
This implements commoning of stores to a common successor in
a simple ad-hoc way. I've decided to put it into the code sinking
pass since, well, it sinks stores. It's still separate since
it does not really sink code into less executed places.
It's ad-hoc since it does not perform any dataflow or alias analysis
but simply only considers trailing stores in a block, iteratively
though. If the stores are from different values a PHI node is
inserted to merge them. gcc.dg/tree-ssa/split-path-7.c shows
that path splitting will eventually undo this very transform,
I've decided to not bother with it and simply disable sinking for
the particular testcase.
Doing this transform is good for code size when the stores are
from constants, once we have to insert PHIs the situation becomes
less clear but it's a transform we do elsewhere as well
(cselim for one), and reversing the transform should be easy.
2020-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/33315
* tree-ssa-sink.c: Include tree-eh.h.
(sink_stats): Add commoned member.
(sink_common_stores_to_bb): New function implementing store
commoning by sinking to the successor.
(sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
(pass_sink_code::execute): Likewise. Record commoned stores
in statistics.
* gcc.dg/tree-ssa/ssa-sink-13.c: New testcase.
* gcc.dg/tree-ssa/ssa-sink-14.c: Likewise.
* gcc.dg/tree-ssa/split-path-7.c: Disable sinking.
This "subtract/extend/add" existed for a long time and still annoying us
(PR37451, part of PR61837) when converting from 32bits to 64bits, as the ctr
register is used as 64bits on powerpc64, Andraw Pinski had a patch but
caused some issue and reverted by Joseph S. Myers(PR37451, PR37782).
Andraw:
http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01070.htmlhttp://gcc.gnu.org/ml/gcc-patches/2008-10/msg01321.html
Joseph:
https://gcc.gnu.org/legacy-ml/gcc-patches/2011-11/msg02405.html
We still can do the simplification from "subtract/zero_ext/add" to "zero_ext"
when loop iterations is known to be LT than MODE_MAX (only do simplify
when counter+0x1 NOT overflow).
Bootstrap and regression tested pass on Power8-LE.
gcc/ChangeLog
2020-05-15 Xiong Hu Luo <luoxhu@linux.ibm.com>
PR rtl-optimization/37451, part of PR target/61837
* loop-doloop.c (doloop_simplify_count): New function. Simplify
(add -1; zero_ext; add +1) to zero_ext when not wrapping.
(doloop_modify): Call doloop_simplify_count.
gcc/testsuite/ChangeLog
2020-05-15 Xiong Hu Luo <luoxhu@linux.ibm.com>
PR rtl-optimization/37451, part of PR target/61837
* gcc.target/powerpc/doloop-2.c: New test.
Uros Bizjak
Richard Biener
H.J. Lu
Alex Coplan
GCC Administrator
Iain Sandoe
Jeff Law
Iain Buclaw
Aldy Hernandez
Patrick Palka
Joseph Myers
Ian Lance Taylor
Jason Merrill
Segher Boessenkool
Tobias Burnus
Nathan Sidwell
Martin Liska
Andrew Stubbs
Andrew Burgess
Christophe Lyon
Xionghu Luo