245 lines
7.2 KiB
C++
245 lines
7.2 KiB
C++
/* Copyright (C) 2009, 2011 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@redhat.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef LIBITM_CACHELINE_H
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#define LIBITM_CACHELINE_H 1
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// Minimum cacheline size is 32, due to both complex long double and __m256.
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// There's no requirement that 64-bit use a 64-byte cacheline size, but do
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// so for now to make sure everything is parameterized properly.
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#ifdef __x86_64__
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# define CACHELINE_SIZE 64
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#else
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# define CACHELINE_SIZE 32
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#endif
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namespace GTM HIDDEN {
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// A gtm_cacheline_mask stores a modified bit for every modified byte
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// in the cacheline with which it is associated.
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typedef sized_integral<CACHELINE_SIZE / 8>::type gtm_cacheline_mask;
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extern uint32_t const gtm_bit_to_byte_mask[16];
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union gtm_cacheline
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{
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// Byte access to the cacheline.
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unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE)));
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// Larger sized access to the cacheline.
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uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)];
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uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)];
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uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)];
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gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)];
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#ifdef __MMX__
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__m64 m64[CACHELINE_SIZE / sizeof(__m64)];
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#endif
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#ifdef __SSE__
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__m128 m128[CACHELINE_SIZE / sizeof(__m128)];
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#endif
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#ifdef __SSE2__
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__m128i m128i[CACHELINE_SIZE / sizeof(__m128i)];
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#endif
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#ifdef __AVX__
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__m256 m256[CACHELINE_SIZE / sizeof(__m256)];
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__m256i m256i[CACHELINE_SIZE / sizeof(__m256i)];
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#endif
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// Store S into D, but only the bytes specified by M.
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static void store_mask (uint32_t *d, uint32_t s, uint8_t m);
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static void store_mask (uint64_t *d, uint64_t s, uint8_t m);
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#ifdef __SSE2__
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static void store_mask (__m128i *d, __m128i s, uint16_t m);
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#endif
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// Copy S to D, but only the bytes specified by M.
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static void copy_mask (gtm_cacheline * __restrict d,
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const gtm_cacheline * __restrict s,
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gtm_cacheline_mask m);
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// A write barrier to emit after (a series of) copy_mask.
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// When we're emitting non-temporal stores, the normal strong
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// ordering of the machine doesn't apply.
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static void copy_mask_wb ();
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#if defined(__SSE__) || defined(__AVX__)
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// Copy S to D; only bother defining if we can do this more efficiently
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// than the compiler-generated default implementation.
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gtm_cacheline& operator= (const gtm_cacheline &s);
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#endif // SSE, AVX
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};
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inline void
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gtm_cacheline::copy_mask_wb ()
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{
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#ifdef __SSE2__
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_mm_sfence ();
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#endif
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}
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#if defined(__SSE__) || defined(__AVX__)
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inline gtm_cacheline& ALWAYS_INLINE
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gtm_cacheline::operator= (const gtm_cacheline & __restrict s)
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{
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#ifdef __AVX__
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# define CP m256
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# define TYPE __m256
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#else
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# define CP m128
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# define TYPE __m128
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#endif
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TYPE w, x, y, z;
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// ??? Wouldn't it be nice to have a pragma to tell the compiler
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// to completely unroll a given loop?
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switch (CACHELINE_SIZE / sizeof(TYPE))
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{
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case 1:
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this->CP[0] = s.CP[0];
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break;
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case 2:
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x = s.CP[0];
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y = s.CP[1];
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this->CP[0] = x;
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this->CP[1] = y;
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break;
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case 4:
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w = s.CP[0];
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x = s.CP[1];
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y = s.CP[2];
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z = s.CP[3];
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this->CP[0] = w;
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this->CP[1] = x;
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this->CP[2] = y;
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this->CP[3] = z;
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break;
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default:
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__builtin_trap ();
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}
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return *this;
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}
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#endif
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// Support masked integer stores more efficiently with an unlocked cmpxchg
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// insn. My reasoning is that while we write to locations that we do not wish
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// to modify, we do it in an uninterruptable insn, and so we either truely
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// write back the original data or the insn fails -- unlike with a
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// load/and/or/write sequence which can be interrupted either by a kernel
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// task switch or an unlucky cacheline steal by another processor. Avoiding
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// the LOCK prefix improves performance by a factor of 10, and we don't need
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// the memory barrier semantics implied by that prefix.
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inline void ALWAYS_INLINE
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gtm_cacheline::store_mask (uint32_t *d, uint32_t s, uint8_t m)
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{
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gtm_cacheline_mask tm = (1 << sizeof (s)) - 1;
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if (__builtin_expect (m & tm, tm))
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{
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if (__builtin_expect ((m & tm) == tm, 1))
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*d = s;
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else
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{
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gtm_cacheline_mask bm = gtm_bit_to_byte_mask[m & 15];
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gtm_word n, o = *d;
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__asm("\n0:\t"
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"mov %[o], %[n]\n\t"
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"and %[m], %[n]\n\t"
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"or %[s], %[n]\n\t"
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"cmpxchg %[n], %[d]\n\t"
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".byte 0x2e\n\t" // predict not-taken, aka jnz,pn
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"jnz 0b"
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: [d] "+m"(*d), [n] "=&r" (n), [o] "+a"(o)
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: [s] "r" (s & bm), [m] "r" (~bm));
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}
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}
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}
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inline void ALWAYS_INLINE
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gtm_cacheline::store_mask (uint64_t *d, uint64_t s, uint8_t m)
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{
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gtm_cacheline_mask tm = (1 << sizeof (s)) - 1;
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if (__builtin_expect (m & tm, tm))
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{
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if (__builtin_expect ((m & tm) == tm, 1))
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*d = s;
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else
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{
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#ifdef __x86_64__
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uint32_t bl = gtm_bit_to_byte_mask[m & 15];
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uint32_t bh = gtm_bit_to_byte_mask[(m >> 4) & 15];
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gtm_cacheline_mask bm = bl | ((gtm_cacheline_mask)bh << 31 << 1);
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uint64_t n, o = *d;
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__asm("\n0:\t"
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"mov %[o], %[n]\n\t"
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"and %[m], %[n]\n\t"
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"or %[s], %[n]\n\t"
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"cmpxchg %[n], %[d]\n\t"
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".byte 0x2e\n\t" // predict not-taken, aka jnz,pn
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"jnz 0b"
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: [d] "+m"(*d), [n] "=&r" (n), [o] "+a"(o)
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: [s] "r" (s & bm), [m] "r" (~bm));
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#else
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/* ??? While it's possible to perform this operation with
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cmpxchg8b, the sequence requires all 7 general registers
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and thus cannot be performed with -fPIC. Don't even try. */
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uint32_t *d32 = reinterpret_cast<uint32_t *>(d);
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store_mask (d32, s, m);
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store_mask (d32 + 1, s >> 32, m >> 4);
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#endif
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}
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}
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}
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#ifdef __SSE2__
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inline void ALWAYS_INLINE
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gtm_cacheline::store_mask (__m128i *d, __m128i s, uint16_t m)
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{
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if (__builtin_expect (m == 0, 0))
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return;
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if (__builtin_expect (m == 0xffff, 1))
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*d = s;
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else
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{
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__m128i bm0, bm1, bm2, bm3;
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bm0 = _mm_set_epi32 (0, 0, 0, gtm_bit_to_byte_mask[m & 15]); m >>= 4;
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bm1 = _mm_set_epi32 (0, 0, 0, gtm_bit_to_byte_mask[m & 15]); m >>= 4;
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bm2 = _mm_set_epi32 (0, 0, 0, gtm_bit_to_byte_mask[m & 15]); m >>= 4;
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bm3 = _mm_set_epi32 (0, 0, 0, gtm_bit_to_byte_mask[m & 15]); m >>= 4;
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bm0 = _mm_unpacklo_epi32 (bm0, bm1);
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bm2 = _mm_unpacklo_epi32 (bm2, bm3);
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bm0 = _mm_unpacklo_epi64 (bm0, bm2);
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_mm_maskmoveu_si128 (s, bm0, (char *)d);
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}
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}
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#endif // SSE2
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} // namespace GTM
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#endif // LIBITM_CACHELINE_H
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