f095523350
This patch is the first of a series that tries to remove two
assumptions:
(1) that all vectors involved in vectorisation must be the same size
(2) that there is only one vector mode for a given element mode and
number of elements
Relaxing (1) helps with targets that support multiple vector sizes or
that require the number of elements to stay the same. E.g. if we're
vectorising code that operates on narrow and wide elements, and the
narrow elements use 64-bit vectors, then on AArch64 it would normally
be better to use 128-bit vectors rather than pairs of 64-bit vectors
for the wide elements.
Relaxing (2) makes it possible for -msve-vector-bits=128 to produce
fixed-length code for SVE. It also allows unpacked/half-size SVE
vectors to work with -msve-vector-bits=256.
The patch adds a new hook that targets can use to control how we
move from one vector mode to another. The hook takes a starting vector
mode, a new element mode, and (optionally) a new number of elements.
The flexibility needed for (1) comes in when the number of elements
isn't specified.
All callers in this patch specify the number of elements, but a later
vectoriser patch doesn't.
2019-11-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* target.def (related_mode): New hook.
* doc/tm.texi.in (TARGET_VECTORIZE_RELATED_MODE): New hook.
* doc/tm.texi: Regenerate.
* targhooks.h (default_vectorize_related_mode): Declare.
* targhooks.c (default_vectorize_related_mode): New function.
* machmode.h (related_vector_mode): Declare.
* stor-layout.c (related_vector_mode): New function.
* expmed.c (extract_bit_field_1): Use it instead of mode_for_vector.
* optabs-query.c (qimode_for_vec_perm): Likewise.
* tree-vect-stmts.c (get_group_load_store_type): Likewise.
(vectorizable_store, vectorizable_load): Likewise
From-SVN: r278229
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| contrib | ||
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