Limit threads sharing L2 cache to 2 for SLM/KNL
Silvermont and Knights Landing have a modular system design with two cores sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, it should be adjusted for Silvermont and Knights Landing. [BZ #18185] * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads sharing L2 cache to 2 for Silvermont/Knights Landing.
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2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
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[BZ #18185]
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* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
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sharing L2 cache to 2 for Silvermont/Knights Landing.
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2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
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[BZ #17711]
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2
NEWS
2
NEWS
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@ -15,7 +15,7 @@ Version 2.22
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17932, 17944, 17949, 17964, 17965, 17967, 17969, 17978, 17987, 17991,
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17996, 17998, 17999, 18019, 18020, 18029, 18030, 18032, 18036, 18038,
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18039, 18042, 18043, 18046, 18047, 18068, 18080, 18093, 18100, 18104,
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18110, 18111, 18128, 18138.
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18110, 18111, 18128, 18138, 18185.
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* A powerpc and powerpc64 optimization for TLS, similar to TLS descriptors
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for LD and GD on x86 and x86-64, has been implemented. You will need
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@ -585,6 +585,10 @@ init_cacheinfo (void)
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__cpuid (1, eax, ebx_1, ecx, edx);
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#endif
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unsigned int family = (eax >> 8) & 0x0f;
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unsigned int model = (eax >> 4) & 0x0f;
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unsigned int extended_model = (eax >> 12) & 0xf0;
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#ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
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/* Intel prefers SSSE3 instructions for memory/string routines
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if they are available. */
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@ -647,6 +651,25 @@ init_cacheinfo (void)
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}
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}
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threads += 1;
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if (threads > 2 && level == 2 && family == 6)
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{
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model += extended_model;
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switch (model)
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{
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case 0x57:
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/* Knights Landing has L2 cache shared by 2 cores. */
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Silvermont has L2 cache shared by 2 cores. */
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threads = 2;
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break;
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default:
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break;
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}
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}
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}
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else
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{
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