203 lines
5.9 KiB
C
203 lines
5.9 KiB
C
#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
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#define __LINUX_TI_AM335X_TSCADC_MFD_H
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/*
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* TI Touch Screen / ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mfd/core.h>
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#define REG_RAWIRQSTATUS 0x024
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#define REG_IRQSTATUS 0x028
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#define REG_IRQENABLE 0x02C
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#define REG_IRQCLR 0x030
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#define REG_IRQWAKEUP 0x034
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#define REG_DMAENABLE_SET 0x038
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#define REG_DMAENABLE_CLEAR 0x03c
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#define REG_CTRL 0x040
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#define REG_ADCFSM 0x044
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#define REG_CLKDIV 0x04C
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#define REG_SE 0x054
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#define REG_IDLECONFIG 0x058
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#define REG_CHARGECONFIG 0x05C
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#define REG_CHARGEDELAY 0x060
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#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
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#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
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#define REG_FIFO0CNT 0xE4
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#define REG_FIFO0THR 0xE8
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#define REG_FIFO1CNT 0xF0
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#define REG_FIFO1THR 0xF4
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#define REG_DMA1REQ 0xF8
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#define REG_FIFO0 0x100
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#define REG_FIFO1 0x200
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/* Register Bitfields */
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/* IRQ wakeup enable */
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#define IRQWKUP_ENB BIT(0)
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/* Step Enable */
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#define STEPENB_MASK (0x1FFFF << 0)
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#define STEPENB(val) ((val) << 0)
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#define ENB(val) (1 << (val))
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#define STPENB_STEPENB STEPENB(0x1FFFF)
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#define STPENB_STEPENB_TC STEPENB(0x1FFF)
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/* IRQ enable */
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#define IRQENB_HW_PEN BIT(0)
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#define IRQENB_EOS BIT(1)
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#define IRQENB_FIFO0THRES BIT(2)
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#define IRQENB_FIFO0OVRRUN BIT(3)
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#define IRQENB_FIFO0UNDRFLW BIT(4)
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#define IRQENB_FIFO1THRES BIT(5)
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#define IRQENB_FIFO1OVRRUN BIT(6)
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#define IRQENB_FIFO1UNDRFLW BIT(7)
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#define IRQENB_PENUP BIT(9)
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/* Step Configuration */
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#define STEPCONFIG_MODE_MASK (3 << 0)
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#define STEPCONFIG_MODE(val) ((val) << 0)
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#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
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#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
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#define STEPCONFIG_AVG_MASK (7 << 2)
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#define STEPCONFIG_AVG(val) ((val) << 2)
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#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
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#define STEPCONFIG_XPP BIT(5)
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#define STEPCONFIG_XNN BIT(6)
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#define STEPCONFIG_YPP BIT(7)
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#define STEPCONFIG_YNN BIT(8)
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#define STEPCONFIG_XNP BIT(9)
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#define STEPCONFIG_YPN BIT(10)
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#define STEPCONFIG_RFP(val) ((val) << 12)
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#define STEPCONFIG_RFP_VREFP (0x3 << 12)
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#define STEPCONFIG_INM_MASK (0xF << 15)
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#define STEPCONFIG_INM(val) ((val) << 15)
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#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
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#define STEPCONFIG_INP_MASK (0xF << 19)
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#define STEPCONFIG_INP(val) ((val) << 19)
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#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
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#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
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#define STEPCONFIG_FIFO1 BIT(26)
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#define STEPCONFIG_RFM(val) ((val) << 23)
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#define STEPCONFIG_RFM_VREFN (0x3 << 23)
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/* Delay register */
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#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
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#define STEPDELAY_OPEN(val) ((val) << 0)
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#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
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#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
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#define STEPDELAY_SAMPLE(val) ((val) << 24)
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#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
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/* Charge Config */
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#define STEPCHARGE_RFP_MASK (7 << 12)
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#define STEPCHARGE_RFP(val) ((val) << 12)
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#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
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#define STEPCHARGE_INM_MASK (0xF << 15)
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#define STEPCHARGE_INM(val) ((val) << 15)
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#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
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#define STEPCHARGE_INP_MASK (0xF << 19)
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#define STEPCHARGE_INP(val) ((val) << 19)
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#define STEPCHARGE_RFM_MASK (3 << 23)
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#define STEPCHARGE_RFM(val) ((val) << 23)
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#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
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/* Charge delay */
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#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
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#define CHARGEDLY_OPEN(val) ((val) << 0)
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#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
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/* Control register */
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#define CNTRLREG_TSCSSENB BIT(0)
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#define CNTRLREG_STEPID BIT(1)
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#define CNTRLREG_STEPCONFIGWRT BIT(2)
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#define CNTRLREG_POWERDOWN BIT(4)
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#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
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#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
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#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
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#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
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#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
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#define CNTRLREG_TSCENB BIT(7)
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/* FIFO READ Register */
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#define FIFOREAD_DATA_MASK (0xfff << 0)
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#define FIFOREAD_CHNLID_MASK (0xf << 16)
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/* DMA ENABLE/CLEAR Register */
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#define DMA_FIFO0 BIT(0)
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#define DMA_FIFO1 BIT(1)
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/* Sequencer Status */
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#define SEQ_STATUS BIT(5)
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#define CHARGE_STEP 0x11
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#define ADC_CLK 3000000
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#define TOTAL_STEPS 16
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#define TOTAL_CHANNELS 8
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#define FIFO1_THRESHOLD 19
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/*
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* time in us for processing a single channel, calculated as follows:
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*
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* max num cycles = open delay + (sample delay + conv time) * averaging
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*
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* max num cycles: 262143 + (255 + 13) * 16 = 266431
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*
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* clock frequency: 26MHz / 8 = 3.25MHz
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* clock period: 1 / 3.25MHz = 308ns
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*
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* max processing time: 266431 * 308ns = 83ms(approx)
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*/
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#define IDLE_TIMEOUT 83 /* milliseconds */
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#define TSCADC_CELLS 2
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struct ti_tscadc_dev {
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struct device *dev;
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struct regmap *regmap;
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void __iomem *tscadc_base;
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phys_addr_t tscadc_phys_base;
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int irq;
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int used_cells; /* 1-2 */
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int tsc_wires;
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int tsc_cell; /* -1 if not used */
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int adc_cell; /* -1 if not used */
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struct mfd_cell cells[TSCADC_CELLS];
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u32 reg_se_cache;
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bool adc_waiting;
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bool adc_in_use;
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wait_queue_head_t reg_se_wait;
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spinlock_t reg_lock;
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unsigned int clk_div;
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/* tsc device */
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struct titsc *tsc;
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/* adc device */
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struct adc_device *adc;
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};
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static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
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{
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struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
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return *tscadc_dev;
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}
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
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#endif
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