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linux-headers-5.4.0-2.3

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Alibek Omarov 2 years ago
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252
arch/e2k/Makefile
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# e2k/Makefile
#
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies. Remember to do have actions
# for "archclean" and "archdep" for cleaning up and making dependencies for
# this architecture
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
KBUILD_DEFCONFIG ?= defconfig
AS = $(shell $(CC) -print-prog-name=as)
OBJDUMP = $(shell $(CC) -print-prog-name=objdump)
LD = $(shell $(CC) -print-prog-name=ld)
OBJCOPY = $(shell $(CC) -print-prog-name=objcopy)
KBUILD_CFLAGS += -fkernel -gline -masm-inline $(call cc-option,-fforbid-fp) \
$(call cc-option,-fmax-errors=5)
ifeq ($(PROFILE_GENERATE), 1)
KBUILD_CFLAGS += -fprofile-generate-kernel
endif
ifeq ($(origin PROFILE_USE), undefined)
else
KBUILD_CFLAGS += -fprofile-use="$(PROFILE_USE)"
endif
KBUILD_CFLAGS += $(call cc-option,-finline-functions,) \
$(call cc-option,-finline-functions-called-once,)
# Some uninteresting or broken warnings can be disabled with #pragma's only
KBUILD_CFLAGS += -Wno-array-bounds -Wno-duplicate-type-qualifier \
-Wno-builtin-functions-redefined -Wno-reduced-alignment \
-Wno-unused-value -Wno-overflow -Wno-signed-one-bit-field \
-include $(srctree)/arch/e2k/include/asm/override-lcc-warnings.h
LDFLAGS_vmlinux :=
CHECKFLAGS += -D__e2k__
CFLAGS += -pipe -D__linux__
KBUILD_CFLAGS += $(CFLAGS)
ifdef CONFIG_SMP_DAM_BUG
KBUILD_CFLAGS += -fno-dam-call
endif
CFLAGS_GENERIC := -march=elbrus-v2
CFLAGS_ES2 := -mtune=elbrus-2c+
CFLAGS_E2S := -mtune=elbrus-4c
CFLAGS_E8C := -mtune=elbrus-8c
CFLAGS_E1CP := -mtune=elbrus-1c+
CFLAGS_E8C2 := -mtune=elbrus-8c2
CFLAGS_E12C := -mtune=elbrus-12c
CFLAGS_E16C := -mtune=elbrus-16c
CFLAGS_E2C3 := -mtune=elbrus-2c3
CFLAGS_ALL_CPUS := $(CFLAGS_ES2) $(CFLAGS_E2S) $(CFLAGS_E8C) $(CFLAGS_E1CP) \
$(CFLAGS_E8C2) $(CFLAGS_E12C) $(CFLAGS_E16C) $(CFLAGS_E2C3)
export CFLAGS_ALL_CPUS
CFLAGS_E2K_SIC := $(CFLAGS_ES2)
export CFLAGS_ES2 CFLAGS_E2S CFLAGS_E8C CFLAGS_E1CP CFLAGS_E8C2 CFLAGS_E2C3 \
CFLAGS_E12C CFLAGS_E16C CFLAGS_E2K_SIC
ifeq ($(CONFIG_E2K_MACHINE),y)
ifeq ($(CONFIG_E2K_ES2_DSP),y)
KBUILD_CFLAGS += $(CFLAGS_ES2)
KBUILD_AFLAGS += $(CFLAGS_ES2)
TARGET_MDL := 04
else
ifeq ($(CONFIG_E2K_ES2_RU),y)
KBUILD_CFLAGS += $(CFLAGS_ES2)
KBUILD_AFLAGS += $(CFLAGS_ES2)
TARGET_MDL := 06
else
ifeq ($(CONFIG_E2K_E2S),y)
KBUILD_CFLAGS += $(CFLAGS_E2S)
KBUILD_AFLAGS += $(CFLAGS_E2S)
TARGET_MDL := 03
else
ifeq ($(CONFIG_E2K_E8C),y)
KBUILD_CFLAGS += $(CFLAGS_E8C)
KBUILD_AFLAGS += $(CFLAGS_E8C)
TARGET_MDL := 07
else
ifeq ($(CONFIG_E2K_E1CP),y)
KBUILD_CFLAGS += $(CFLAGS_E1CP)
KBUILD_AFLAGS += $(CFLAGS_E1CP)
TARGET_MDL := 08
else
ifeq ($(CONFIG_E2K_E8C2),y)
KBUILD_CFLAGS += $(CFLAGS_E8C2)
KBUILD_AFLAGS += $(CFLAGS_E8C2)
TARGET_MDL := 09
else
ifeq ($(CONFIG_E2K_E12C),y)
KBUILD_CFLAGS += $(CFLAGS_E12C)
KBUILD_AFLAGS += $(CFLAGS_E12C)
TARGET_MDL := 0a
else
ifeq ($(CONFIG_E2K_E16C),y)
KBUILD_CFLAGS += $(CFLAGS_E16C)
KBUILD_AFLAGS += $(CFLAGS_E16C)
TARGET_MDL := 0b
else
ifeq ($(CONFIG_E2K_E2C3),y)
KBUILD_CFLAGS += $(CFLAGS_E2C3)
KBUILD_AFLAGS += $(CFLAGS_E2C3)
TARGET_MDL := 0c
else
error "Invalid e2k machine type"
endif # ifeq ($(CONFIG_E2K_E2C3),y)
endif # ifeq ($(CONFIG_E2K_E16C),y)
endif # ifeq ($(CONFIG_E2K_E12C),y)
endif # ifeq ($(CONFIG_E2K_E8C2),y)
endif # ifeq ($(CONFIG_E2K_E1CP),y)
endif # ifeq ($(CONFIG_E2K_E8C),y)
endif # ifeq ($(CONFIG_E2K_E2S),y)
endif # ifeq ($(CONFIG_E2K_ES2_RU),y)
endif # ifeq ($(CONFIG_E2K_ES2_DSP),y)
else # ! ifeq ($(CONFIG_E2K_MACHINE),y)
KBUILD_CFLAGS += $(CFLAGS_GENERIC)
KBUILD_AFLAGS += $(CFLAGS_GENERIC)
TARGET_MDL := 00
endif
KBUILD_LDFLAGS += --relaxed-e2k-machine-check
KBUILD_CFLAGS += $(cflags-y)
libs-y += arch/e2k/lib/
core-y += arch/e2k/kernel/ \
arch/e2k/mm/ \
arch/e2k/p2v/ \
arch/e2k/fast_syscalls/
core-$(CONFIG_PROTECTED_MODE) += arch/e2k/3p/
drivers-$(CONFIG_PCI) += arch/e2k/pci/
# suspend and hibernation support
drivers-$(CONFIG_PM) += arch/e2k/power/
#KVM hypervisor and guest support
core-$(CONFIG_KVM) += arch/e2k/kvm/
core-$(CONFIG_KVM_GUEST) += arch/e2k/kvm/guest/
# Elbrus common modules
core-y += arch/l/
drivers-$(CONFIG_PCI) += arch/l/pci/
boot := arch/e2k/boot
all: es2boot
MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot
.PHONY: clean archclean archmrproper archdep bootimage image zImage
es2boot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_ES2=y boot
e2sboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E2S=y boot
e8cboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E8C=y boot
e1cpboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E1CP=y boot
e8c2boot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E8C2=y CONFIG_E8C=y boot
e12cboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E12C=y boot
e16cboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E16C=y boot
e2c3boot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E2C3=y boot
image: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_BOOT=y $(objtree)/image.boot
$(Q)echo "Target mdl: $(TARGET_MDL)"; \
echo $(TARGET_MDL) | \
xxd -r -p | \
dd of=$(objtree)/image.boot bs=1 seek=258 count=1 conv=notrunc 2>/dev/null; \
echo 00000000 | xxd -r -p | \
dd of=$(objtree)/image.boot bs=1 seek=1588 count=4 conv=notrunc 2>/dev/null; \
e2k_kernel_csum=`cksum $(objtree)/image.boot | awk '{ printf "%08x\n", $$1 }'`; \
echo "Kernel image check sum: $$e2k_kernel_csum"; \
echo $$e2k_kernel_csum | \
sed 's/\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)/\7\8\5\6\3\4\1\2/' | \
xxd -r -p | \
dd of=$(objtree)/image.boot bs=1 seek=1588 count=4 conv=notrunc 2>/dev/null; \
echo 'Kernel: image.boot is ready' ' (#'`cat .version`')'
zImage: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_BOOT=y $(objtree)/zImage
$(Q)echo "Target mdl: $(TARGET_MDL)"; \
echo $(TARGET_MDL) | \
xxd -r -p | \
dd of=$(objtree)/zImage bs=1 seek=258 count=1 conv=notrunc 2>/dev/null; \
echo 00000000 | xxd -r -p | \
dd of=$(objtree)/zImage bs=1 seek=1588 count=4 conv=notrunc 2>/dev/null; \
e2k_kernel_csum=`cksum $(objtree)/zImage | awk '{ printf "%08x\n", $$1 }'`; \
echo "Kernel image check sum: $$e2k_kernel_csum"; \
echo $$e2k_kernel_csum | \
sed 's/\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)\(.\)/\7\8\5\6\3\4\1\2/' | \
xxd -r -p | \
dd of=$(objtree)/zImage bs=1 seek=1588 count=4 conv=notrunc 2>/dev/null; \
echo 'Kernel: zImage is ready' ' (#'`cat .version`')'
image.boot: bootimage
bootimage: image
archclean:
$(Q)$(MAKE) $(clean)=arch/e2k/boot
archmrproper:
archdep:
@$(MAKEBOOT) dep
install-headers:
@$(MAKEBOOT) install-headers
install-includes: include/linux/version.h arch/e2k/include FORCE
$(CONFIG_SHELL) scripts/gen-osl-include -l $(srctree) -r $(ROOT_WA)
build-install: FORCE
$(CONFIG_SHELL) scripts/gen-osl-build -l $(srctree) -m $(MODLIB)
define archhelp
echo '* image/bootimage - Kernel boot image (image.boot)'
echo ' zImage - Compressed kernel boot image (image.boot)'
echo ' install-headers - Install kernel headers in '
echo ' <basedir>/usr/include'
echo ' es2boot - Build kernel boot image with small embedded boot for es2 simulator'
echo ' e2sboot - Build kernel boot image with small embedded boot for e2s simulator'
echo ' e8cboot - Build kernel boot image with small embedded boot for e8c simulator'
echo ' e1cpboot - Build kernel boot image with small embedded boot for e1cp simulator'
echo ' e8c2boot - Build kernel boot image with small embedded boot for e8c2 simulator'
echo ' e12cboot - Build kernel boot image with small embedded boot for e12c simulator'
echo ' e16cboot - Build kernel boot image with small embedded boot for e16c simulator'
echo ' e2c3boot - Build kernel boot image with small embedded boot for e2c3 simulator'
echo ' [with_kernel=1] - When building boot, build in compressed kernel into the boot image'
endef

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arch/e2k/include/asm-l/acenv.h
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#ifndef _ASM_L_ACENV_H_
#define _ASM_L_ACENV_H_
int __acpi_acquire_global_lock(unsigned int *lock);
int __acpi_release_global_lock(unsigned int *lock);
#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
((Acq) = __acpi_release_global_lock(&facs->global_lock))
#endif /* _ASM_L_ACENV_H_ */

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arch/e2k/include/asm-l/acpi.h
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#ifndef _ASM_L_ACPI_H
#define _ASM_L_ACPI_H
/*
* Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
* Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
* Copuright (C) 2012 Evgeny Kravtsunov <kravtsunov_e@mcst.ru>
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <asm/mpspec.h>
#include <asm/irqflags.h>
#include <acpi/pdc_intel.h>
#define COMPILER_DEPENDENT_INT64 long
#define COMPILER_DEPENDENT_UINT64 unsigned long
/*
* Calling conventions:
*
* ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
* ACPI_EXTERNAL_XFACE - External ACPI interfaces
* ACPI_INTERNAL_XFACE - Internal ACPI interfaces
* ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
*/
#define ACPI_SYSTEM_XFACE
#define ACPI_EXTERNAL_XFACE
#define ACPI_INTERNAL_XFACE
#define ACPI_INTERNAL_VAR_XFACE
/* Asm macros */
#define ACPI_ASM_MACROS
#define BREAKPOINT3
#define ACPI_DISABLE_IRQS() raw_local_irq_disable()
#define ACPI_ENABLE_IRQS() raw_local_irq_enable()
#ifdef CONFIG_ACPI
#include <asm/acenv.h>
enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
IDLE_POLL};
extern int acpi_lapic;
extern int acpi_ioapic;
extern int acpi_noirq;
extern int acpi_strict;
extern int acpi_disabled;
extern int acpi_ht;
extern int acpi_pci_disabled;
extern int acpi_skip_timer_override;
extern int acpi_use_timer_override;
extern int acpi_fix_pin2_polarity;
extern u8 acpi_sci_flags;
extern int acpi_sci_override_gsi;
void acpi_pic_sci_set_trigger(unsigned int, u16);
static inline void disable_acpi(void)
{
acpi_disabled = 1;
acpi_ht = 0;
acpi_pci_disabled = 1;
acpi_noirq = 1;
}
extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
static inline void acpi_disable_pci(void)
{
acpi_pci_disabled = 1;
acpi_noirq_set();
}
/* routines for saving/restoring kernel state */
extern int acpi_save_state_mem(void);
extern void acpi_restore_state_mem(void);
extern unsigned long acpi_wakeup_address;
/*
* Check if the CPU can handle C2 and deeper
*/
static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
{
/* here check machine type taken from mptable */
return 1;
}
/*
* Elbrus won't implement _PDC as it is deprecated in ACPI4.0 in favor of _OSC
*/
static inline bool arch_has_acpi_pdc(void)
{
return 0;
}
static inline void arch_acpi_set_pdc_bits(u32 *buf)
{
return;
}
#else /* !CONFIG_ACPI */
#define acpi_lapic 0
#define acpi_ioapic 0
#define acpi_disable_cmcff 0
static inline void acpi_noirq_set(void) { }
static inline void acpi_disable_pci(void) { }
static inline void disable_acpi(void) { }
#endif /* !CONFIG_ACPI */
#define ARCH_HAS_POWER_INIT 0
#define acpi_unlazy_tlb(x)
#endif /* _ASM_L_ACPI_H */

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arch/e2k/include/asm-l/apic.h
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#ifndef _ASM_L_APIC_H
#define _ASM_L_APIC_H
#include <linux/cpumask.h>
#include <linux/errno.h>
#if 0
#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/fixmap.h>
#include <asm/msr.h>
#else
#include <linux/cpumask.h>
#include <asm/percpu.h>
#endif
#include <asm/processor.h>
#include <asm/apicdef.h>
#include <asm/hardirq.h>
#include <linux/atomic.h>
#include <asm/mpspec.h>
#include <asm-l/idle.h>
#if defined CONFIG_E2K || defined CONFIG_E90S
# define cpu_has_tsc 1
# define cpu_has_apic 1
# define cpu_has_x2apic 0
# define READ_APIC_ID() GET_APIC_ID(arch_apic_read(APIC_ID))
extern int first_system_vector;
#endif
#if 0
#define ARCH_APICTIMER_STOPS_ON_C3 1
#endif
/*
* Debugging macros
*/
#define APIC_QUIET 0
#define APIC_VERBOSE 1
#define APIC_DEBUG 2
/*
* Define the default level of output to be very little
* This can be turned up by using apic=verbose for more
* information and apic=debug for _lots_ of information.
* apic_verbosity is defined in apic.c
*/
#define apic_printk(v, s, a...) do { \
if ((v) <= apic_verbosity) \
printk(s, ##a); \
} while (0)
extern unsigned int calibration_result;
#if defined(CONFIG_L_LOCAL_APIC) && defined(CONFIG_L_X86_32)
extern void generic_apic_probe(void);
#else
static inline void generic_apic_probe(void)
{
}
#endif
#ifdef CONFIG_L_LOCAL_APIC
# define READ_APIC_ID() GET_APIC_ID(arch_apic_read(APIC_ID))
# define BOOT_READ_APIC_ID() GET_APIC_ID(boot_arch_apic_read(APIC_ID))
extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;
#if 0
extern int disable_apic;
#else
#define disable_apic 0
#endif
extern unsigned int lapic_timer_frequency;
#ifdef CONFIG_SMP
extern void __inquire_remote_apic(int apicid);
#else /* CONFIG_SMP */
static inline void __inquire_remote_apic(int apicid)
{
}
#endif /* CONFIG_SMP */
static inline void default_inquire_remote_apic(int apicid)
{
if (apic_verbosity >= APIC_DEBUG)
__inquire_remote_apic(apicid);
}
/*
* With 82489DX we can't rely on apic feature bit
* retrieved via cpuid but still have to deal with
* such an apic chip so we assume that SMP configuration
* is found from MP table (64bit case uses ACPI mostly
* which set smp presence flag as well so we are safe
* to use this helper too).
*/
static inline bool apic_from_smp_config(void)
{
return smp_found_config && !disable_apic;
}
/*
* Basic functions accessing APICs.
*/
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt/pv_ops.h>
#endif
#if 0
#ifdef CONFIG_L_X86_64
extern int is_vsmp_box(void);
#else
static inline int is_vsmp_box(void)
{
return 0;
}
#endif
#else
# define is_vsmp_box() 0
#endif
extern void xapic_wait_icr_idle(void);
extern u32 safe_xapic_wait_icr_idle(void);
extern void xapic_icr_write(u32, u32);
extern int setup_profiling_timer(unsigned int);
#if 0
static inline void native_apic_mem_write(u32 reg, u32 v)
{
volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
ASM_OUTPUT2("=r" (v), "=m" (*addr)),
ASM_OUTPUT2("0" (v), "m" (*addr)));
}
static inline u32 native_apic_mem_read(u32 reg)
{
return *((volatile u32 *)(APIC_BASE + reg));
}
#else
static inline void native_apic_mem_write(u32 reg, u32 v)
{
arch_apic_write(reg, v);
}
static inline u32 native_apic_mem_read(u32 reg)
{
return arch_apic_read(reg);
}
#endif
extern void native_apic_wait_icr_idle(void);
extern u32 native_safe_apic_wait_icr_idle(void);
extern void native_apic_icr_write(u32 low, u32 id);
extern u64 native_apic_icr_read(void);
extern int x2apic_mode;
#ifdef CONFIG_X86_X2APIC
/*
* Make previous memory operations globally visible before
* sending the IPI through x2apic wrmsr. We need a serializing instruction or
* mfence for this.
*/
static inline void x2apic_wrmsr_fence(void)
{
asm volatile("mfence" : : : "memory");
}
static inline void native_apic_msr_write(u32 reg, u32 v)
{
if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
reg == APIC_LVR)
return;
wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}
static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
{
wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
}
static inline u32 native_apic_msr_read(u32 reg)
{
u64 msr;
if (reg == APIC_DFR)
return -1;
rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
return (u32)msr;
}
static inline void native_x2apic_wait_icr_idle(void)
{
/* no need to wait for icr idle in x2apic */
return;
}
static inline u32 native_safe_x2apic_wait_icr_idle(void)
{
/* no need to wait for icr idle in x2apic */
return 0;
}
static inline void native_x2apic_icr_write(u32 low, u32 id)
{
wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
}
static inline u64 native_x2apic_icr_read(void)
{
unsigned long val;
rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
return val;
}
extern int x2apic_phys;
extern int x2apic_preenabled;
extern void check_x2apic(void);
extern void enable_x2apic(void);
extern void x2apic_icr_write(u32 low, u32 id);
static inline int x2apic_enabled(void)
{
u64 msr;
if (!cpu_has_x2apic)
return 0;
rdmsrl(MSR_IA32_APICBASE, msr);
if (msr & X2APIC_ENABLE)
return 1;
return 0;
}
#define x2apic_supported() (cpu_has_x2apic)
static inline void x2apic_force_phys(void)
{
x2apic_phys = 1;
}
#else
static inline void disable_x2apic(void)
{
}
static inline void check_x2apic(void)
{
}
static inline void enable_x2apic(void)
{
}
static inline int x2apic_enabled(void)
{
return 0;
}
static inline void x2apic_force_phys(void)
{
}
#define nox2apic 0
#define x2apic_preenabled 0
#define x2apic_supported() 0
#endif
extern void enable_IR_x2apic(void);
extern int get_physical_broadcast(void);
extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
#ifdef CONFIG_E2K
extern void clear_local_APIC(void);
#endif /* CONFIG_E2K */
extern void lapic_shutdown(void);
extern int verify_local_APIC(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void end_local_APIC_setup(void);
extern void bsp_end_local_APIC_setup(void);
extern void init_apic_mappings(void);
void register_lapic_address(unsigned long address);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);
extern int apic_force_enable(unsigned long addr);
/*
* On 32bit this is mach-xxx local
*/
#ifdef CONFIG_L_X86_64
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
return 0;
}
#endif
extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
#else /* !CONFIG_L_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok 1
static inline void init_apic_mappings(void) { }
static inline void disable_local_APIC(void) { }
#ifdef CONFIG_E2K
static inline void clear_local_APIC(void) { }
#endif /* CONFIG_E2K */
# define setup_boot_APIC_clock x86_init_noop
# define setup_secondary_APIC_clock x86_init_noop
#endif /* !CONFIG_L_LOCAL_APIC */
#ifdef CONFIG_L_X86_64
#define SET_APIC_ID(x) (apic->set_apic_id(x))
#else
#endif
/*
* Copyright 2004 James Cleverdon, IBM.
* Subject to the GNU Public License, v.2
*
* Generic APIC sub-arch data struct.
*
* Hacked for x86-64 by James Cleverdon from i386 architecture code by
* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
* James Cleverdon.
*/
struct apic {
char *name;
int (*probe)(void);
int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
int (*apic_id_valid)(int apicid);
int (*apic_id_registered)(void);
u32 irq_delivery_mode;
u32 irq_dest_mode;
const struct cpumask *(*target_cpus)(void);
int disable_esr;
int dest_logical;
unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
unsigned long (*check_apicid_present)(int apicid);
void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
const struct cpumask *mask);
void (*init_apic_ldr)(void);
void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
void (*setup_apic_routing)(void);
int (*multi_timer_check)(int apic, int irq);
int (*cpu_present_to_apicid)(int mps_cpu);
void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
void (*setup_portio_remap)(void);
int (*check_phys_apicid_present)(int phys_apicid);
void (*enable_apic_mode)(void);
int (*phys_pkg_id)(int cpuid_apic, int index_msb);
/*
* When one of the next two hooks returns 1 the apic
* is switched to this. Essentially they are additional
* probe functions:
*/
int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
unsigned int (*get_apic_id)(unsigned long x);
unsigned long (*set_apic_id)(unsigned int id);
unsigned long apic_id_mask;
int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
const struct cpumask *andmask,
unsigned int *apicid);
/* ipi */
void (*send_IPI_mask)(const struct cpumask *mask, int vector);
void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
int vector);
void (*send_IPI_allbutself)(int vector);
void (*send_IPI_all)(int vector);
void (*send_IPI_self)(int vector);
/* wakeup_secondary_cpu */
int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
int trampoline_phys_low;
int trampoline_phys_high;
void (*wait_for_init_deassert)(atomic_t *deassert);
void (*smp_callin_clear_local_apic)(void);
void (*inquire_remote_apic)(int apicid);
/* apic ops */
u32 (*read)(u32 reg);
void (*write)(u32 reg, u32 v);
/*
* ->eoi_write() has the same signature as ->write().
*
* Drivers can support both ->eoi_write() and ->write() by passing the same
* callback value. Kernel can override ->eoi_write() and fall back
* on write for EOI.
*/
void (*eoi_write)(u32 reg, u32 v);
u64 (*icr_read)(void);
void (*icr_write)(u32 low, u32 high);
void (*wait_icr_idle)(void);
u32 (*safe_wait_icr_idle)(void);
#ifdef CONFIG_L_X86_32
/*
* Called very early during boot from get_smp_config(). It should
* return the logical apicid. x86_[bios]_cpu_to_apicid is
* initialized before this function is called.
*
* If logical apicid can't be determined that early, the function
* may return BAD_APICID. Logical apicid will be configured after
* init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
* won't be applied properly during early boot in this case.
*/
int (*x86_32_early_logical_apicid)(int cpu);
/*
* Optional method called from setup_local_APIC() after logical
* apicid is guaranteed to be known to initialize apicid -> node
* mapping if NUMA initialization hasn't done so already. Don't
* add new users.
*/
int (*x86_32_numa_cpu_node)(int cpu);
#endif
};
/*
* Pointer to the local APIC driver in use on this system (there's
* always just one such driver in use - the kernel decides via an
* early probing process which one it picks - and then sticks to it):
*/
extern struct apic *apic;
/*
* APIC drivers are probed based on how they are listed in the .apicdrivers
* section. So the order is important and enforced by the ordering
* of different apic driver files in the Makefile.
*
* For the files having two apic drivers, we use apic_drivers()
* to enforce the order with in them.
*/
#define apic_driver(sym) \
static const struct apic *__apicdrivers_##sym __used \
__aligned(sizeof(struct apic *)) \
__section(.apicdrivers) = { &sym }
#define apic_drivers(sym1, sym2) \
static struct apic *__apicdrivers_##sym1##sym2[2] __used \
__aligned(sizeof(struct apic *)) \
__section(.apicdrivers) = { &sym1, &sym2 }
extern struct apic *__apicdrivers[], *__apicdrivers_end[];
/*
* APIC functionality to boot other CPUs - only used on SMP:
*/
#ifdef CONFIG_SMP
extern atomic_t init_deasserted;
extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
#endif
#ifdef CONFIG_L_LOCAL_APIC
static inline u32 apic_read(u32 reg)
{
return apic->read(reg);
}
static inline void apic_write(u32 reg, u32 val)
{
apic->write(reg, val);
}
static inline void apic_eoi(void)
{
apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
}
static inline u64 apic_icr_read(void)
{
return apic->icr_read();
}
static inline void apic_icr_write(u32 low, u32 high)
{
apic->icr_write(low, high);
}
static inline void apic_wait_icr_idle(void)
{
apic->wait_icr_idle();
}
static inline u32 safe_apic_wait_icr_idle(void)
{
return apic->safe_wait_icr_idle();
}
extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
#else /* CONFIG_L_LOCAL_APIC */
static inline u32 apic_read(u32 reg) { return 0; }
static inline void apic_write(u32 reg, u32 val) { }
static inline void apic_eoi(void) { }
static inline u64 apic_icr_read(void) { return 0; }
static inline void apic_icr_write(u32 low, u32 high) { }
static inline void apic_wait_icr_idle(void) { }
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
#endif /* CONFIG_L_LOCAL_APIC */
static inline void ack_APIC_irq(void)
{
/*
* ack_APIC_irq() actually gets compiled as a single instruction
* ... yummie.
*/
apic_eoi();
}
static inline unsigned default_get_apic_id(unsigned long x)
{
unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
if (APIC_XAPIC(ver)/* || boot_cpu_has(X86_FEATURE_EXTD_APICID)*/)
return (x >> 24) & 0xFF;
else
return (x >> 24) & 0x0F;
}
/*
* Warm reset vector default position:
*/
#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
#ifdef CONFIG_L_X86_64
extern int default_acpi_madt_oem_check(char *, char *);
extern void apic_send_IPI_self(int vector);
#endif
static inline void default_wait_for_init_deassert(atomic_t *deassert)
{
while (!atomic_read(deassert))
cpu_relax();
return;
}
extern void generic_bigsmp_probe(void);
#ifdef CONFIG_L_LOCAL_APIC
#if 0
#include <asm/smp.h>
#endif
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
static inline const struct cpumask *default_target_cpus(void)
{
#ifdef CONFIG_SMP
return cpu_online_mask;
#else
return cpumask_of(0);
#endif
}
static inline const struct cpumask *online_target_cpus(void)
{
return cpu_online_mask;
}
DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid);
#ifdef CONFIG_SMP
#define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu)
#else
#define cpu_physical_id(cpu) boot_cpu_physical_apicid
#endif
static inline unsigned int read_apic_id(void)
{
unsigned int reg;
reg = apic_read(APIC_ID);
return apic->get_apic_id(reg);
}
static inline int default_apic_id_valid(int apicid)
{
return (apicid < 255);
}
extern void default_setup_apic_routing(void);
extern struct apic apic_noop;
#ifdef CONFIG_L_X86_32
static inline int noop_x86_32_early_logical_apicid(int cpu)
{
return BAD_APICID;
}
/*
* Set up the logical destination ID.
*
* Intel recommends to set DFR, LDR and TPR before enabling
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
* document number 292116). So here it goes...
*/
extern void default_init_apic_ldr(void);
static inline int default_apic_id_registered(void)
{
return physid_isset(read_apic_id(), phys_cpu_present_map);
}
static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
}
#endif
static inline int
flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
const struct cpumask *andmask,
unsigned int *apicid)
{
unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
cpumask_bits(andmask)[0] &
cpumask_bits(cpu_online_mask)[0] &
APIC_ALL_CPUS;
if (likely(cpu_mask)) {
*apicid = (unsigned int)cpu_mask;
return 0;
} else {
return -EINVAL;
}
}
extern int
default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
const struct cpumask *andmask,
unsigned int *apicid);
static inline void
flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
const struct cpumask *mask)
{
/* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
* priority interrupt delivery mode.
*
* In particular there was a hyperthreading cpu observed to
* deliver interrupts to the wrong hyperthread when only one
* hyperthread was specified in the interrupt desitination.
*/
cpumask_clear(retmask);
cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
}
static inline void
default_vector_allocation_domain(int cpu, struct cpumask *retmask,
const struct cpumask *mask)
{
cpumask_copy(retmask, cpumask_of(cpu));
}
static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
{
return physid_isset(apicid, *map);
}
static inline unsigned long default_check_apicid_present(int bit)
{
return physid_isset(bit, phys_cpu_present_map);
}
static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
{
*retmap = *phys_map;
}
static inline int __default_cpu_present_to_apicid(int mps_cpu)
{
if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
else
return BAD_APICID;
}
static inline int
__default_check_phys_apicid_present(int phys_apicid)
{
return physid_isset(phys_apicid, phys_cpu_present_map);
}
/* #ifdef CONFIG_L_X86_32 */
#if 1
static inline int default_cpu_present_to_apicid(int mps_cpu)
{
return __default_cpu_present_to_apicid(mps_cpu);
}
static inline int
default_check_phys_apicid_present(int phys_apicid)
{
return __default_check_phys_apicid_present(phys_apicid);
}
#else
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
#endif
#endif /* CONFIG_L_LOCAL_APIC */
static inline void entering_irq(void)
{
l_irq_enter();
exit_idle();
}
static inline void entering_ack_irq(void)
{
entering_irq();
ack_APIC_irq();
}
static inline void exiting_irq(void)
{
l_irq_exit();
}
static inline void exiting_ack_irq(void)
{
l_irq_exit();
/* Ack only at the end to avoid potential reentry */
ack_APIC_irq();
}
extern void ioapic_zap_locks(void);
struct irq_data;
extern void ack_apic_edge(struct irq_data *data);
#endif /* _ASM_L_APIC_H */

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arch/e2k/include/asm-l/apicdef.h
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#ifndef _ASM_L_APICDEF_H
#define _ASM_L_APICDEF_H
/*
* Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
*
* Alan Cox <Alan.Cox@linux.org>, 1995.
* Ingo Molnar <mingo@redhat.com>, 1999, 2000
*/
#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
#define APIC_DEFAULT_PHYS_BASE 0xfee00000
/*
* This is the IO-APIC register space as specified
* by Intel docs:
*/
#define IO_APIC_SLOT_SIZE 1024
#define APIC_REGS_SIZE 0x1000
#define APIC_BSP 0x10
#define APIC_BSP_ENABLE 0x00000800
#define APIC_BSP_IS_BSP 0x00000100
#define APIC_ENABLE(x) ((x) & APIC_BSP_ENABLE)
#define BootStrap(x) ((x) & APIC_BSP_IS_BSP)
#define APIC_ID 0x20
#define APIC_ID_SHIFT 24
#define APIC_ID_SIZE 8
#define APIC_ID_BIT_MASK ((1 << APIC_ID_SIZE) - 1)
#define APIC_ID_MASK (APIC_ID_BIT_MASK << \
APIC_ID_SHIFT)
#define GET_APIC_ID(x) (((x) >> APIC_ID_SHIFT) & \
APIC_ID_BIT_MASK)
#define APIC_LVR 0x30
#define APIC_LVR_MASK 0xFF00FF
#define APIC_LVR_DIRECTED_EOI (1 << 24)
#define APIC_MAXLVT 0x03
#define APIC_VERSION 0x10
#define GET_APIC_VERSION(x) ((x) & 0xFFu)
#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
#define SET_APIC_VERSION(x) ((x) & 0xFF)
#define SET_APIC_MAXLVT(x) (((x) & 0xff) << 16)
#if 0
# define APIC_INTEGRATED(x) ((x) & 0xF0u)
#else
# define APIC_INTEGRATED(x) (1)
#endif
#define APIC_XAPIC(x) ((x) >= 0x14)
#define APIC_EXT_SPACE(x) ((x) & 0x80000000)
#define APIC_TASKPRI 0x80
#define APIC_TPRI_MASK 0xFFu
#define APIC_ARBPRI 0x90
#define APIC_ARBPRI_MASK 0xFFu
#define APIC_PROCPRI 0xA0
#define APIC_EOI 0xB0
#define APIC_EOI_ACK 0x0
#define APIC_RRR 0xC0
#define APIC_LDR 0xD0
#define APIC_LDR_MASK (0xFFu << 24)
#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
#define SET_APIC_LOGICAL_ID(x) (((x) << 24))
#define APIC_ALL_CPUS 0xFFu
#define APIC_DFR 0xE0
#define GET_APIC_DLVR_MODE(x) (((x) >> 28) & 0xF)
#define APIC_DFR_CLUSTER 0x0FFFFFFFul
#define APIC_DFR_FLAT 0xFFFFFFFFul
#define APIC_SPIV 0xF0
#define APIC_SPIV_DIRECTED_EOI (1 << 12)
#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
#define APIC_SPIV_APIC_ENABLED (1 << 8)
#define APIC_SOFT_ENABLED(x) ((x) & APIC_SPIV_APIC_ENABLED)
#define APIC_FOCUS_DISABLED(x) ((x) & APIC_SPIV_FOCUS_DISABLED)
#define APIC_SPIV_SPURIOUS_VECT 0x000FF
#define GET_SPURIOUS_VECTOR(x) ((x) & APIC_SPIV_SPURIOUS_VECT)
#define SET_SPURIOUS_VECTOR(x) ((x) & APIC_SPIV_SPURIOUS_VECT)
#define APIC_ISR 0x100
#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
#define APIC_TMR 0x180
#define APIC_IRR 0x200
#define APIC_ESR 0x280
#define APIC_ESR_SEND_CS 0x00001
#define APIC_ESR_RECV_CS 0x00002
#define APIC_ESR_SEND_ACC 0x00004
#define APIC_ESR_RECV_ACC 0x00008
#define APIC_ESR_SENDILL 0x00020
#define APIC_ESR_RECVILL 0x00040
#define APIC_ESR_ILLREGA 0x00080
#define APIC_LVTCMCI 0x2f0
#define APIC_ICR 0x300
#define APIC_DEST_SELF 0x40000
#define APIC_DEST_ALLINC 0x80000
#define APIC_DEST_ALLBUT 0xC0000
#define APIC_ICR_RR_MASK 0x30000
#define APIC_ICR_RR_INVALID 0x00000
#define APIC_ICR_RR_INPROG 0x10000
#define APIC_ICR_RR_VALID 0x20000
#define APIC_INT_LEVELTRIG 0x08000
#define APIC_INT_ASSERT 0x04000
#define APIC_ICR_BUSY 0x01000
#define APIC_DEST_LOGICAL 0x00800
#define APIC_DEST_PHYSICAL 0x00000
#define APIC_DM_FIXED 0x00000
#define APIC_DM_LOWEST 0x00100
#define APIC_DM_SMI 0x00200
#define APIC_DM_REMRD 0x00300
#define APIC_DM_NMI 0x00400
#define APIC_DM_INIT 0x00500
#define APIC_DM_STARTUP 0x00600
#define APIC_DM_EXTINT 0x00700
#define APIC_VECTOR_MASK 0x000FF
#define APIC_ICR2 0x310
#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
#define SET_APIC_DEST_FIELD(x) ((x) << 24)
#define APIC_LVTT 0x320
#define APIC_LVTTHMR 0x330
#define APIC_LVTPC 0x340
#define APIC_LVT0 0x350
#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
#define SET_APIC_TIMER_BASE(x) (((x) << 18))
#define APIC_TIMER_BASE_CLKIN 0x0
#define APIC_TIMER_BASE_TMBASE 0x1
#define APIC_TIMER_BASE_DIV 0x2
#define APIC_LVT_TIMER_PERIODIC (1 << 17)
#define APIC_LVT_MASKED (1 << 16)
#define APIC_LVT_LEVEL_TRIGGER (1 << 15)
#define APIC_LVT_REMOTE_IRR (1 << 14)
#define APIC_INPUT_POLARITY (1 << 13)
#define APIC_SEND_PENDING (1 << 12)
#define APIC_MODE_MASK 0x700
#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
#define APIC_MODE_FIXED 0x0
#define APIC_MODE_NMI 0x4
#define APIC_MODE_EXTINT 0x7
#define APIC_LVT1 0x360
#define APIC_LVTERR 0x370
#define APIC_TMICT 0x380
#define APIC_TMCCT 0x390
#define APIC_TDCR 0x3E0
#define APIC_SELF_IPI 0x3F0
#define APIC_TDR_DIV_TMBASE (1 << 2)
#define APIC_TDR_DIV_1 0xB
#define APIC_TDR_DIV_2 0x0
#define APIC_TDR_DIV_4 0x1
#define APIC_TDR_DIV_8 0x2
#define APIC_TDR_DIV_16 0x3
#define APIC_TDR_DIV_32 0x8
#define APIC_TDR_DIV_64 0x9
#define APIC_TDR_DIV_128 0xA
#if 0
#define APIC_EFEAT 0x400
#define APIC_ECTRL 0x410
#define APIC_EILVTn(n) (0x500 + 0x10 * n)
#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
#define APIC_EILVT_NR_AMD_10H 4
#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
#define APIC_EILVT_MSG_FIX 0x0
#define APIC_EILVT_MSG_SMI 0x2
#define APIC_EILVT_MSG_NMI 0x4
#define APIC_EILVT_MSG_EXT 0x7
#define APIC_EILVT_MASKED (1 << 16)
#endif
#define APIC_NM_TIMER_LVTT 0xf00
#define APIC_NM_TIMER_INIT_COUNT 0xf10
#define APIC_NM_TIMER_CURRENT_COUNT 0xf20
#define APIC_NM_TIMER_DIVIDER 0xf30
#define APIC_LVT2 0xf40
#define APIC_LVT3 0xf50
#define APIC_DSP APIC_LVT3
#define APIC_LVT4 0xf60
#define APIC_M_ERM 0xfc0
#define APIC_NM_WATCHDOG 0x80000000
#define APIC_NM_WATCHDOG1 0x40000000
#define APIC_NM_SPECIAL 0x20000
#define APIC_NM_TIMER 0x10000
#define APIC_NM_NMI_DEBUG_MASK 0x8000
#define APIC_NM_INTQLAPIC_MASK 0x4000
#define APIC_NM_INT_VIOLAT_MASK 0x2000
#define APIC_NM 0xfe0
#define APIC_NM_BIT_MASK 0x7ff00
#define APIC_NM_PCI 0x40000
#define APIC_NM_SPECIAL 0x20000
#define APIC_NM_TIMER 0x10000
#define APIC_NM_NMI_DEBUG 0x8000
#define APIC_NM_INTQLAPIC 0x4000
#define APIC_NM_INT_VIOLAT 0x2000
#define APIC_NM_STARTUP 0x1000
#define APIC_NM_INIT 0x0800
#define APIC_NM_NMI 0x0400
#define APIC_NM_SMI 0x0200
#define APIC_NM_EXTINT 0x0100
#define APIC_NM_STARTUP_ADDR 0x00ff
#define GET_APIC_STARTUP_ADDR(x) ((x) & APIC_NM_STARTUP_ADDR)
#define APIC_NM_MASK(x) ((x) & APIC_NM_BIT_MASK)
#define GET_APIC_NM_BITS(x) (((x) & APIC_NM_BIT_MASK) >> 9)
#define APIC_NM_IS_STRATUP(x) ((x) & APIC_NM_STARTUP)
#define APIC_NM_IS_INIT(x) ((x) & APIC_NM_INIT)
#define APIC_NM_IS_NMI(x) ((x) & APIC_NM_NMI)
#define APIC_NM_IS_SMI(x) ((x) & APIC_NM_SMI)
#define APIC_VECT 0xff0
#define APIC_VECT_VECTOR_MASK 0x000000ff
#define APIC_VECT_EXTINT (1 << 31)
#define APIC_VECT_VECTOR(x) ((x) & APIC_VECT_VECTOR_MASK)
#define APIC_VECT_IS_EXTINT(x) ((x) & APIC_VECT_EXTINT)
#if 0
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR 0x800
#else
#define APIC_BASE 0x00000000fee00000UL
#endif
#define X2APIC_ENABLE (1UL << 10)
/*
* a maximum number of IO-APICs depends on the following:
* each IO link can have IOHUB with IO-APIC
* each node can have embedded IO-APIC
*/
#define MAX_IO_APICS (MAX_NUMIOLINKS + MAX_NUMNODES)
#define MAX_LOCAL_APIC MAX_APICS
#if 0
#ifdef CONFIG_L_X86_32
# define MAX_IO_APICS 64
# define MAX_LOCAL_APIC 256
#else
# define MAX_IO_APICS 128
# define MAX_LOCAL_APIC 32768
#endif
#endif
/*
* All x86-64 systems are xAPIC compatible.
* In the following, "apicid" is a physical APIC ID.
*/
#define XAPIC_DEST_CPUS_SHIFT 4
#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
#if 0
#ifndef __ASSEMBLY__
/*
* the local APIC register structure, memory mapped. Not terribly well
* tested, but we might eventually use this one in the future - the
* problem why we cannot use it right now is the P5 APIC, it has an
* errata which cannot take 8-bit reads and writes, only 32-bit ones ...
*/
#define u32 unsigned int
struct local_apic {
/*000*/ struct { u32 __reserved[4]; } __reserved_01;
/*010*/ struct { u32 __reserved[4]; } __reserved_02;
/*020*/ struct { /* APIC ID Register */
u32 __reserved_1 : 24,
phys_apic_id : 4,
__reserved_2 : 4;
u32 __reserved[3];
} id;
/*030*/ const
struct { /* APIC Version Register */
u32 version : 8,
__reserved_1 : 8,
max_lvt : 8,
__reserved_2 : 8;
u32 __reserved[3];
} version;
/*040*/ struct { u32 __reserved[4]; } __reserved_03;
/*050*/ struct { u32 __reserved[4]; } __reserved_04;
/*060*/ struct { u32 __reserved[4]; } __reserved_05;
/*070*/ struct { u32 __reserved[4]; } __reserved_06;
/*080*/ struct { /* Task Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} tpr;
/*090*/ const
struct { /* Arbitration Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} apr;
/*0A0*/ const
struct { /* Processor Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} ppr;
/*0B0*/ struct { /* End Of Interrupt Register */
u32 eoi;
u32 __reserved[3];
} eoi;
/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
/*0D0*/ struct { /* Logical Destination Register */
u32 __reserved_1 : 24,
logical_dest : 8;
u32 __reserved_2[3];
} ldr;
/*0E0*/ struct { /* Destination Format Register */
u32 __reserved_1 : 28,
model : 4;
u32 __reserved_2[3];
} dfr;
/*0F0*/ struct { /* Spurious Interrupt Vector Register */
u32 spurious_vector : 8,
apic_enabled : 1,
focus_cpu : 1,
__reserved_2 : 22;
u32 __reserved_3[3];
} svr;
/*100*/ struct { /* In Service Register */
/*170*/ u32 bitfield;
u32 __reserved[3];
} isr [8];
/*180*/ struct { /* Trigger Mode Register */
/*1F0*/ u32 bitfield;
u32 __reserved[3];
} tmr [8];
/*200*/ struct { /* Interrupt Request Register */
/*270*/ u32 bitfield;
u32 __reserved[3];
} irr [8];
/*280*/ union { /* Error Status Register */
struct {
u32 send_cs_error : 1,
receive_cs_error : 1,
send_accept_error : 1,
receive_accept_error : 1,
__reserved_1 : 1,
send_illegal_vector : 1,
receive_illegal_vector : 1,
illegal_register_address : 1,
__reserved_2 : 24;
u32 __reserved_3[3];
} error_bits;
struct {
u32 errors;
u32 __reserved_3[3];
} all_errors;
} esr;
/*290*/ struct { u32 __reserved[4]; } __reserved_08;
/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
/*300*/ struct { /* Interrupt Command Register 1 */
u32 vector : 8,
delivery_mode : 3,
destination_mode : 1,
delivery_status : 1,
__reserved_1 : 1,
level : 1,
trigger : 1,
__reserved_2 : 2,
shorthand : 2,
__reserved_3 : 12;
u32 __reserved_4[3];
} icr1;
/*310*/ struct { /* Interrupt Command Register 2 */
union {
u32 __reserved_1 : 24,
phys_dest : 4,
__reserved_2 : 4;
u32 __reserved_3 : 24,
logical_dest : 8;
} dest;
u32 __reserved_4[3];
} icr2;
/*320*/ struct { /* LVT - Timer */
u32 vector : 8,
__reserved_1 : 4,
delivery_status : 1,
__reserved_2 : 3,
mask : 1,
timer_mode : 1,