linux/arch/arm/include/asm/arch_timer.h

#ifndef __ASMARM_ARCH_TIMER_H
#define __ASMARM_ARCH_TIMER_H

#include <linux/ioport.h>

struct arch_timer {
	struct resource	res[2];
};

#ifdef CONFIG_ARM_ARCH_TIMER
int arch_timer_register(struct arch_timer *);
int arch_timer_sched_clock_init(void);
int arch_timer_of_register(void);
#else
static inline int arch_timer_register(struct arch_timer *at)
{
	return -ENXIO;
}

static inline int arch_timer_of_register(void)
{
	return -ENXIO;
}

static inline int arch_timer_sched_clock_init(void)
{
	return -ENXIO;
}
#endif

#endif
ARM: local timers: Add A15 architected timer support Add support for the A15 generic timer and clocksource. As the timer generates interrupts on a different PPI depending on the execution mode (normal or secure), it is possible to register two different PPIs. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2012-01-11 18:25:17 +01:00			`#ifndef __ASMARM_ARCH_TIMER_H`
			`#define __ASMARM_ARCH_TIMER_H`

			`#include <linux/ioport.h>`

			`struct arch_timer {`
			`struct resource res[2];`
			`};`

			`#ifdef CONFIG_ARM_ARCH_TIMER`
			`int arch_timer_register(struct arch_timer *);`
ARM: architected timers: Add A15 specific sched_clock implementation Provide an A15 sched_clock implementation using the virtual counter, which is thought to be more useful than the physical one in a virtualised environment, as it can offset the time spent in another VM or the hypervisor. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2011-01-14 16:32:36 +01:00			`int arch_timer_sched_clock_init(void);`
ARM: architected timers: add DT support Add runtime DT support and documentation for the Cortex A7/A15 architected timers. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2012-01-19 14:53:50 +01:00			`int arch_timer_of_register(void);`
ARM: local timers: Add A15 architected timer support Add support for the A15 generic timer and clocksource. As the timer generates interrupts on a different PPI depending on the execution mode (normal or secure), it is possible to register two different PPIs. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2012-01-11 18:25:17 +01:00			`#else`
			`static inline int arch_timer_register(struct arch_timer *at)`
			`{`
			`return -ENXIO;`
			`}`
ARM: architected timers: Add A15 specific sched_clock implementation Provide an A15 sched_clock implementation using the virtual counter, which is thought to be more useful than the physical one in a virtualised environment, as it can offset the time spent in another VM or the hypervisor. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2011-01-14 16:32:36 +01:00
ARM: architected timers: add DT support Add runtime DT support and documentation for the Cortex A7/A15 architected timers. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2012-01-19 14:53:50 +01:00			`static inline int arch_timer_of_register(void)`
			`{`
			`return -ENXIO;`
			`}`

ARM: architected timers: Add A15 specific sched_clock implementation Provide an A15 sched_clock implementation using the virtual counter, which is thought to be more useful than the physical one in a virtualised environment, as it can offset the time spent in another VM or the hypervisor. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2011-01-14 16:32:36 +01:00			`static inline int arch_timer_sched_clock_init(void)`
			`{`
			`return -ENXIO;`
			`}`
ARM: local timers: Add A15 architected timer support Add support for the A15 generic timer and clocksource. As the timer generates interrupts on a different PPI depending on the execution mode (normal or secure), it is possible to register two different PPIs. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2012-01-11 18:25:17 +01:00			`#endif`

			`#endif`