2011-02-16 13:39:16 +01:00
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/*
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* Freescale MXS I2C bus driver
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*
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2012-10-12 12:55:16 +02:00
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* Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
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2011-02-16 13:39:16 +01:00
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*
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* based on a (non-working) driver which was:
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*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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2011-08-31 20:37:50 +02:00
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#include <linux/stmp_device.h>
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2012-05-12 07:43:32 +02:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2012-08-24 05:44:31 +02:00
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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2011-02-16 13:39:16 +01:00
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#define DRIVER_NAME "mxs-i2c"
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#define MXS_I2C_CTRL0 (0x00)
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#define MXS_I2C_CTRL0_SET (0x04)
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#define MXS_I2C_CTRL0_SFTRST 0x80000000
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2013-01-24 13:56:21 +01:00
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#define MXS_I2C_CTRL0_RUN 0x20000000
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2011-02-16 13:39:16 +01:00
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#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
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#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
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#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
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#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
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#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
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#define MXS_I2C_CTRL0_DIRECTION 0x00010000
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#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
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2012-07-09 18:22:53 +02:00
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#define MXS_I2C_TIMING0 (0x10)
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#define MXS_I2C_TIMING1 (0x20)
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#define MXS_I2C_TIMING2 (0x30)
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2011-02-16 13:39:16 +01:00
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#define MXS_I2C_CTRL1 (0x40)
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#define MXS_I2C_CTRL1_SET (0x44)
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#define MXS_I2C_CTRL1_CLR (0x48)
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2013-04-15 02:16:55 +02:00
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#define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
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2011-02-16 13:39:16 +01:00
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#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
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#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
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#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
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#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
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#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
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#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
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#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
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#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
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2013-04-15 02:16:54 +02:00
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#define MXS_I2C_STAT (0x50)
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#define MXS_I2C_STAT_BUS_BUSY 0x00000800
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#define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
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2013-01-24 13:56:21 +01:00
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#define MXS_I2C_DATA (0xa0)
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#define MXS_I2C_DEBUG0 (0xb0)
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#define MXS_I2C_DEBUG0_CLR (0xb8)
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#define MXS_I2C_DEBUG0_DMAREQ 0x80000000
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2011-02-16 13:39:16 +01:00
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#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
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MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
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MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
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MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
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MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
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MXS_I2C_CTRL1_SLAVE_IRQ)
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#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
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MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION | \
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MXS_I2C_CTRL0_XFER_COUNT(1))
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#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION)
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#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
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MXS_I2C_CTRL0_MASTER_MODE)
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2013-09-30 01:23:53 +02:00
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enum mxs_i2c_devtype {
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MXS_I2C_UNKNOWN = 0,
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MXS_I2C_V1,
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MXS_I2C_V2,
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};
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2011-02-16 13:39:16 +01:00
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/**
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* struct mxs_i2c_dev - per device, private MXS-I2C data
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*
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* @dev: driver model device node
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2013-09-30 01:23:53 +02:00
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* @dev_type: distinguish i.MX23/i.MX28 features
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2011-02-16 13:39:16 +01:00
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* @regs: IO registers pointer
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* @cmd_complete: completion object for transaction wait
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* @cmd_err: error code for last transaction
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* @adapter: i2c subsystem adapter node
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*/
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struct mxs_i2c_dev {
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struct device *dev;
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2013-09-30 01:23:53 +02:00
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enum mxs_i2c_devtype dev_type;
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2011-02-16 13:39:16 +01:00
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void __iomem *regs;
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struct completion cmd_complete;
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2013-01-08 01:32:06 +01:00
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int cmd_err;
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2011-02-16 13:39:16 +01:00
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struct i2c_adapter adapter;
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2012-11-30 18:48:35 +01:00
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uint32_t timing0;
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uint32_t timing1;
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2013-07-05 18:28:00 +02:00
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uint32_t timing2;
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2012-08-24 05:44:31 +02:00
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/* DMA support components */
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2013-07-05 18:28:00 +02:00
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struct dma_chan *dmach;
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2012-08-24 05:44:31 +02:00
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uint32_t pio_data[2];
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uint32_t addr_data;
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struct scatterlist sg_io[2];
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bool dma_read;
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2011-02-16 13:39:16 +01:00
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};
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2013-07-11 03:19:28 +02:00
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static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
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2011-02-16 13:39:16 +01:00
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{
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2013-07-11 03:19:28 +02:00
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int ret = stmp_reset_block(i2c->regs);
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if (ret)
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return ret;
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2012-07-09 18:22:53 +02:00
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2012-11-30 18:48:35 +01:00
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/*
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* Configure timing for the I2C block. The I2C TIMING2 register has to
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* be programmed with this particular magic number. The rest is derived
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* from the XTAL speed and requested I2C speed.
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*
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* For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
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*/
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writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
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writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
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2013-07-05 18:28:00 +02:00
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writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
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2012-07-09 18:22:53 +02:00
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2011-02-16 13:39:16 +01:00
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writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
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2013-07-11 03:19:28 +02:00
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return 0;
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2011-02-16 13:39:16 +01:00
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}
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2012-08-24 05:44:31 +02:00
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static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
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{
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if (i2c->dma_read) {
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dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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} else {
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dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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}
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}
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static void mxs_i2c_dma_irq_callback(void *param)
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{
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struct mxs_i2c_dev *i2c = param;
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complete(&i2c->cmd_complete);
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mxs_i2c_dma_finish(i2c);
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}
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static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msg, uint32_t flags)
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{
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struct dma_async_tx_descriptor *desc;
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struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
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if (msg->flags & I2C_M_RD) {
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i2c->dma_read = 1;
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i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
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/*
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* SELECT command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[0],
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto select_init_pio_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
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dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto select_init_dma_fail;
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}
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/*
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* READ command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
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MXS_I2C_CTRL0_XFER_COUNT(msg->len);
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[1],
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1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto select_init_dma_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
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dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto read_init_dma_fail;
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}
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} else {
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i2c->dma_read = 0;
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i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
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/*
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* WRITE command.
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*/
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/* Queue the PIO register write transfer. */
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i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
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MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
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desc = dmaengine_prep_slave_sg(i2c->dmach,
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(struct scatterlist *)&i2c->pio_data[0],
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get PIO reg. write descriptor.\n");
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goto write_init_pio_fail;
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}
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/* Queue the DMA data transfer. */
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sg_init_table(i2c->sg_io, 2);
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sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
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sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
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dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(i2c->dev,
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"Failed to get DMA data write descriptor.\n");
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goto write_init_dma_fail;
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}
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}
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/*
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* The last descriptor must have this callback,
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* to finish the DMA transaction.
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*/
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desc->callback = mxs_i2c_dma_irq_callback;
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desc->callback_param = i2c;
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/* Start the transfer. */
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dmaengine_submit(desc);
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dma_async_issue_pending(i2c->dmach);
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return 0;
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/* Read failpath. */
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read_init_dma_fail:
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dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
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select_init_dma_fail:
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dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
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select_init_pio_fail:
|
2012-11-18 06:25:07 +01:00
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dmaengine_terminate_all(i2c->dmach);
|
2012-08-24 05:44:31 +02:00
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return -EINVAL;
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/* Write failpath. */
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write_init_dma_fail:
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dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
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write_init_pio_fail:
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2012-11-18 06:25:07 +01:00
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dmaengine_terminate_all(i2c->dmach);
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2012-08-24 05:44:31 +02:00
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return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c)
|
|
|
|
{
|
|
|
|
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
|
|
|
|
|
|
|
|
while (!(readl(i2c->regs + MXS_I2C_DEBUG0) &
|
|
|
|
MXS_I2C_DEBUG0_DMAREQ)) {
|
|
|
|
if (time_after(jiffies, timeout))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
cond_resched();
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-15 02:16:54 +02:00
|
|
|
static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last)
|
2013-01-24 13:56:21 +01:00
|
|
|
{
|
|
|
|
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We do not use interrupts in the PIO mode. Due to the
|
|
|
|
* maximum transfer length being 8 bytes in PIO mode, the
|
|
|
|
* overhead of interrupt would be too large and this would
|
|
|
|
* neglect the gain from using the PIO mode.
|
|
|
|
*/
|
|
|
|
|
|
|
|
while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
|
|
|
|
MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
|
|
|
|
if (time_after(jiffies, timeout))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
cond_resched();
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
|
|
|
|
i2c->regs + MXS_I2C_CTRL1_CLR);
|
|
|
|
|
2013-04-15 02:16:54 +02:00
|
|
|
/*
|
|
|
|
* When ending a transfer with a stop, we have to wait for the bus to
|
|
|
|
* go idle before we report the transfer as completed. Otherwise the
|
|
|
|
* start of the next transfer may race with the end of the current one.
|
|
|
|
*/
|
|
|
|
while (last && (readl(i2c->regs + MXS_I2C_STAT) &
|
|
|
|
(MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) {
|
|
|
|
if (time_after(jiffies, timeout))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
cond_resched();
|
|
|
|
}
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-15 02:16:55 +02:00
|
|
|
static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
|
|
|
|
{
|
|
|
|
u32 state;
|
|
|
|
|
|
|
|
state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
|
|
|
|
|
|
|
|
if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
|
|
|
|
i2c->cmd_err = -ENXIO;
|
|
|
|
else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
|
|
|
|
MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
|
|
|
|
MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
|
|
|
|
MXS_I2C_CTRL1_SLAVE_IRQ))
|
|
|
|
i2c->cmd_err = -EIO;
|
|
|
|
|
|
|
|
return i2c->cmd_err;
|
|
|
|
}
|
|
|
|
|
2013-04-15 02:16:54 +02:00
|
|
|
static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
writel(cmd, i2c->regs + MXS_I2C_CTRL0);
|
|
|
|
|
|
|
|
/* readback makes sure the write is latched into hardware */
|
|
|
|
reg = readl(i2c->regs + MXS_I2C_CTRL0);
|
|
|
|
reg |= MXS_I2C_CTRL0_RUN;
|
|
|
|
writel(reg, i2c->regs + MXS_I2C_CTRL0);
|
|
|
|
}
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
|
|
|
|
struct i2c_msg *msg, uint32_t flags)
|
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
|
|
|
|
uint32_t addr_data = msg->addr << 1;
|
|
|
|
uint32_t data = 0;
|
|
|
|
int i, shifts_left, ret;
|
|
|
|
|
|
|
|
/* Mute IRQs coming from this block. */
|
|
|
|
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
|
|
|
|
|
|
|
|
if (msg->flags & I2C_M_RD) {
|
|
|
|
addr_data |= I2C_SMBUS_READ;
|
|
|
|
|
|
|
|
/* SELECT command. */
|
2013-04-15 02:16:54 +02:00
|
|
|
mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT);
|
2013-01-24 13:56:21 +01:00
|
|
|
|
|
|
|
ret = mxs_i2c_pio_wait_dmareq(i2c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
writel(addr_data, i2c->regs + MXS_I2C_DATA);
|
2013-04-15 02:16:54 +02:00
|
|
|
writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
|
2013-01-24 13:56:21 +01:00
|
|
|
|
2013-04-15 02:16:54 +02:00
|
|
|
ret = mxs_i2c_pio_wait_cplt(i2c, 0);
|
2013-01-24 13:56:21 +01:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-04-15 02:16:55 +02:00
|
|
|
if (mxs_i2c_pio_check_error_state(i2c))
|
|
|
|
goto cleanup;
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
/* READ command. */
|
2013-04-15 02:16:54 +02:00
|
|
|
mxs_i2c_pio_trigger_cmd(i2c,
|
|
|
|
MXS_CMD_I2C_READ | flags |
|
|
|
|
MXS_I2C_CTRL0_XFER_COUNT(msg->len));
|
2013-01-24 13:56:21 +01:00
|
|
|
|
|
|
|
for (i = 0; i < msg->len; i++) {
|
|
|
|
if ((i & 3) == 0) {
|
|
|
|
ret = mxs_i2c_pio_wait_dmareq(i2c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
data = readl(i2c->regs + MXS_I2C_DATA);
|
2013-04-15 02:16:54 +02:00
|
|
|
writel(MXS_I2C_DEBUG0_DMAREQ,
|
|
|
|
i2c->regs + MXS_I2C_DEBUG0_CLR);
|
2013-01-24 13:56:21 +01:00
|
|
|
}
|
|
|
|
msg->buf[i] = data & 0xff;
|
|
|
|
data >>= 8;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
addr_data |= I2C_SMBUS_WRITE;
|
|
|
|
|
|
|
|
/* WRITE command. */
|
2013-04-15 02:16:54 +02:00
|
|
|
mxs_i2c_pio_trigger_cmd(i2c,
|
|
|
|
MXS_CMD_I2C_WRITE | flags |
|
|
|
|
MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1));
|
2013-01-24 13:56:21 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The LSB of data buffer is the first byte blasted across
|
|
|
|
* the bus. Higher order bytes follow. Thus the following
|
|
|
|
* filling schematic.
|
|
|
|
*/
|
|
|
|
data = addr_data << 24;
|
|
|
|
for (i = 0; i < msg->len; i++) {
|
|
|
|
data >>= 8;
|
|
|
|
data |= (msg->buf[i] << 24);
|
|
|
|
if ((i & 3) == 2) {
|
|
|
|
ret = mxs_i2c_pio_wait_dmareq(i2c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
writel(data, i2c->regs + MXS_I2C_DATA);
|
2013-04-15 02:16:54 +02:00
|
|
|
writel(MXS_I2C_DEBUG0_DMAREQ,
|
|
|
|
i2c->regs + MXS_I2C_DEBUG0_CLR);
|
2013-01-24 13:56:21 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
shifts_left = 24 - (i & 3) * 8;
|
|
|
|
if (shifts_left) {
|
|
|
|
data >>= shifts_left;
|
|
|
|
ret = mxs_i2c_pio_wait_dmareq(i2c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
writel(data, i2c->regs + MXS_I2C_DATA);
|
2013-04-15 02:16:54 +02:00
|
|
|
writel(MXS_I2C_DEBUG0_DMAREQ,
|
|
|
|
i2c->regs + MXS_I2C_DEBUG0_CLR);
|
2013-01-24 13:56:21 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-15 02:16:54 +02:00
|
|
|
ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP);
|
2013-01-24 13:56:21 +01:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-04-15 02:16:55 +02:00
|
|
|
/* make sure we capture any occurred error into cmd_err */
|
|
|
|
mxs_i2c_pio_check_error_state(i2c);
|
|
|
|
|
|
|
|
cleanup:
|
2013-01-24 13:56:21 +01:00
|
|
|
/* Clear any dangling IRQs and re-enable interrupts. */
|
|
|
|
writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
|
|
|
|
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
/*
|
|
|
|
* Low level master read/write transaction.
|
|
|
|
*/
|
|
|
|
static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
|
|
|
|
int stop)
|
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
|
2013-07-11 03:19:28 +02:00
|
|
|
int ret, err;
|
2011-02-16 13:39:16 +01:00
|
|
|
int flags;
|
|
|
|
|
2012-08-24 05:44:31 +02:00
|
|
|
flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
|
|
|
|
msg->addr, msg->len, msg->flags, stop);
|
|
|
|
|
|
|
|
if (msg->len == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
/*
|
|
|
|
* The current boundary to select between PIO/DMA transfer method
|
|
|
|
* is set to 8 bytes, transfers shorter than 8 bytes are transfered
|
|
|
|
* using PIO mode while longer transfers use DMA. The 8 byte border is
|
|
|
|
* based on this empirical measurement and a lot of previous frobbing.
|
2013-09-30 01:23:53 +02:00
|
|
|
* Note: this special feature only works on i.MX28 SoC
|
2013-01-24 13:56:21 +01:00
|
|
|
*/
|
2013-04-15 02:16:55 +02:00
|
|
|
i2c->cmd_err = 0;
|
2013-07-01 23:14:21 +02:00
|
|
|
if (0) { /* disable PIO mode until a proper fix is made */
|
2013-01-24 13:56:21 +01:00
|
|
|
ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
|
2013-07-11 03:19:28 +02:00
|
|
|
if (ret) {
|
|
|
|
err = mxs_i2c_reset(i2c);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2013-01-24 13:56:21 +01:00
|
|
|
} else {
|
|
|
|
INIT_COMPLETION(i2c->cmd_complete);
|
|
|
|
ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-02-16 13:39:16 +01:00
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
ret = wait_for_completion_timeout(&i2c->cmd_complete,
|
2011-02-16 13:39:16 +01:00
|
|
|
msecs_to_jiffies(1000));
|
2013-01-24 13:56:21 +01:00
|
|
|
if (ret == 0)
|
|
|
|
goto timeout;
|
2013-04-15 02:16:55 +02:00
|
|
|
}
|
2013-01-24 13:56:21 +01:00
|
|
|
|
2013-04-15 02:16:55 +02:00
|
|
|
if (i2c->cmd_err == -ENXIO) {
|
|
|
|
/*
|
|
|
|
* If the transfer fails with a NAK from the slave the
|
|
|
|
* controller halts until it gets told to return to idle state.
|
|
|
|
*/
|
|
|
|
writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
|
|
|
|
i2c->regs + MXS_I2C_CTRL1_SET);
|
2013-01-24 13:56:21 +01:00
|
|
|
}
|
2011-02-16 13:39:16 +01:00
|
|
|
|
2013-04-15 02:16:55 +02:00
|
|
|
ret = i2c->cmd_err;
|
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
dev_dbg(i2c->dev, "Done with err=%d\n", ret);
|
2011-02-16 13:39:16 +01:00
|
|
|
|
2013-01-24 13:56:21 +01:00
|
|
|
return ret;
|
2011-02-16 13:39:16 +01:00
|
|
|
|
|
|
|
timeout:
|
|
|
|
dev_dbg(i2c->dev, "Timeout!\n");
|
2012-10-12 12:55:16 +02:00
|
|
|
mxs_i2c_dma_finish(i2c);
|
2013-07-11 03:19:28 +02:00
|
|
|
ret = mxs_i2c_reset(i2c);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
|
|
|
|
int num)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 mxs_i2c_func(struct i2c_adapter *adap)
|
|
|
|
{
|
2012-11-18 06:25:08 +01:00
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
2011-02-16 13:39:16 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct mxs_i2c_dev *i2c = dev_id;
|
|
|
|
u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
|
|
|
|
|
|
|
|
if (!stat)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
|
|
|
|
i2c->cmd_err = -ENXIO;
|
|
|
|
else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
|
|
|
|
MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
|
|
|
|
MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
|
|
|
|
/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
|
|
|
|
i2c->cmd_err = -EIO;
|
|
|
|
|
|
|
|
writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
|
2012-01-13 12:14:26 +01:00
|
|
|
|
2011-02-16 13:39:16 +01:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm mxs_i2c_algo = {
|
|
|
|
.master_xfer = mxs_i2c_xfer,
|
|
|
|
.functionality = mxs_i2c_func,
|
|
|
|
};
|
|
|
|
|
2013-07-05 18:28:00 +02:00
|
|
|
static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
|
2012-11-30 18:48:35 +01:00
|
|
|
{
|
2013-07-05 18:28:00 +02:00
|
|
|
/* The I2C block clock runs at 24MHz */
|
2012-11-30 18:48:35 +01:00
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const uint32_t clk = 24000000;
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2013-07-05 18:28:00 +02:00
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uint32_t divider;
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2012-11-30 18:48:35 +01:00
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uint16_t high_count, low_count, rcv_count, xmit_count;
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2013-07-05 18:28:00 +02:00
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uint32_t bus_free, leadin;
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2012-11-30 18:48:35 +01:00
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struct device *dev = i2c->dev;
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2013-07-05 18:28:00 +02:00
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divider = DIV_ROUND_UP(clk, speed);
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if (divider < 25) {
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/*
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* limit the divider, so that min(low_count, high_count)
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* is >= 1
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*/
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divider = 25;
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dev_warn(dev,
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"Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
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speed / 1000, speed % 1000,
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clk / divider / 1000, clk / divider % 1000);
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} else if (divider > 1897) {
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/*
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* limit the divider, so that max(low_count, high_count)
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* cannot exceed 1023
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*/
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divider = 1897;
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dev_warn(dev,
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"Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
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speed / 1000, speed % 1000,
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clk / divider / 1000, clk / divider % 1000);
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2012-11-30 18:48:35 +01:00
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}
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/*
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2013-07-05 18:28:00 +02:00
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* The I2C spec specifies the following timing data:
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* standard mode fast mode Bitfield name
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* tLOW (SCL LOW period) 4700 ns 1300 ns
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* tHIGH (SCL HIGH period) 4000 ns 600 ns
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* tSU;DAT (data setup time) 250 ns 100 ns
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* tHD;STA (START hold time) 4000 ns 600 ns
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* tBUF (bus free time) 4700 ns 1300 ns
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2012-11-30 18:48:35 +01:00
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*
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2013-07-05 18:28:00 +02:00
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* The hardware (of the i.MX28 at least) seems to add 2 additional
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* clock cycles to the low_count and 7 cycles to the high_count.
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* This is compensated for by subtracting the respective constants
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* from the values written to the timing registers.
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2012-11-30 18:48:35 +01:00
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*/
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2013-07-05 18:28:00 +02:00
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if (speed > 100000) {
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/* fast mode */
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low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
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high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
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leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
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bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
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} else {
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/* normal mode */
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low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
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high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
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leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
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bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
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}
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rcv_count = high_count * 3 / 8;
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xmit_count = low_count * 3 / 8;
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dev_dbg(dev,
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"speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
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speed, clk / divider, divider, low_count, high_count,
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xmit_count, rcv_count, leadin, bus_free);
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2012-11-30 18:48:35 +01:00
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2013-07-05 18:28:00 +02:00
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low_count -= 2;
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high_count -= 7;
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2012-11-30 18:48:35 +01:00
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i2c->timing0 = (high_count << 16) | rcv_count;
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i2c->timing1 = (low_count << 16) | xmit_count;
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2013-07-05 18:28:00 +02:00
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i2c->timing2 = (bus_free << 16 | leadin);
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2012-11-30 18:48:35 +01:00
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}
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2012-07-09 18:22:53 +02:00
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static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
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{
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uint32_t speed;
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struct device *dev = i2c->dev;
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struct device_node *node = dev->of_node;
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int ret;
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ret = of_property_read_u32(node, "clock-frequency", &speed);
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2012-11-30 18:48:35 +01:00
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if (ret) {
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2012-07-09 18:22:53 +02:00
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dev_warn(dev, "No I2C speed selected, using 100kHz\n");
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2012-11-30 18:48:35 +01:00
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speed = 100000;
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}
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mxs_i2c_derive_timing(i2c, speed);
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2012-07-09 18:22:53 +02:00
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return 0;
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}
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2013-09-30 01:23:53 +02:00
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static struct platform_device_id mxs_i2c_devtype[] = {
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{
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.name = "imx23-i2c",
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.driver_data = MXS_I2C_V1,
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}, {
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.name = "imx28-i2c",
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.driver_data = MXS_I2C_V2,
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}, { /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
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static const struct of_device_id mxs_i2c_dt_ids[] = {
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{ .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
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{ .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
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2012-11-27 21:59:38 +01:00
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static int mxs_i2c_probe(struct platform_device *pdev)
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2011-02-16 13:39:16 +01:00
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{
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2013-09-30 01:23:53 +02:00
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const struct of_device_id *of_id =
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of_match_device(mxs_i2c_dt_ids, &pdev->dev);
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2011-02-16 13:39:16 +01:00
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struct device *dev = &pdev->dev;
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struct mxs_i2c_dev *i2c;
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struct i2c_adapter *adap;
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struct resource *res;
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resource_size_t res_size;
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2013-02-26 04:20:22 +01:00
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int err, irq;
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2011-02-16 13:39:16 +01:00
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i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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2013-09-30 01:23:53 +02:00
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if (of_id) {
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const struct platform_device_id *device_id = of_id->data;
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i2c->dev_type = device_id->driver_data;
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}
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2011-02-16 13:39:16 +01:00
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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2012-08-24 05:44:31 +02:00
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irq = platform_get_irq(pdev, 0);
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2013-02-26 04:20:22 +01:00
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if (!res || irq < 0)
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2011-02-16 13:39:16 +01:00
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return -ENOENT;
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res_size = resource_size(res);
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if (!devm_request_mem_region(dev, res->start, res_size, res->name))
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return -EBUSY;
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i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
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if (!i2c->regs)
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return -EBUSY;
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err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
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if (err)
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return err;
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i2c->dev = dev;
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2012-07-09 18:22:53 +02:00
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2012-11-21 06:19:06 +01:00
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init_completion(&i2c->cmd_complete);
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2012-09-08 17:28:06 +02:00
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if (dev->of_node) {
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err = mxs_i2c_get_ofdata(i2c);
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if (err)
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return err;
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}
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2012-07-09 18:22:53 +02:00
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2012-08-24 05:44:31 +02:00
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/* Setup the DMA */
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2013-02-26 04:20:22 +01:00
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i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
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2012-10-12 12:55:16 +02:00
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if (!i2c->dmach) {
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dev_err(dev, "Failed to request dma\n");
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return -ENODEV;
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2012-08-24 05:44:31 +02:00
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}
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2011-02-16 13:39:16 +01:00
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platform_set_drvdata(pdev, i2c);
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/* Do reset to enforce correct startup after pinmuxing */
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2013-07-11 03:19:28 +02:00
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err = mxs_i2c_reset(i2c);
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if (err)
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return err;
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2011-02-16 13:39:16 +01:00
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adap = &i2c->adapter;
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strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
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adap->owner = THIS_MODULE;
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adap->algo = &mxs_i2c_algo;
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adap->dev.parent = dev;
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adap->nr = pdev->id;
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2012-05-12 07:43:32 +02:00
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adap->dev.of_node = pdev->dev.of_node;
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2011-02-16 13:39:16 +01:00
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i2c_set_adapdata(adap, i2c);
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err = i2c_add_numbered_adapter(adap);
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if (err) {
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dev_err(dev, "Failed to add adapter (%d)\n", err);
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writel(MXS_I2C_CTRL0_SFTRST,
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i2c->regs + MXS_I2C_CTRL0_SET);
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return err;
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}
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return 0;
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}
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2012-11-27 21:59:38 +01:00
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static int mxs_i2c_remove(struct platform_device *pdev)
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2011-02-16 13:39:16 +01:00
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{
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struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
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2013-03-09 09:16:46 +01:00
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i2c_del_adapter(&i2c->adapter);
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2011-02-16 13:39:16 +01:00
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2012-08-24 05:44:31 +02:00
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if (i2c->dmach)
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dma_release_channel(i2c->dmach);
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2011-02-16 13:39:16 +01:00
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writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
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return 0;
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}
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static struct platform_driver mxs_i2c_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
|
2012-05-12 07:43:32 +02:00
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.of_match_table = mxs_i2c_dt_ids,
|
2011-02-16 13:39:16 +01:00
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},
|
2012-11-27 21:59:38 +01:00
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.remove = mxs_i2c_remove,
|
2011-02-16 13:39:16 +01:00
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};
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static int __init mxs_i2c_init(void)
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{
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return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
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}
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subsys_initcall(mxs_i2c_init);
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static void __exit mxs_i2c_exit(void)
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{
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platform_driver_unregister(&mxs_i2c_driver);
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}
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module_exit(mxs_i2c_exit);
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MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
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MODULE_DESCRIPTION("MXS I2C Bus Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRIVER_NAME);
|