2005-04-17 00:20:36 +02:00
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/*
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* sata_promise.c - Promise SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc.
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*
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*
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2005-08-29 02:18:39 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware information only available under NDA.
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2005-04-17 00:20:36 +02:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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2005-10-30 20:39:11 +01:00
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#include <linux/device.h>
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2005-04-17 00:20:36 +02:00
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#include <scsi/scsi_host.h>
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2005-11-07 06:59:37 +01:00
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#include <scsi/scsi_cmnd.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/libata.h>
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#include <asm/io.h>
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#include "sata_promise.h"
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#define DRV_NAME "sata_promise"
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2006-11-14 20:46:17 +01:00
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#define DRV_VERSION "1.05"
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2005-04-17 00:20:36 +02:00
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enum {
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PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_FLASH_CTL = 0x44, /* Flash control register */
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PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
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PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
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PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
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2006-01-28 18:39:29 +01:00
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PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
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[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
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PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
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PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
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2005-04-17 00:20:36 +02:00
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PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
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(1<<8) | (1<<9) | (1<<10),
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board_2037x = 0, /* FastTrak S150 TX2plus */
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board_20319 = 1, /* FastTrak S150 TX4 */
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2005-05-12 21:51:01 +02:00
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board_20619 = 2, /* FastTrak TX4000 */
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2006-01-17 14:06:21 +01:00
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board_20771 = 3, /* FastTrak TX2300 */
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2006-01-28 18:39:29 +01:00
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board_2057x = 4, /* SATAII150 Tx2plus */
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board_40518 = 5, /* SATAII150 Tx4 */
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2005-04-17 00:20:36 +02:00
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2006-01-28 18:39:29 +01:00
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PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
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2005-04-17 00:20:36 +02:00
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PDC_RESET = (1 << 11), /* HDMA reset */
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2005-12-13 08:29:45 +01:00
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PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
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2005-12-14 04:28:19 +01:00
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ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
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ATA_FLAG_PIO_POLLING,
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[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
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/* hp->flags bits */
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PDC_FLAG_GEN_II = (1 << 0),
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2005-04-17 00:20:36 +02:00
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};
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struct pdc_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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};
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2006-01-28 18:39:29 +01:00
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struct pdc_host_priv {
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[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
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unsigned long flags;
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2006-01-28 18:39:29 +01:00
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int hotplug_offset;
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};
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2005-04-17 00:20:36 +02:00
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
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static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
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2005-04-17 00:20:36 +02:00
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static void pdc_eng_timeout(struct ata_port *ap);
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static int pdc_port_start(struct ata_port *ap);
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static void pdc_port_stop(struct ata_port *ap);
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2005-08-29 11:12:30 +02:00
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static void pdc_pata_phy_reset(struct ata_port *ap);
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static void pdc_sata_phy_reset(struct ata_port *ap);
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2005-04-17 00:20:36 +02:00
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static void pdc_qc_prep(struct ata_queued_cmd *qc);
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2005-10-22 20:27:05 +02:00
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static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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2005-04-17 00:20:36 +02:00
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static void pdc_irq_clear(struct ata_port *ap);
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2006-01-23 05:09:36 +01:00
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static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
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2006-08-24 09:19:22 +02:00
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static void pdc_host_stop(struct ata_host *host);
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2005-04-17 00:20:36 +02:00
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2005-08-30 11:42:52 +02:00
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2005-11-07 06:59:37 +01:00
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static struct scsi_host_template pdc_ata_sht = {
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2005-04-17 00:20:36 +02:00
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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2006-05-31 11:28:09 +02:00
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.slave_destroy = ata_scsi_slave_destroy,
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2005-04-17 00:20:36 +02:00
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.bios_param = ata_std_bios_param,
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};
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2005-10-22 20:27:05 +02:00
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static const struct ata_port_operations pdc_sata_ops = {
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2005-04-17 00:20:36 +02:00
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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2005-08-29 11:12:30 +02:00
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.phy_reset = pdc_sata_phy_reset,
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2005-04-17 00:20:36 +02:00
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.eng_timeout = pdc_eng_timeout,
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2006-05-22 17:59:59 +02:00
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.data_xfer = ata_mmio_data_xfer,
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2005-04-17 00:20:36 +02:00
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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2005-08-29 11:12:30 +02:00
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2005-04-17 00:20:36 +02:00
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.scr_read = pdc_sata_scr_read,
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.scr_write = pdc_sata_scr_write,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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2006-01-28 18:39:29 +01:00
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.host_stop = pdc_host_stop,
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2005-04-17 00:20:36 +02:00
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};
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2005-10-22 20:27:05 +02:00
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static const struct ata_port_operations pdc_pata_ops = {
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2005-08-29 11:12:30 +02:00
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.phy_reset = pdc_pata_phy_reset,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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2006-05-22 17:59:59 +02:00
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.data_xfer = ata_mmio_data_xfer,
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2005-08-29 11:12:30 +02:00
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.eng_timeout = pdc_eng_timeout,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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2006-01-28 18:39:29 +01:00
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.host_stop = pdc_host_stop,
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2005-08-29 11:12:30 +02:00
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};
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2005-11-28 10:06:23 +01:00
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static const struct ata_port_info pdc_port_info[] = {
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2005-04-17 00:20:36 +02:00
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/* board_2037x */
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{
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.sht = &pdc_ata_sht,
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2006-08-24 09:19:22 +02:00
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.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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2005-04-17 00:20:36 +02:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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2005-08-29 11:12:30 +02:00
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.port_ops = &pdc_sata_ops,
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2005-04-17 00:20:36 +02:00
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},
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/* board_20319 */
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{
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.sht = &pdc_ata_sht,
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2006-08-24 09:19:22 +02:00
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.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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2005-04-17 00:20:36 +02:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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|
|
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
2005-08-29 11:12:30 +02:00
|
|
|
.port_ops = &pdc_sata_ops,
|
2005-04-17 00:20:36 +02:00
|
|
|
},
|
2005-05-12 21:51:01 +02:00
|
|
|
|
|
|
|
/* board_20619 */
|
|
|
|
{
|
|
|
|
.sht = &pdc_ata_sht,
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
|
2005-05-12 21:51:01 +02:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
2005-08-29 11:12:30 +02:00
|
|
|
.port_ops = &pdc_pata_ops,
|
2005-05-12 21:51:01 +02:00
|
|
|
},
|
2006-01-17 14:06:21 +01:00
|
|
|
|
|
|
|
/* board_20771 */
|
|
|
|
{
|
|
|
|
.sht = &pdc_ata_sht,
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
|
2006-01-17 14:06:21 +01:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
|
|
|
.port_ops = &pdc_sata_ops,
|
|
|
|
},
|
2006-01-28 18:39:29 +01:00
|
|
|
|
|
|
|
/* board_2057x */
|
|
|
|
{
|
|
|
|
.sht = &pdc_ata_sht,
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
|
2006-01-28 18:39:29 +01:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
|
|
|
.port_ops = &pdc_sata_ops,
|
|
|
|
},
|
|
|
|
|
|
|
|
/* board_40518 */
|
|
|
|
{
|
|
|
|
.sht = &pdc_ata_sht,
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
|
2006-01-28 18:39:29 +01:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
|
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
|
|
|
.port_ops = &pdc_sata_ops,
|
|
|
|
},
|
2005-04-17 00:20:36 +02:00
|
|
|
};
|
|
|
|
|
2005-11-10 17:04:11 +01:00
|
|
|
static const struct pci_device_id pdc_ata_pci_tbl[] = {
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
|
|
|
|
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
|
|
|
|
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
|
2005-05-12 21:51:01 +02:00
|
|
|
|
2006-07-24 09:37:52 +02:00
|
|
|
/* TODO: remove all associated board_20771 code, as it completely
|
|
|
|
* duplicates board_2037x code, unless reason for separation can be
|
|
|
|
* divined.
|
|
|
|
*/
|
|
|
|
#if 0
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3570), board_20771 },
|
2006-07-24 09:37:52 +02:00
|
|
|
#endif
|
2006-10-11 10:46:52 +02:00
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3577), board_20771 },
|
2006-07-24 09:37:52 +02:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
{ } /* terminate list */
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static struct pci_driver pdc_ata_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = pdc_ata_pci_tbl,
|
|
|
|
.probe = pdc_ata_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static int pdc_port_start(struct ata_port *ap)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct device *dev = ap->host->dev;
|
2006-12-01 10:55:58 +01:00
|
|
|
struct pdc_host_priv *hp = ap->host->private_data;
|
2005-04-17 00:20:36 +02:00
|
|
|
struct pdc_port_priv *pp;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = ata_port_start(ap);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
pp = kzalloc(sizeof(*pp), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (!pp) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
|
|
|
|
if (!pp->pkt) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_kfree;
|
|
|
|
}
|
|
|
|
|
|
|
|
ap->private_data = pp;
|
|
|
|
|
2006-12-01 10:55:58 +01:00
|
|
|
/* fix up PHYMODE4 align timing */
|
|
|
|
if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
|
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
|
|
|
|
unsigned int tmp;
|
|
|
|
|
|
|
|
tmp = readl(mmio + 0x014);
|
|
|
|
tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
|
|
|
|
writel(tmp, mmio + 0x014);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_kfree:
|
|
|
|
kfree(pp);
|
|
|
|
err_out:
|
|
|
|
ata_port_stop(ap);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_port_stop(struct ata_port *ap)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct device *dev = ap->host->dev;
|
2005-04-17 00:20:36 +02:00
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
|
|
|
|
|
|
ap->private_data = NULL;
|
|
|
|
dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
|
|
|
|
kfree(pp);
|
|
|
|
ata_port_stop(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
static void pdc_host_stop(struct ata_host *host)
|
2006-01-28 18:39:29 +01:00
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct pdc_host_priv *hp = host->private_data;
|
2006-01-28 18:39:29 +01:00
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
ata_pci_host_stop(host);
|
2006-01-28 18:39:29 +01:00
|
|
|
|
|
|
|
kfree(hp);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static void pdc_reset_port(struct ata_port *ap)
|
|
|
|
{
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned int i;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
for (i = 11; i > 0; i--) {
|
|
|
|
tmp = readl(mmio);
|
|
|
|
if (tmp & PDC_RESET)
|
|
|
|
break;
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
tmp |= PDC_RESET;
|
|
|
|
writel(tmp, mmio);
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp &= ~PDC_RESET;
|
|
|
|
writel(tmp, mmio);
|
|
|
|
readl(mmio); /* flush */
|
|
|
|
}
|
|
|
|
|
2005-08-29 11:12:30 +02:00
|
|
|
static void pdc_sata_phy_reset(struct ata_port *ap)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
pdc_reset_port(ap);
|
|
|
|
sata_phy_reset(ap);
|
|
|
|
}
|
|
|
|
|
2006-05-24 07:43:25 +02:00
|
|
|
static void pdc_pata_cbl_detect(struct ata_port *ap)
|
2005-08-29 11:12:30 +02:00
|
|
|
{
|
2006-05-24 07:43:25 +02:00
|
|
|
u8 tmp;
|
2006-10-10 23:48:07 +02:00
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
|
2006-05-24 07:43:25 +02:00
|
|
|
|
|
|
|
tmp = readb(mmio);
|
|
|
|
|
|
|
|
if (tmp & 0x01) {
|
|
|
|
ap->cbl = ATA_CBL_PATA40;
|
|
|
|
ap->udma_mask &= ATA_UDMA_MASK_40C;
|
|
|
|
} else
|
|
|
|
ap->cbl = ATA_CBL_PATA80;
|
|
|
|
}
|
2005-08-29 11:12:30 +02:00
|
|
|
|
2006-05-24 07:43:25 +02:00
|
|
|
static void pdc_pata_phy_reset(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
pdc_pata_cbl_detect(ap);
|
2005-08-29 11:12:30 +02:00
|
|
|
pdc_reset_port(ap);
|
|
|
|
ata_port_probe(ap);
|
|
|
|
ata_bus_reset(ap);
|
|
|
|
}
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
|
|
|
|
{
|
|
|
|
if (sc_reg > SCR_CONTROL)
|
|
|
|
return 0xffffffffU;
|
2005-10-21 07:46:02 +02:00
|
|
|
return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
|
|
|
|
u32 val)
|
|
|
|
{
|
|
|
|
if (sc_reg > SCR_CONTROL)
|
|
|
|
return;
|
2005-10-21 07:46:02 +02:00
|
|
|
writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_qc_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct pdc_port_priv *pp = qc->ap->private_data;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
ata_qc_prep(qc);
|
|
|
|
/* fall through */
|
|
|
|
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
|
|
|
|
qc->dev->devno, pp->pkt);
|
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48)
|
|
|
|
i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
|
|
|
|
else
|
|
|
|
i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
|
|
|
|
|
|
|
|
pdc_pkt_footer(&qc->tf, pp->pkt, i);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_eng_timeout(struct ata_port *ap)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_host *host = ap->host;
|
2005-04-17 00:20:36 +02:00
|
|
|
u8 drv_stat;
|
|
|
|
struct ata_queued_cmd *qc;
|
2005-08-26 04:01:20 +02:00
|
|
|
unsigned long flags;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2005-08-26 04:01:20 +02:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
2006-05-15 13:57:56 +02:00
|
|
|
ata_port_printk(ap, KERN_ERR, "command timeout\n");
|
2005-10-30 10:44:42 +01:00
|
|
|
drv_stat = ata_wait_idle(ap);
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= __ac_err_mask(drv_stat);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
|
|
|
|
|
2006-05-15 13:57:56 +02:00
|
|
|
ata_port_printk(ap, KERN_ERR,
|
|
|
|
"unknown timeout, cmd 0x%x stat 0x%x\n",
|
|
|
|
qc->tf.command, drv_stat);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= ac_err_mask(drv_stat);
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2006-02-10 07:10:48 +01:00
|
|
|
ata_eh_qc_complete(qc);
|
2005-04-17 00:20:36 +02:00
|
|
|
DPRINTK("EXIT\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int pdc_host_intr( struct ata_port *ap,
|
|
|
|
struct ata_queued_cmd *qc)
|
|
|
|
{
|
2005-12-05 08:38:02 +01:00
|
|
|
unsigned int handled = 0;
|
2005-04-17 00:20:36 +02:00
|
|
|
u32 tmp;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
tmp = readl(mmio);
|
|
|
|
if (tmp & PDC_ERR_MASK) {
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= AC_ERR_DEV;
|
2005-04-17 00:20:36 +02:00
|
|
|
pdc_reset_port(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
2005-12-05 08:38:02 +01:00
|
|
|
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
|
|
|
|
ata_qc_complete(qc);
|
2005-04-17 00:20:36 +02:00
|
|
|
handled = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2005-09-27 11:34:38 +02:00
|
|
|
ap->stats.idle_irq++;
|
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2005-09-27 11:34:38 +02:00
|
|
|
return handled;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_irq_clear(struct ata_port *ap)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_host *host = ap->host;
|
|
|
|
void __iomem *mmio = host->mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
readl(mmio + PDC_INT_SEQMASK);
|
|
|
|
}
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
|
|
|
static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_host *host = dev_instance;
|
2005-04-17 00:20:36 +02:00
|
|
|
struct ata_port *ap;
|
|
|
|
u32 mask = 0;
|
|
|
|
unsigned int i, tmp;
|
|
|
|
unsigned int handled = 0;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
if (!host || !host->mmio_base) {
|
2005-04-17 00:20:36 +02:00
|
|
|
VPRINTK("QUICK EXIT\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
mmio_base = host->mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* reading should also clear interrupts */
|
|
|
|
mask = readl(mmio_base + PDC_INT_SEQMASK);
|
|
|
|
|
|
|
|
if (mask == 0xffffffff) {
|
|
|
|
VPRINTK("QUICK EXIT 2\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
2006-01-28 18:39:29 +01:00
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_lock(&host->lock);
|
2006-01-28 18:39:29 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
mask &= 0xffff; /* only 16 tags possible */
|
|
|
|
if (!mask) {
|
|
|
|
VPRINTK("QUICK EXIT 3\n");
|
2006-01-28 18:39:29 +01:00
|
|
|
goto done_irq;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
writel(mask, mmio_base + PDC_INT_SEQMASK);
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
2005-04-17 00:20:36 +02:00
|
|
|
VPRINTK("port %u\n", i);
|
2006-08-24 09:19:22 +02:00
|
|
|
ap = host->ports[i];
|
2005-04-17 00:20:36 +02:00
|
|
|
tmp = mask & (1 << (i + 1));
|
2005-08-22 07:59:24 +02:00
|
|
|
if (tmp && ap &&
|
2006-04-02 16:30:40 +02:00
|
|
|
!(ap->flags & ATA_FLAG_DISABLED)) {
|
2005-04-17 00:20:36 +02:00
|
|
|
struct ata_queued_cmd *qc;
|
|
|
|
|
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
2005-09-27 11:39:50 +02:00
|
|
|
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
|
2005-04-17 00:20:36 +02:00
|
|
|
handled += pdc_host_intr(ap, qc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VPRINTK("EXIT\n");
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
done_irq:
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_unlock(&host->lock);
|
2005-04-17 00:20:36 +02:00
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pdc_packet_start(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
|
|
unsigned int port_no = ap->port_no;
|
|
|
|
u8 seq = (u8) (port_no + 1);
|
|
|
|
|
|
|
|
VPRINTK("ENTER, ap %p\n", ap);
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
writel(0x00000001, ap->host->mmio_base + (seq * 4));
|
|
|
|
readl(ap->host->mmio_base + (seq * 4)); /* flush */
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
pp->pkt[2] = seq;
|
|
|
|
wmb(); /* flush PRD, pkt writes */
|
2005-10-21 07:46:02 +02:00
|
|
|
writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
|
|
|
readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
2006-01-23 05:09:36 +01:00
|
|
|
static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
pdc_packet_start(qc);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case ATA_PROT_ATAPI_DMA:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ata_qc_issue_prot(qc);
|
|
|
|
}
|
|
|
|
|
2005-10-22 20:27:05 +02:00
|
|
|
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_tf_load(ap, tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-10-22 20:27:05 +02:00
|
|
|
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_exec_command(ap, tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
|
|
|
|
{
|
|
|
|
port->cmd_addr = base;
|
|
|
|
port->data_addr = base;
|
|
|
|
port->feature_addr =
|
|
|
|
port->error_addr = base + 0x4;
|
|
|
|
port->nsect_addr = base + 0x8;
|
|
|
|
port->lbal_addr = base + 0xc;
|
|
|
|
port->lbam_addr = base + 0x10;
|
|
|
|
port->lbah_addr = base + 0x14;
|
|
|
|
port->device_addr = base + 0x18;
|
|
|
|
port->command_addr =
|
|
|
|
port->status_addr = base + 0x1c;
|
|
|
|
port->altstatus_addr =
|
|
|
|
port->ctl_addr = base + 0x38;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
|
|
|
|
{
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2006-01-28 18:39:29 +01:00
|
|
|
struct pdc_host_priv *hp = pe->private_data;
|
|
|
|
int hotplug_offset = hp->hotplug_offset;
|
2005-04-17 00:20:36 +02:00
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Except for the hotplug stuff, this is voodoo from the
|
|
|
|
* Promise driver. Label this entire section
|
|
|
|
* "TODO: figure out why we do this"
|
|
|
|
*/
|
|
|
|
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
/* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
|
2005-04-17 00:20:36 +02:00
|
|
|
tmp = readl(mmio + PDC_FLASH_CTL);
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
tmp |= 0x02000; /* bit 13 (enable bmr burst) */
|
|
|
|
if (!(hp->flags & PDC_FLAG_GEN_II))
|
|
|
|
tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
|
2005-04-17 00:20:36 +02:00
|
|
|
writel(tmp, mmio + PDC_FLASH_CTL);
|
|
|
|
|
|
|
|
/* clear plug/unplug flags for all ports */
|
2006-01-28 18:39:29 +01:00
|
|
|
tmp = readl(mmio + hotplug_offset);
|
|
|
|
writel(tmp | 0xff, mmio + hotplug_offset);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* mask plug/unplug ints */
|
2006-01-28 18:39:29 +01:00
|
|
|
tmp = readl(mmio + hotplug_offset);
|
|
|
|
writel(tmp | 0xff0000, mmio + hotplug_offset);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
/* don't initialise TBG or SLEW on 2nd generation chips */
|
|
|
|
if (hp->flags & PDC_FLAG_GEN_II)
|
|
|
|
return;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* reduce TBG clock to 133 Mhz. */
|
|
|
|
tmp = readl(mmio + PDC_TBG_MODE);
|
|
|
|
tmp &= ~0x30000; /* clear bit 17, 16*/
|
|
|
|
tmp |= 0x10000; /* set bit 17:16 = 0:1 */
|
|
|
|
writel(tmp, mmio + PDC_TBG_MODE);
|
|
|
|
|
|
|
|
readl(mmio + PDC_TBG_MODE); /* flush */
|
|
|
|
msleep(10);
|
|
|
|
|
|
|
|
/* adjust slew rate control register. */
|
|
|
|
tmp = readl(mmio + PDC_SLEW_CTL);
|
|
|
|
tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
|
|
|
|
tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
|
|
|
|
writel(tmp, mmio + PDC_SLEW_CTL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
|
static int printed_version;
|
|
|
|
struct ata_probe_ent *probe_ent = NULL;
|
2006-01-28 18:39:29 +01:00
|
|
|
struct pdc_host_priv *hp;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned long base;
|
2005-08-30 11:18:18 +02:00
|
|
|
void __iomem *mmio_base;
|
2005-04-17 00:20:36 +02:00
|
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
|
|
int pci_dev_busy = 0;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (!printed_version++)
|
2005-10-30 20:39:11 +01:00
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
|
|
if (rc) {
|
|
|
|
pci_dev_busy = 1;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (probe_ent == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_regions;
|
|
|
|
}
|
|
|
|
|
|
|
|
probe_ent->dev = pci_dev_to_dev(pdev);
|
|
|
|
INIT_LIST_HEAD(&probe_ent->node);
|
|
|
|
|
2005-08-30 11:42:52 +02:00
|
|
|
mmio_base = pci_iomap(pdev, 3, 0);
|
2005-04-17 00:20:36 +02:00
|
|
|
if (mmio_base == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_free_ent;
|
|
|
|
}
|
|
|
|
base = (unsigned long) mmio_base;
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
hp = kzalloc(sizeof(*hp), GFP_KERNEL);
|
|
|
|
if (hp == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_free_ent;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set default hotplug offset */
|
|
|
|
hp->hotplug_offset = PDC_SATA_PLUG_CSR;
|
|
|
|
probe_ent->private_data = hp;
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
probe_ent->sht = pdc_port_info[board_idx].sht;
|
2006-08-24 09:19:22 +02:00
|
|
|
probe_ent->port_flags = pdc_port_info[board_idx].flags;
|
2005-04-17 00:20:36 +02:00
|
|
|
probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
|
|
|
|
probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
|
|
|
|
probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
|
|
|
|
probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
|
|
|
|
|
|
|
|
probe_ent->irq = pdev->irq;
|
2006-07-02 04:29:42 +02:00
|
|
|
probe_ent->irq_flags = IRQF_SHARED;
|
2005-04-17 00:20:36 +02:00
|
|
|
probe_ent->mmio_base = mmio_base;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
|
|
|
|
|
|
|
|
probe_ent->port[0].scr_addr = base + 0x400;
|
|
|
|
probe_ent->port[1].scr_addr = base + 0x500;
|
|
|
|
|
|
|
|
/* notice 4-port boards */
|
|
|
|
switch (board_idx) {
|
2006-01-28 18:39:29 +01:00
|
|
|
case board_40518:
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
hp->flags |= PDC_FLAG_GEN_II;
|
2006-01-28 18:39:29 +01:00
|
|
|
/* Override hotplug offset for SATAII150 */
|
|
|
|
hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
|
|
|
|
/* Fall through */
|
2005-04-17 00:20:36 +02:00
|
|
|
case board_20319:
|
|
|
|
probe_ent->n_ports = 4;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
|
|
|
|
probe_ent->port[2].scr_addr = base + 0x600;
|
|
|
|
probe_ent->port[3].scr_addr = base + 0x700;
|
|
|
|
break;
|
2006-01-28 18:39:29 +01:00
|
|
|
case board_2057x:
|
[PATCH] sata_promise fixes and updates
This patch updates the sata_promise driver as follows:
- Correct typo in definition of PDC_TBG_MODE: it's at 0x41C not 0x41
in first-generation chips. This error caused PCI access alignment
exceptions on SPARC64, and on all platforms it disabled the expected
initialisation of TBG mode.
- Add flags field to struct pdc_host_priv. Define PDC_FLAG_GEN_II
and use it to distinguish first- and second-generation chips.
- Prevent the FLASH_CTL FIFO_SHD bit from being set to 1 on second-
generation chips. This matches Promises' ulsata2 driver.
- Prevent TBG mode and SLEW rate initialisation in second-generation chips.
These two registers have moved, TBG mode has been redefined, and
Promise's ulsata2 driver no longer attempts to initialise them.
- Correct PCI device table so devices 0x3570, 0x3571, and 0x3d73 are
marked as 2057x (2nd gen) not 2037x (1st gen).
- Correct PCI device table so device 0x3d17 is marked as 40518
(2nd gen 4 ports) not 20319 (1st gen 4 ports).
- Correct pdc_ata_init_one() to treat 20771 as a second-generation chip.
Tested on 0x3d75 (2nd gen), 0x3d73 (2nd gen), and 0x3373 (1st gen) chips.
The information comes from the newly uploaded Promise SATA HW specs,
Promise's ultra and ulsata2 drivers, and debugging on 3d75/3d73/3373 chips.
hp->hotplug_offset could now be removed and its value recomputed
in pdc_host_init() using hp->flags, but that would be a cleanup
not a functional change, so I'm ignoring it for now.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-22 22:00:15 +01:00
|
|
|
case board_20771:
|
|
|
|
hp->flags |= PDC_FLAG_GEN_II;
|
2006-01-28 18:39:29 +01:00
|
|
|
/* Override hotplug offset for SATAII150 */
|
|
|
|
hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
|
|
|
|
/* Fall through */
|
2005-04-17 00:20:36 +02:00
|
|
|
case board_2037x:
|
2005-11-30 22:42:55 +01:00
|
|
|
probe_ent->n_ports = 2;
|
2005-04-17 00:20:36 +02:00
|
|
|
break;
|
2005-05-12 21:51:01 +02:00
|
|
|
case board_20619:
|
|
|
|
probe_ent->n_ports = 4;
|
|
|
|
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
|
|
|
|
probe_ent->port[2].scr_addr = base + 0x600;
|
|
|
|
probe_ent->port[3].scr_addr = base + 0x700;
|
2005-11-30 22:42:55 +01:00
|
|
|
break;
|
2005-04-17 00:20:36 +02:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
|
|
/* initialize adapter */
|
|
|
|
pdc_host_init(board_idx, probe_ent);
|
|
|
|
|
2006-01-28 18:39:29 +01:00
|
|
|
/* FIXME: Need any other frees than hp? */
|
|
|
|
if (!ata_device_add(probe_ent))
|
|
|
|
kfree(hp);
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
kfree(probe_ent);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_free_ent:
|
|
|
|
kfree(probe_ent);
|
|
|
|
err_out_regions:
|
|
|
|
pci_release_regions(pdev);
|
|
|
|
err_out:
|
|
|
|
if (!pci_dev_busy)
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int __init pdc_ata_init(void)
|
|
|
|
{
|
2006-08-10 11:13:18 +02:00
|
|
|
return pci_register_driver(&pdc_ata_pci_driver);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void __exit pdc_ata_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&pdc_ata_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
2005-05-12 21:51:01 +02:00
|
|
|
MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
|
2005-04-17 00:20:36 +02:00
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(pdc_ata_init);
|
|
|
|
module_exit(pdc_ata_exit);
|