2005-07-10 20:58:15 +02:00
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/*
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* linux/arch/arm/plat-omap/gpio.c
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*
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* Support functions for OMAP GPIO
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*
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2005-09-07 18:20:26 +02:00
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* Copyright (C) 2003-2005 Nokia Corporation
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2007-10-19 23:21:04 +02:00
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* Written by Juha Yrjölä <juha.yrjola@nokia.com>
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2005-07-10 20:58:15 +02:00
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*
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2009-05-28 23:16:04 +02:00
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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2005-07-10 20:58:15 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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2005-09-07 18:20:26 +02:00
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#include <linux/sysdev.h>
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#include <linux/err.h>
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2006-01-07 17:15:52 +01:00
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#include <linux/clk.h>
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2008-09-06 13:10:45 +02:00
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#include <linux/io.h>
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2005-07-10 20:58:15 +02:00
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2008-08-05 17:14:15 +02:00
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#include <mach/hardware.h>
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2005-07-10 20:58:15 +02:00
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#include <asm/irq.h>
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2008-08-05 17:14:15 +02:00
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#include <mach/irqs.h>
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#include <mach/gpio.h>
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2005-07-10 20:58:15 +02:00
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#include <asm/mach/irq.h>
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/*
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* OMAP1510 GPIO registers
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP1510_GPIO_BASE 0xfffce000
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2005-07-10 20:58:15 +02:00
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#define OMAP1510_GPIO_DATA_INPUT 0x00
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#define OMAP1510_GPIO_DATA_OUTPUT 0x04
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#define OMAP1510_GPIO_DIR_CONTROL 0x08
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#define OMAP1510_GPIO_INT_CONTROL 0x0c
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#define OMAP1510_GPIO_INT_MASK 0x10
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#define OMAP1510_GPIO_INT_STATUS 0x14
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#define OMAP1510_GPIO_PIN_CONTROL 0x18
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#define OMAP1510_IH_GPIO_BASE 64
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/*
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* OMAP1610 specific GPIO registers
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP1610_GPIO1_BASE 0xfffbe400
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#define OMAP1610_GPIO2_BASE 0xfffbec00
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#define OMAP1610_GPIO3_BASE 0xfffbb400
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#define OMAP1610_GPIO4_BASE 0xfffbbc00
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2005-07-10 20:58:15 +02:00
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#define OMAP1610_GPIO_REVISION 0x0000
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#define OMAP1610_GPIO_SYSCONFIG 0x0010
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#define OMAP1610_GPIO_SYSSTATUS 0x0014
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#define OMAP1610_GPIO_IRQSTATUS1 0x0018
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#define OMAP1610_GPIO_IRQENABLE1 0x001c
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2005-09-07 18:20:26 +02:00
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#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
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2005-07-10 20:58:15 +02:00
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#define OMAP1610_GPIO_DATAIN 0x002c
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#define OMAP1610_GPIO_DATAOUT 0x0030
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#define OMAP1610_GPIO_DIRECTION 0x0034
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#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
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#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
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#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
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2005-09-07 18:20:26 +02:00
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#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
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2005-07-10 20:58:15 +02:00
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#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
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#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
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2005-09-07 18:20:26 +02:00
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#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
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2005-07-10 20:58:15 +02:00
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#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
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/*
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2009-09-22 11:02:58 +02:00
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* OMAP7XX specific GPIO registers
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2005-07-10 20:58:15 +02:00
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP7XX_GPIO1_BASE 0xfffbc000
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#define OMAP7XX_GPIO2_BASE 0xfffbc800
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#define OMAP7XX_GPIO3_BASE 0xfffbd000
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#define OMAP7XX_GPIO4_BASE 0xfffbd800
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#define OMAP7XX_GPIO5_BASE 0xfffbe000
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#define OMAP7XX_GPIO6_BASE 0xfffbe800
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2009-09-22 11:02:58 +02:00
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#define OMAP7XX_GPIO_DATA_INPUT 0x00
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#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
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#define OMAP7XX_GPIO_DIR_CONTROL 0x08
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#define OMAP7XX_GPIO_INT_CONTROL 0x0c
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#define OMAP7XX_GPIO_INT_MASK 0x10
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#define OMAP7XX_GPIO_INT_STATUS 0x14
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2005-07-10 20:58:15 +02:00
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2009-10-20 00:25:20 +02:00
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#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
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2009-08-28 19:50:33 +02:00
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2005-09-07 18:20:26 +02:00
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/*
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* omap24xx specific GPIO registers
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP242X_GPIO1_BASE 0x48018000
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#define OMAP242X_GPIO2_BASE 0x4801a000
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#define OMAP242X_GPIO3_BASE 0x4801c000
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#define OMAP242X_GPIO4_BASE 0x4801e000
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2006-12-07 02:14:08 +01:00
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2009-10-20 00:25:20 +02:00
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#define OMAP243X_GPIO1_BASE 0x4900C000
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#define OMAP243X_GPIO2_BASE 0x4900E000
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#define OMAP243X_GPIO3_BASE 0x49010000
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#define OMAP243X_GPIO4_BASE 0x49012000
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#define OMAP243X_GPIO5_BASE 0x480B6000
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2006-12-07 02:14:08 +01:00
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2005-09-07 18:20:26 +02:00
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#define OMAP24XX_GPIO_REVISION 0x0000
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#define OMAP24XX_GPIO_SYSCONFIG 0x0010
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#define OMAP24XX_GPIO_SYSSTATUS 0x0014
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#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
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2006-09-25 11:41:46 +02:00
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#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
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#define OMAP24XX_GPIO_IRQENABLE2 0x002c
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2005-09-07 18:20:26 +02:00
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#define OMAP24XX_GPIO_IRQENABLE1 0x001c
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2008-11-26 23:35:16 +01:00
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#define OMAP24XX_GPIO_WAKE_EN 0x0020
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2005-09-07 18:20:26 +02:00
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#define OMAP24XX_GPIO_CTRL 0x0030
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#define OMAP24XX_GPIO_OE 0x0034
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#define OMAP24XX_GPIO_DATAIN 0x0038
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#define OMAP24XX_GPIO_DATAOUT 0x003c
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#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
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#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
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#define OMAP24XX_GPIO_RISINGDETECT 0x0048
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#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
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2007-05-05 20:40:29 +02:00
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#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
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#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
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2005-09-07 18:20:26 +02:00
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#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
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#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
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#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
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#define OMAP24XX_GPIO_SETWKUENA 0x0084
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#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
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#define OMAP24XX_GPIO_SETDATAOUT 0x0094
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2009-07-28 15:27:30 +02:00
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#define OMAP4_GPIO_REVISION 0x0000
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#define OMAP4_GPIO_SYSCONFIG 0x0010
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#define OMAP4_GPIO_EOI 0x0020
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#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
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#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
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#define OMAP4_GPIO_IRQSTATUS0 0x002c
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#define OMAP4_GPIO_IRQSTATUS1 0x0030
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#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
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#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
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#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
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#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
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#define OMAP4_GPIO_IRQWAKEN0 0x0044
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#define OMAP4_GPIO_IRQWAKEN1 0x0048
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#define OMAP4_GPIO_SYSSTATUS 0x0104
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#define OMAP4_GPIO_CTRL 0x0130
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#define OMAP4_GPIO_OE 0x0134
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#define OMAP4_GPIO_DATAIN 0x0138
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#define OMAP4_GPIO_DATAOUT 0x013c
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#define OMAP4_GPIO_LEVELDETECT0 0x0140
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#define OMAP4_GPIO_LEVELDETECT1 0x0144
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#define OMAP4_GPIO_RISINGDETECT 0x0148
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#define OMAP4_GPIO_FALLINGDETECT 0x014c
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#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
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#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
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#define OMAP4_GPIO_CLEARDATAOUT 0x0190
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#define OMAP4_GPIO_SETDATAOUT 0x0194
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2007-11-30 01:15:11 +01:00
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/*
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* omap34xx specific GPIO registers
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP34XX_GPIO1_BASE 0x48310000
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#define OMAP34XX_GPIO2_BASE 0x49050000
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#define OMAP34XX_GPIO3_BASE 0x49052000
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#define OMAP34XX_GPIO4_BASE 0x49054000
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#define OMAP34XX_GPIO5_BASE 0x49056000
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#define OMAP34XX_GPIO6_BASE 0x49058000
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2007-11-30 01:15:11 +01:00
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2009-05-28 23:16:04 +02:00
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/*
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* OMAP44XX specific GPIO registers
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*/
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2009-10-20 00:25:20 +02:00
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#define OMAP44XX_GPIO1_BASE 0x4a310000
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#define OMAP44XX_GPIO2_BASE 0x48055000
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#define OMAP44XX_GPIO3_BASE 0x48057000
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#define OMAP44XX_GPIO4_BASE 0x48059000
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#define OMAP44XX_GPIO5_BASE 0x4805B000
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#define OMAP44XX_GPIO6_BASE 0x4805D000
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2007-11-30 01:15:11 +01:00
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2005-07-10 20:58:15 +02:00
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struct gpio_bank {
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2009-10-20 00:25:20 +02:00
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unsigned long pbase;
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2005-09-07 18:20:26 +02:00
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void __iomem *base;
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2005-07-10 20:58:15 +02:00
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u16 irq;
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u16 virtual_irq_start;
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2005-09-07 18:20:26 +02:00
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int method;
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2010-02-12 21:26:48 +01:00
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#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
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2005-09-07 18:20:26 +02:00
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u32 suspend_wakeup;
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u32 saved_wakeup;
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2006-12-07 02:13:52 +01:00
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#endif
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2010-02-12 21:26:48 +01:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
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2006-12-07 02:13:52 +01:00
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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u32 saved_datain;
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u32 saved_fallingdetect;
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u32 saved_risingdetect;
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#endif
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2008-01-17 06:56:15 +01:00
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u32 level_mask;
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omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
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u32 toggle_mask;
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2005-07-10 20:58:15 +02:00
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spinlock_t lock;
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2008-03-03 21:43:23 +01:00
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struct gpio_chip chip;
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2008-12-11 02:35:24 +01:00
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struct clk *dbck;
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2009-11-22 19:11:25 +01:00
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u32 mod_usage;
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2005-07-10 20:58:15 +02:00
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};
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#define METHOD_MPUIO 0
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#define METHOD_GPIO_1510 1
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#define METHOD_GPIO_1610 2
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2009-09-22 11:02:58 +02:00
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#define METHOD_GPIO_7XX 3
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2009-03-24 02:07:40 +01:00
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#define METHOD_GPIO_24XX 5
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2010-02-15 18:27:25 +01:00
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#define METHOD_GPIO_44XX 6
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2005-07-10 20:58:15 +02:00
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2005-09-07 18:20:26 +02:00
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#ifdef CONFIG_ARCH_OMAP16XX
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2005-07-10 20:58:15 +02:00
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static struct gpio_bank gpio_bank_1610[5] = {
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2009-10-20 00:25:20 +02:00
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{ OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
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METHOD_MPUIO },
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{ OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
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METHOD_GPIO_1610 },
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{ OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
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METHOD_GPIO_1610 },
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{ OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
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METHOD_GPIO_1610 },
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{ OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
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METHOD_GPIO_1610 },
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2005-07-10 20:58:15 +02:00
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};
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#endif
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2005-11-10 15:26:50 +01:00
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#ifdef CONFIG_ARCH_OMAP15XX
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2005-07-10 20:58:15 +02:00
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static struct gpio_bank gpio_bank_1510[2] = {
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2009-10-20 00:25:20 +02:00
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{ OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
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METHOD_MPUIO },
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{ OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
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METHOD_GPIO_1510 }
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2005-07-10 20:58:15 +02:00
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};
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#endif
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2009-09-23 19:56:19 +02:00
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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2009-09-22 11:02:58 +02:00
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static struct gpio_bank gpio_bank_7xx[7] = {
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2009-10-20 00:25:20 +02:00
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{ OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
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METHOD_MPUIO },
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{ OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
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METHOD_GPIO_7XX },
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{ OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
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METHOD_GPIO_7XX },
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{ OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
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METHOD_GPIO_7XX },
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{ OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
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METHOD_GPIO_7XX },
|
|
|
|
{ OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
|
|
|
|
METHOD_GPIO_7XX },
|
|
|
|
{ OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
|
|
|
|
METHOD_GPIO_7XX },
|
2005-07-10 20:58:15 +02:00
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:47 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
2006-12-07 02:14:08 +01:00
|
|
|
|
|
|
|
static struct gpio_bank gpio_bank_242x[4] = {
|
2009-10-20 00:25:20 +02:00
|
|
|
{ OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
|
|
|
|
METHOD_GPIO_24XX },
|
2005-09-07 18:20:26 +02:00
|
|
|
};
|
2006-12-07 02:14:08 +01:00
|
|
|
|
|
|
|
static struct gpio_bank gpio_bank_243x[5] = {
|
2009-10-20 00:25:20 +02:00
|
|
|
{ OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
|
|
|
|
METHOD_GPIO_24XX },
|
2006-12-07 02:14:08 +01:00
|
|
|
};
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2007-11-30 01:15:11 +01:00
|
|
|
static struct gpio_bank gpio_bank_34xx[6] = {
|
2009-10-20 00:25:20 +02:00
|
|
|
{ OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
|
|
|
|
METHOD_GPIO_24XX },
|
|
|
|
{ OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
|
|
|
|
METHOD_GPIO_24XX },
|
2007-11-30 01:15:11 +01:00
|
|
|
};
|
|
|
|
|
2008-09-26 14:17:48 +02:00
|
|
|
struct omap3_gpio_regs {
|
|
|
|
u32 sysconfig;
|
|
|
|
u32 irqenable1;
|
|
|
|
u32 irqenable2;
|
|
|
|
u32 wake_en;
|
|
|
|
u32 ctrl;
|
|
|
|
u32 oe;
|
|
|
|
u32 leveldetect0;
|
|
|
|
u32 leveldetect1;
|
|
|
|
u32 risingdetect;
|
|
|
|
u32 fallingdetect;
|
|
|
|
u32 dataout;
|
|
|
|
u32 setwkuena;
|
|
|
|
u32 setdataout;
|
2007-11-30 01:15:11 +01:00
|
|
|
};
|
|
|
|
|
2008-09-26 14:17:48 +02:00
|
|
|
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
|
2007-11-30 01:15:11 +01:00
|
|
|
#endif
|
|
|
|
|
2009-05-28 23:16:04 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
|
|
static struct gpio_bank gpio_bank_44xx[6] = {
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2010-02-17 22:44:12 +01:00
|
|
|
{ OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
|
2010-02-15 18:27:25 +01:00
|
|
|
METHOD_GPIO_44XX },
|
2009-05-28 23:16:04 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static struct gpio_bank *gpio_bank;
|
|
|
|
static int gpio_bank_count;
|
|
|
|
|
|
|
|
static inline struct gpio_bank *get_gpio_bank(int gpio)
|
|
|
|
{
|
2006-04-02 18:46:23 +02:00
|
|
|
if (cpu_is_omap15xx()) {
|
2005-07-10 20:58:15 +02:00
|
|
|
if (OMAP_GPIO_IS_MPUIO(gpio))
|
|
|
|
return &gpio_bank[0];
|
|
|
|
return &gpio_bank[1];
|
|
|
|
}
|
|
|
|
if (cpu_is_omap16xx()) {
|
|
|
|
if (OMAP_GPIO_IS_MPUIO(gpio))
|
|
|
|
return &gpio_bank[0];
|
|
|
|
return &gpio_bank[1 + (gpio >> 4)];
|
|
|
|
}
|
2009-03-24 02:07:40 +01:00
|
|
|
if (cpu_is_omap7xx()) {
|
2005-07-10 20:58:15 +02:00
|
|
|
if (OMAP_GPIO_IS_MPUIO(gpio))
|
|
|
|
return &gpio_bank[0];
|
|
|
|
return &gpio_bank[1 + (gpio >> 5)];
|
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
if (cpu_is_omap24xx())
|
|
|
|
return &gpio_bank[gpio >> 5];
|
2009-05-28 23:16:04 +02:00
|
|
|
if (cpu_is_omap34xx() || cpu_is_omap44xx())
|
2007-11-30 01:15:11 +01:00
|
|
|
return &gpio_bank[gpio >> 5];
|
2008-12-11 02:35:27 +01:00
|
|
|
BUG();
|
|
|
|
return NULL;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_gpio_index(int gpio)
|
|
|
|
{
|
2009-03-24 02:07:40 +01:00
|
|
|
if (cpu_is_omap7xx())
|
2005-07-10 20:58:15 +02:00
|
|
|
return gpio & 0x1f;
|
2005-09-07 18:20:26 +02:00
|
|
|
if (cpu_is_omap24xx())
|
|
|
|
return gpio & 0x1f;
|
2009-05-28 23:16:04 +02:00
|
|
|
if (cpu_is_omap34xx() || cpu_is_omap44xx())
|
2007-11-30 01:15:11 +01:00
|
|
|
return gpio & 0x1f;
|
2005-09-07 18:20:26 +02:00
|
|
|
return gpio & 0x0f;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int gpio_valid(int gpio)
|
|
|
|
{
|
|
|
|
if (gpio < 0)
|
|
|
|
return -1;
|
2008-01-13 00:35:04 +01:00
|
|
|
if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
|
2006-09-25 11:41:30 +02:00
|
|
|
if (gpio >= OMAP_MAX_GPIO_LINES + 16)
|
2005-07-10 20:58:15 +02:00
|
|
|
return -1;
|
|
|
|
return 0;
|
|
|
|
}
|
2006-04-02 18:46:23 +02:00
|
|
|
if (cpu_is_omap15xx() && gpio < 16)
|
2005-07-10 20:58:15 +02:00
|
|
|
return 0;
|
|
|
|
if ((cpu_is_omap16xx()) && gpio < 64)
|
|
|
|
return 0;
|
2009-03-24 02:07:40 +01:00
|
|
|
if (cpu_is_omap7xx() && gpio < 192)
|
2005-07-10 20:58:15 +02:00
|
|
|
return 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
if (cpu_is_omap24xx() && gpio < 128)
|
|
|
|
return 0;
|
2009-05-28 23:16:04 +02:00
|
|
|
if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
|
2007-11-30 01:15:11 +01:00
|
|
|
return 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int check_gpio(int gpio)
|
|
|
|
{
|
2009-11-17 23:39:03 +01:00
|
|
|
if (unlikely(gpio_valid(gpio) < 0)) {
|
2005-07-10 20:58:15 +02:00
|
|
|
printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
|
|
|
|
dump_stack();
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_IO_CNTL;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_DIR_CONTROL;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_DIRECTION;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_DIR_CONTROL;
|
2009-03-24 02:07:40 +01:00
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
reg += OMAP24XX_GPIO_OE;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4)
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
reg += OMAP4_GPIO_OE;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
WARN_ON(1);
|
|
|
|
return;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (is_input)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l = 0;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_OUTPUT;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_DATA_OUTPUT;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
if (enable)
|
|
|
|
reg += OMAP1610_GPIO_SET_DATAOUT;
|
|
|
|
else
|
|
|
|
reg += OMAP1610_GPIO_CLEAR_DATAOUT;
|
|
|
|
l = 1 << gpio;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_DATA_OUTPUT;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
if (enable)
|
|
|
|
reg += OMAP24XX_GPIO_SETDATAOUT;
|
|
|
|
else
|
|
|
|
reg += OMAP24XX_GPIO_CLEARDATAOUT;
|
|
|
|
l = 1 << gpio;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
if (enable)
|
|
|
|
reg += OMAP4_GPIO_SETDATAOUT;
|
|
|
|
else
|
|
|
|
reg += OMAP4_GPIO_CLEARDATAOUT;
|
|
|
|
l = 1 << gpio;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2006-12-07 02:13:59 +01:00
|
|
|
WARN_ON(1);
|
2005-07-10 20:58:15 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
2009-08-05 15:53:24 +02:00
|
|
|
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
2006-12-07 02:13:59 +01:00
|
|
|
return -EINVAL;
|
2005-07-10 20:58:15 +02:00
|
|
|
reg = bank->base;
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_INPUT_LATCH;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_DATA_INPUT;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_DATAIN;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_DATA_INPUT;
|
2009-03-24 02:07:40 +01:00
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
reg += OMAP24XX_GPIO_DATAIN;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
reg += OMAP4_GPIO_DATAIN;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2006-12-07 02:13:59 +01:00
|
|
|
return -EINVAL;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
return (__raw_readl(reg)
|
|
|
|
& (1 << get_gpio_index(gpio))) != 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2009-08-05 15:53:24 +02:00
|
|
|
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
void __iomem *reg;
|
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
|
|
|
return -EINVAL;
|
|
|
|
reg = bank->base;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_OUTPUT;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_DATA_OUTPUT;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_DATAOUT;
|
|
|
|
break;
|
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_DATA_OUTPUT;
|
2009-08-05 15:53:24 +02:00
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2009-08-05 15:53:24 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-08-05 15:53:24 +02:00
|
|
|
reg += OMAP24XX_GPIO_DATAOUT;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
|
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
#define MOD_REG_BIT(reg, bit_mask, set) \
|
|
|
|
do { \
|
|
|
|
int l = __raw_readl(base + reg); \
|
|
|
|
if (set) l |= bit_mask; \
|
|
|
|
else l &= ~bit_mask; \
|
|
|
|
__raw_writel(l, base + reg); \
|
|
|
|
} while(0)
|
|
|
|
|
2007-05-05 20:40:29 +02:00
|
|
|
void omap_set_gpio_debounce(int gpio, int enable)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
void __iomem *reg;
|
2008-12-11 02:35:27 +01:00
|
|
|
unsigned long flags;
|
2007-05-05 20:40:29 +02:00
|
|
|
u32 val, l = 1 << get_gpio_index(gpio);
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
return;
|
|
|
|
|
|
|
|
bank = get_gpio_bank(gpio);
|
|
|
|
reg = bank->base;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap44xx())
|
|
|
|
reg += OMAP4_GPIO_DEBOUNCENABLE;
|
|
|
|
else
|
|
|
|
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
|
|
|
|
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!(bank->mod_usage & l)) {
|
|
|
|
printk(KERN_ERR "GPIO %d not requested\n", gpio);
|
|
|
|
return;
|
|
|
|
}
|
2008-12-11 02:35:27 +01:00
|
|
|
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2007-05-05 20:40:29 +02:00
|
|
|
val = __raw_readl(reg);
|
|
|
|
|
2008-12-11 02:35:24 +01:00
|
|
|
if (enable && !(val & l))
|
2007-05-05 20:40:29 +02:00
|
|
|
val |= l;
|
2008-12-11 02:35:27 +01:00
|
|
|
else if (!enable && (val & l))
|
2007-05-05 20:40:29 +02:00
|
|
|
val &= ~l;
|
2008-12-11 02:35:24 +01:00
|
|
|
else
|
2008-12-11 02:35:27 +01:00
|
|
|
goto done;
|
2008-12-11 02:35:24 +01:00
|
|
|
|
2009-05-28 23:16:04 +02:00
|
|
|
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
2008-12-11 02:35:27 +01:00
|
|
|
if (enable)
|
|
|
|
clk_enable(bank->dbck);
|
|
|
|
else
|
|
|
|
clk_disable(bank->dbck);
|
|
|
|
}
|
2007-05-05 20:40:29 +02:00
|
|
|
|
|
|
|
__raw_writel(val, reg);
|
2008-12-11 02:35:27 +01:00
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2007-05-05 20:40:29 +02:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(omap_set_gpio_debounce);
|
|
|
|
|
|
|
|
void omap_set_gpio_debounce_time(int gpio, int enc_time)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
void __iomem *reg;
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
return;
|
|
|
|
|
|
|
|
bank = get_gpio_bank(gpio);
|
|
|
|
reg = bank->base;
|
|
|
|
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!bank->mod_usage) {
|
|
|
|
printk(KERN_ERR "GPIO not requested\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-05-05 20:40:29 +02:00
|
|
|
enc_time &= 0xff;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap44xx())
|
|
|
|
reg += OMAP4_GPIO_DEBOUNCINGTIME;
|
|
|
|
else
|
|
|
|
reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
|
|
|
|
|
2007-05-05 20:40:29 +02:00
|
|
|
__raw_writel(enc_time, reg);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(omap_set_gpio_debounce_time);
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2007-05-05 20:40:29 +02:00
|
|
|
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
|
|
|
|
int trigger)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2006-12-07 02:13:52 +01:00
|
|
|
void __iomem *base = bank->base;
|
2005-09-07 18:20:26 +02:00
|
|
|
u32 gpio_bit = 1 << gpio;
|
2009-07-28 15:27:30 +02:00
|
|
|
u32 val;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_LOW);
|
|
|
|
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_HIGH);
|
|
|
|
MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_RISING);
|
|
|
|
MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_FALLING);
|
|
|
|
} else {
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_LOW);
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_HIGH);
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_RISING);
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_FALLING);
|
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
if (trigger != 0)
|
|
|
|
__raw_writel(1 << gpio, bank->base+
|
|
|
|
OMAP4_GPIO_IRQWAKEN0);
|
|
|
|
else {
|
|
|
|
val = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_IRQWAKEN0);
|
|
|
|
__raw_writel(val & (~(1 << gpio)), bank->base +
|
|
|
|
OMAP4_GPIO_IRQWAKEN0);
|
|
|
|
}
|
|
|
|
} else {
|
2009-06-24 19:13:39 +02:00
|
|
|
/*
|
|
|
|
* GPIO wakeup request can only be generated on edge
|
|
|
|
* transitions
|
|
|
|
*/
|
|
|
|
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
2009-07-28 15:27:30 +02:00
|
|
|
__raw_writel(1 << gpio, bank->base
|
2007-05-05 20:40:29 +02:00
|
|
|
+ OMAP24XX_GPIO_SETWKUENA);
|
2009-07-28 15:27:30 +02:00
|
|
|
else
|
|
|
|
__raw_writel(1 << gpio, bank->base
|
2007-05-05 20:40:29 +02:00
|
|
|
+ OMAP24XX_GPIO_CLEARWKUENA);
|
2009-07-28 15:27:30 +02:00
|
|
|
}
|
2008-12-22 13:27:12 +01:00
|
|
|
}
|
|
|
|
/* This part needs to be executed always for OMAP34xx */
|
|
|
|
if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
|
2009-06-24 19:13:39 +02:00
|
|
|
/*
|
|
|
|
* Log the edge gpio and manually trigger the IRQ
|
|
|
|
* after resume if the input level changes
|
|
|
|
* to avoid irq lost during PER RET/OFF mode
|
|
|
|
* Applies for omap2 non-wakeup gpio and all omap3 gpios
|
|
|
|
*/
|
|
|
|
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->enabled_non_wakeup_gpios |= gpio_bit;
|
|
|
|
else
|
|
|
|
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
|
|
|
|
}
|
2007-05-05 20:40:29 +02:00
|
|
|
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
bank->level_mask =
|
|
|
|
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
|
|
|
|
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
|
|
|
|
} else {
|
|
|
|
bank->level_mask =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2010-01-29 23:20:05 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
/*
|
|
|
|
* This only applies to chips that can't do both rising and falling edge
|
|
|
|
* detection at once. For all other chips, this function is a noop.
|
|
|
|
*/
|
|
|
|
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l = 0;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_GPIO_INT_EDGE;
|
|
|
|
break;
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_CONTROL;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_CONTROL;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if ((l >> gpio) & 1)
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
else
|
|
|
|
l |= 1 << gpio;
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
2010-01-29 23:20:05 +01:00
|
|
|
#endif
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l = 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_GPIO_INT_EDGE;
|
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l &= ~(1 << gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_CONTROL;
|
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l &= ~(1 << gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2006-12-07 02:13:52 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
if (gpio & 0x08)
|
|
|
|
reg += OMAP1610_GPIO_EDGE_CTRL2;
|
|
|
|
else
|
|
|
|
reg += OMAP1610_GPIO_EDGE_CTRL1;
|
|
|
|
gpio &= 0x07;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
l &= ~(3 << (gpio << 1));
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 2 << (gpio << 1);
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 1 << (gpio << 1);
|
2006-12-07 02:13:52 +01:00
|
|
|
if (trigger)
|
|
|
|
/* Enable wake-up during idle for dynamic tick */
|
|
|
|
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
|
|
|
|
else
|
|
|
|
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_CONTROL;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2009-03-24 02:07:40 +01:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
else
|
|
|
|
goto bad;
|
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2006-12-07 02:13:52 +01:00
|
|
|
set_24xx_gpio_triggering(bank, gpio, trigger);
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2005-09-07 18:20:26 +02:00
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
__raw_writel(l, reg);
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
|
|
return -EINVAL;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
static int gpio_irq_type(unsigned irq, unsigned type)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
2005-09-07 18:20:26 +02:00
|
|
|
unsigned gpio;
|
|
|
|
int retval;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
|
2005-09-07 18:20:26 +02:00
|
|
|
gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
|
|
|
|
else
|
|
|
|
gpio = irq - IH_GPIO_BASE;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (type & ~IRQ_TYPE_SENSE_MASK)
|
2006-04-02 18:46:23 +02:00
|
|
|
return -EINVAL;
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
/* OMAP1 allows only only edge triggering */
|
2007-11-30 01:15:11 +01:00
|
|
|
if (!cpu_class_is_omap2()
|
2006-12-07 02:13:59 +01:00
|
|
|
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2006-12-07 02:14:10 +01:00
|
|
|
bank = get_irq_chip_data(irq);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
|
2006-12-07 02:13:53 +01:00
|
|
|
if (retval == 0) {
|
|
|
|
irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
|
|
|
|
irq_desc[irq].status |= type;
|
|
|
|
}
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2008-01-17 06:56:16 +01:00
|
|
|
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
|
|
|
__set_irq_handler_unlocked(irq, handle_level_irq);
|
|
|
|
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
|
|
|
__set_irq_handler_unlocked(irq, handle_edge_irq);
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
return retval;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
/* MPUIO irqstatus is reset by reading the status register,
|
|
|
|
* so do nothing here */
|
|
|
|
return;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_STATUS;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_IRQSTATUS1;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_STATUS;
|
2009-03-24 02:07:40 +01:00
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
reg += OMAP24XX_GPIO_IRQSTATUS1;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4)
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
reg += OMAP4_GPIO_IRQSTATUS0;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2006-12-07 02:13:59 +01:00
|
|
|
WARN_ON(1);
|
2005-07-10 20:58:15 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
__raw_writel(gpio_mask, reg);
|
2006-09-25 11:41:46 +02:00
|
|
|
|
|
|
|
/* Workaround for clearing DSP GPIO interrupts to allow retention */
|
2010-02-15 18:27:25 +01:00
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
|
reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
|
|
|
|
else if (cpu_is_omap44xx())
|
|
|
|
reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
|
|
|
|
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
2009-04-23 20:10:50 +02:00
|
|
|
__raw_writel(gpio_mask, reg);
|
|
|
|
|
|
|
|
/* Flush posted write for the irq status to avoid spurious interrupts */
|
|
|
|
__raw_readl(reg);
|
2009-07-28 15:27:30 +02:00
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
_clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
|
|
|
|
}
|
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
2006-06-27 01:16:07 +02:00
|
|
|
int inv = 0;
|
|
|
|
u32 l;
|
|
|
|
u32 mask;
|
2006-06-27 01:16:00 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2006-06-27 01:16:00 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_GPIO_MASKIT;
|
2006-06-27 01:16:07 +02:00
|
|
|
mask = 0xffff;
|
|
|
|
inv = 1;
|
2006-06-27 01:16:00 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2006-06-27 01:16:00 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_MASK;
|
2006-06-27 01:16:07 +02:00
|
|
|
mask = 0xffff;
|
|
|
|
inv = 1;
|
2006-06-27 01:16:00 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2006-06-27 01:16:00 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_IRQENABLE1;
|
2006-06-27 01:16:07 +02:00
|
|
|
mask = 0xffff;
|
2006-06-27 01:16:00 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_MASK;
|
2009-03-24 02:07:40 +01:00
|
|
|
mask = 0xffffffff;
|
|
|
|
inv = 1;
|
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2006-06-27 01:16:00 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
reg += OMAP24XX_GPIO_IRQENABLE1;
|
2006-06-27 01:16:07 +02:00
|
|
|
mask = 0xffffffff;
|
2006-06-27 01:16:00 +02:00
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4)
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
reg += OMAP4_GPIO_IRQSTATUSSET0;
|
|
|
|
mask = 0xffffffff;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2006-06-27 01:16:00 +02:00
|
|
|
default:
|
2006-12-07 02:13:59 +01:00
|
|
|
WARN_ON(1);
|
2006-06-27 01:16:00 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-06-27 01:16:07 +02:00
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (inv)
|
|
|
|
l = ~l;
|
|
|
|
l &= mask;
|
|
|
|
return l;
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_GPIO_MASKIT;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l &= ~(gpio_mask);
|
|
|
|
else
|
|
|
|
l |= gpio_mask;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_MASK;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l &= ~(gpio_mask);
|
|
|
|
else
|
|
|
|
l |= gpio_mask;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
if (enable)
|
|
|
|
reg += OMAP1610_GPIO_SET_IRQENABLE1;
|
|
|
|
else
|
|
|
|
reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
|
|
|
|
l = gpio_mask;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_MASK;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l &= ~(gpio_mask);
|
|
|
|
else
|
|
|
|
l |= gpio_mask;
|
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
|
|
|
if (enable)
|
|
|
|
reg += OMAP24XX_GPIO_SETIRQENABLE1;
|
|
|
|
else
|
|
|
|
reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
|
|
|
|
l = gpio_mask;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
if (enable)
|
|
|
|
reg += OMAP4_GPIO_IRQSTATUSSET0;
|
|
|
|
else
|
|
|
|
reg += OMAP4_GPIO_IRQSTATUSCLR0;
|
|
|
|
l = gpio_mask;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2006-12-07 02:13:59 +01:00
|
|
|
WARN_ON(1);
|
2005-07-10 20:58:15 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
|
|
|
_enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
|
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/*
|
|
|
|
* Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
|
|
|
|
* 1510 does not seem to have a wake-up register. If JTAG is connected
|
|
|
|
* to the target, system will wake up always on GPIO events. While
|
|
|
|
* system is running all registered GPIO interrupts need to have wake-up
|
|
|
|
* enabled. When system is suspended, only selected GPIO interrupts need
|
|
|
|
* to have wake-up enabled.
|
|
|
|
*/
|
|
|
|
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2010-01-08 19:29:05 +01:00
|
|
|
unsigned long uninitialized_var(flags);
|
2008-03-03 13:33:30 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:52 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2006-12-07 02:14:11 +01:00
|
|
|
case METHOD_MPUIO:
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-04-23 20:10:49 +02:00
|
|
|
if (enable)
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->suspend_wakeup |= (1 << gpio);
|
2009-04-23 20:10:49 +02:00
|
|
|
else
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->suspend_wakeup &= ~(1 << gpio);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2006-12-07 02:13:52 +01:00
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2006-12-07 02:14:11 +01:00
|
|
|
if (bank->non_wakeup_gpios & (1 << gpio)) {
|
|
|
|
printk(KERN_ERR "Unable to modify wakeup on "
|
|
|
|
"non-wakeup GPIO%d\n",
|
|
|
|
(bank - gpio_bank) * 32 + gpio);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-04-23 20:10:49 +02:00
|
|
|
if (enable)
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->suspend_wakeup |= (1 << gpio);
|
2009-04-23 20:10:49 +02:00
|
|
|
else
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->suspend_wakeup &= ~(1 << gpio);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:13:52 +01:00
|
|
|
return 0;
|
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
|
|
|
|
bank->method);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
static void _reset_gpio(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
2008-07-27 05:23:31 +02:00
|
|
|
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
|
2006-09-25 11:41:38 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
|
|
|
|
static int gpio_wake_enable(unsigned int irq, unsigned int enable)
|
|
|
|
{
|
|
|
|
unsigned int gpio = irq - IH_GPIO_BASE;
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
int retval;
|
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
|
|
|
return -ENODEV;
|
2006-12-07 02:14:10 +01:00
|
|
|
bank = get_irq_chip_data(irq);
|
2005-09-07 18:20:26 +02:00
|
|
|
retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2008-03-03 21:43:23 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
/* Set trigger to none. You need to enable the desired trigger with
|
|
|
|
* request_irq() or set_irq_type().
|
|
|
|
*/
|
2008-12-11 02:35:27 +01:00
|
|
|
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2005-11-10 15:26:50 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
if (bank->method == METHOD_GPIO_1510) {
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Claim the pin for MPU */
|
2005-07-10 20:58:15 +02:00
|
|
|
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
#endif
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!cpu_class_is_omap1()) {
|
|
|
|
if (!bank->mod_usage) {
|
|
|
|
u32 ctrl;
|
|
|
|
ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
ctrl &= 0xFFFFFFFE;
|
|
|
|
/* Module is enabled, clocks are not gated */
|
|
|
|
__raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
}
|
|
|
|
bank->mod_usage |= 1 << offset;
|
|
|
|
}
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
if (bank->method == METHOD_GPIO_1610) {
|
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
|
void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(1 << offset, reg);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2010-02-15 18:27:25 +01:00
|
|
|
if ((bank->method == METHOD_GPIO_24XX) ||
|
|
|
|
(bank->method == METHOD_GPIO_44XX)) {
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
|
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(1 << offset, reg);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
#endif
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!cpu_class_is_omap1()) {
|
|
|
|
bank->mod_usage &= ~(1 << offset);
|
|
|
|
if (!bank->mod_usage) {
|
|
|
|
u32 ctrl;
|
|
|
|
ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
/* Module is disabled, clocks are gated */
|
|
|
|
ctrl |= 1;
|
|
|
|
__raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
}
|
|
|
|
}
|
2008-12-11 02:35:27 +01:00
|
|
|
_reset_gpio(bank, bank->chip.base + offset);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to unmask the GPIO bank interrupt as soon as possible to
|
|
|
|
* avoid missing GPIO interrupts for other lines in the bank.
|
|
|
|
* Then we need to mask-read-clear-unmask the triggered GPIO lines
|
|
|
|
* in the bank to avoid missing nested interrupts for a GPIO line.
|
|
|
|
* If we wait to unmask individual GPIO lines in the bank after the
|
|
|
|
* line's interrupt handler has been run, we may miss some nested
|
|
|
|
* interrupts.
|
|
|
|
*/
|
2006-11-23 12:41:32 +01:00
|
|
|
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *isr_reg = NULL;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 isr;
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
unsigned int gpio_irq, gpio_index;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
2006-06-27 01:16:00 +02:00
|
|
|
u32 retrigger = 0;
|
|
|
|
int unmasked = 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
desc->chip->ack(irq);
|
|
|
|
|
2006-07-01 23:32:41 +02:00
|
|
|
bank = get_irq_data(irq);
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
if (bank->method == METHOD_MPUIO)
|
|
|
|
isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-11-10 15:26:50 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
if (bank->method == METHOD_GPIO_1510)
|
|
|
|
isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX)
|
|
|
|
if (bank->method == METHOD_GPIO_1610)
|
|
|
|
isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
|
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
if (bank->method == METHOD_GPIO_7XX)
|
|
|
|
isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
|
2009-03-24 02:07:40 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
if (bank->method == METHOD_GPIO_24XX)
|
|
|
|
isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4)
|
2010-02-15 18:27:25 +01:00
|
|
|
if (bank->method == METHOD_GPIO_44XX)
|
2009-07-28 15:27:30 +02:00
|
|
|
isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
|
|
|
while(1) {
|
2006-04-02 18:46:23 +02:00
|
|
|
u32 isr_saved, level_mask = 0;
|
2006-06-27 01:16:00 +02:00
|
|
|
u32 enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
enabled = _get_gpio_irqbank_mask(bank);
|
|
|
|
isr_saved = isr = __raw_readl(isr_reg) & enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
|
|
|
|
isr &= 0x0000ffff;
|
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
if (cpu_class_is_omap2()) {
|
2008-01-17 06:56:15 +01:00
|
|
|
level_mask = bank->level_mask & enabled;
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
/* clear edge sensitive interrupts before handler(s) are
|
|
|
|
called so that we don't miss any interrupt occurred while
|
|
|
|
executing them */
|
|
|
|
_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
|
|
|
|
_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
|
|
|
|
_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
|
|
|
|
|
|
|
|
/* if there is only edge sensitive GPIO pin interrupts
|
|
|
|
configured, we could unmask GPIO bank interrupt immediately */
|
2006-06-27 01:16:00 +02:00
|
|
|
if (!level_mask && !unmasked) {
|
|
|
|
unmasked = 1;
|
2006-04-02 18:46:23 +02:00
|
|
|
desc->chip->unmask(irq);
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
isr |= retrigger;
|
|
|
|
retrigger = 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
if (!isr)
|
|
|
|
break;
|
|
|
|
|
|
|
|
gpio_irq = bank->virtual_irq_start;
|
|
|
|
for (; isr != 0; isr >>= 1, gpio_irq++) {
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
if (!(isr & 1))
|
|
|
|
continue;
|
2006-07-03 02:22:22 +02:00
|
|
|
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
/*
|
|
|
|
* Some chips can't respond to both rising and falling
|
|
|
|
* at the same time. If this irq was requested with
|
|
|
|
* both flags, we need to flip the ICR data for the IRQ
|
|
|
|
* to respond to the IRQ for the opposite direction.
|
|
|
|
* This will be indicated in the bank toggle_mask.
|
|
|
|
*/
|
|
|
|
if (bank->toggle_mask & (1 << gpio_index))
|
|
|
|
_toggle_gpio_edge_triggering(bank, gpio_index);
|
|
|
|
#endif
|
|
|
|
|
2008-10-09 14:36:24 +02:00
|
|
|
generic_handle_irq(gpio_irq);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2005-11-10 15:26:50 +01:00
|
|
|
}
|
2006-06-27 01:16:00 +02:00
|
|
|
/* if bank has any level sensitive GPIO pin interrupt
|
|
|
|
configured, we must unmask the bank interrupt only after
|
|
|
|
handler(s) are executed in order to avoid spurious bank
|
|
|
|
interrupt */
|
|
|
|
if (!unmasked)
|
|
|
|
desc->chip->unmask(irq);
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
static void gpio_irq_shutdown(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = irq - IH_GPIO_BASE;
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2006-09-25 11:41:38 +02:00
|
|
|
|
|
|
|
_reset_gpio(bank, gpio);
|
|
|
|
}
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static void gpio_ack_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = irq - IH_GPIO_BASE;
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gpio_mask_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = irq - IH_GPIO_BASE;
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
2009-06-05 00:57:10 +02:00
|
|
|
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gpio_unmask_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = irq - IH_GPIO_BASE;
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2008-01-17 06:56:15 +01:00
|
|
|
unsigned int irq_mask = 1 << get_gpio_index(gpio);
|
2009-06-05 00:57:10 +02:00
|
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
|
|
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
|
|
|
|
|
|
|
|
if (trigger)
|
|
|
|
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
|
2008-01-17 06:56:15 +01:00
|
|
|
|
|
|
|
/* For level-triggered GPIOs, the clearing must be done after
|
|
|
|
* the HW source is cleared, thus after the handler has run */
|
|
|
|
if (bank->level_mask & irq_mask) {
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-01-17 06:56:14 +01:00
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
static struct irq_chip gpio_irq_chip = {
|
|
|
|
.name = "GPIO",
|
|
|
|
.shutdown = gpio_irq_shutdown,
|
|
|
|
.ack = gpio_ack_irq,
|
|
|
|
.mask = gpio_mask_irq,
|
|
|
|
.unmask = gpio_unmask_irq,
|
|
|
|
.set_type = gpio_irq_type,
|
|
|
|
.set_wake = gpio_wake_enable,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
|
|
|
|
/* MPUIO uses the always-on 32k clock */
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static void mpuio_ack_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
/* The ISR is reset automatically, so do nothing here. */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mpuio_mask_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mpuio_unmask_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
|
2006-12-07 02:14:10 +01:00
|
|
|
struct gpio_bank *bank = get_irq_chip_data(irq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
static struct irq_chip mpuio_irq_chip = {
|
|
|
|
.name = "MPUIO",
|
|
|
|
.ack = mpuio_ack_irq,
|
|
|
|
.mask = mpuio_mask_irq,
|
|
|
|
.unmask = mpuio_unmask_irq,
|
2005-09-07 18:20:26 +02:00
|
|
|
.set_type = gpio_irq_type,
|
2006-12-07 02:14:11 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
/* REVISIT: assuming only 16xx supports MPUIO wake events */
|
|
|
|
.set_wake = gpio_wake_enable,
|
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
};
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
|
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_suspend_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
|
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
bank->saved_wakeup = __raw_readl(mask_reg);
|
|
|
|
__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_resume_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
|
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
__raw_writel(bank->saved_wakeup, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-15 03:00:08 +01:00
|
|
|
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
|
2009-07-08 13:22:04 +02:00
|
|
|
.suspend_noirq = omap_mpuio_suspend_noirq,
|
|
|
|
.resume_noirq = omap_mpuio_resume_noirq,
|
|
|
|
};
|
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
/* use platform_driver for this, now that there's no longer any
|
|
|
|
* point to sys_device (other than not disturbing old code).
|
|
|
|
*/
|
|
|
|
static struct platform_driver omap_mpuio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mpuio",
|
2009-07-08 13:22:04 +02:00
|
|
|
.pm = &omap_mpuio_dev_pm_ops,
|
2006-12-07 02:14:11 +01:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device omap_mpuio_device = {
|
|
|
|
.name = "mpuio",
|
|
|
|
.id = -1,
|
|
|
|
.dev = {
|
|
|
|
.driver = &omap_mpuio_driver.driver,
|
|
|
|
}
|
|
|
|
/* could list the /proc/iomem resources */
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline void mpuio_init(void)
|
|
|
|
{
|
2007-04-02 21:46:47 +02:00
|
|
|
platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
|
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
if (platform_driver_register(&omap_mpuio_driver) == 0)
|
|
|
|
(void) platform_device_register(&omap_mpuio_device);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
static inline void mpuio_init(void) {}
|
|
|
|
#endif /* 16xx */
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
#else
|
|
|
|
|
|
|
|
extern struct irq_chip mpuio_irq_chip;
|
|
|
|
|
|
|
|
#define bank_is_mpuio(bank) 0
|
2006-12-07 02:14:11 +01:00
|
|
|
static inline void mpuio_init(void) {}
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
/* REVISIT these are stupid implementations! replace by ones that
|
|
|
|
* don't switch on METHOD_* and which mostly avoid spinlocks
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_direction(bank, offset, 1);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-05 15:53:24 +02:00
|
|
|
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
|
|
|
case METHOD_MPUIO:
|
|
|
|
reg += OMAP_MPUIO_IO_CNTL;
|
|
|
|
break;
|
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_DIR_CONTROL;
|
|
|
|
break;
|
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
reg += OMAP1610_GPIO_DIRECTION;
|
|
|
|
break;
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_DIR_CONTROL;
|
2009-08-05 15:53:24 +02:00
|
|
|
break;
|
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-08-05 15:53:24 +02:00
|
|
|
reg += OMAP24XX_GPIO_OE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return __raw_readl(reg) & mask;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static int gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
2009-08-05 15:53:24 +02:00
|
|
|
struct gpio_bank *bank;
|
|
|
|
void __iomem *reg;
|
|
|
|
int gpio;
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
gpio = chip->base + offset;
|
|
|
|
bank = get_gpio_bank(gpio);
|
|
|
|
reg = bank->base;
|
|
|
|
mask = 1 << get_gpio_index(gpio);
|
|
|
|
|
|
|
|
if (gpio_is_input(bank, mask))
|
|
|
|
return _get_gpio_datain(bank, gpio);
|
|
|
|
else
|
|
|
|
return _get_gpio_dataout(bank, gpio);
|
2008-03-03 21:43:23 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_dataout(bank, offset, value);
|
|
|
|
_set_gpio_direction(bank, offset, 0);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_dataout(bank, offset, value);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:25 +01:00
|
|
|
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
return bank->virtual_irq_start + offset;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
2005-11-10 15:26:50 +01:00
|
|
|
static int initialized;
|
2010-02-12 21:26:46 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
|
2005-11-10 15:26:50 +01:00
|
|
|
static struct clk * gpio_ick;
|
2007-11-30 01:15:11 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(CONFIG_ARCH_OMAP2)
|
2005-11-10 15:26:50 +01:00
|
|
|
static struct clk * gpio_fck;
|
2007-11-30 01:15:11 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2430)
|
2006-12-07 02:14:08 +01:00
|
|
|
static struct clk * gpio5_ick;
|
|
|
|
static struct clk * gpio5_fck;
|
|
|
|
#endif
|
|
|
|
|
2009-05-28 23:16:04 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
2007-11-30 01:15:11 +01:00
|
|
|
static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
|
|
|
|
#endif
|
|
|
|
|
2009-10-20 00:25:20 +02:00
|
|
|
static void __init omap_gpio_show_rev(void)
|
|
|
|
{
|
|
|
|
u32 rev;
|
|
|
|
|
|
|
|
if (cpu_is_omap16xx())
|
|
|
|
rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
|
|
|
|
else if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
|
rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
|
|
|
else if (cpu_is_omap44xx())
|
|
|
|
rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
|
|
|
|
else
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
|
|
|
|
(rev >> 4) & 0x0f, rev & 0x0f);
|
|
|
|
}
|
|
|
|
|
2008-02-26 20:10:50 +01:00
|
|
|
/* This lock class tells lockdep that GPIO irqs are in a different
|
|
|
|
* category than their parents, so it won't report false recursion.
|
|
|
|
*/
|
|
|
|
static struct lock_class_key gpio_lock_class;
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static int __init _omap_gpio_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
2008-03-03 21:43:23 +01:00
|
|
|
int gpio = 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
2009-10-20 00:25:20 +02:00
|
|
|
int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
|
2007-11-30 01:15:11 +01:00
|
|
|
char clk_name[11];
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
initialized = 1;
|
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP1)
|
2006-04-02 18:46:23 +02:00
|
|
|
if (cpu_is_omap15xx()) {
|
2005-11-10 15:26:50 +01:00
|
|
|
gpio_ick = clk_get(NULL, "arm_gpio_ck");
|
|
|
|
if (IS_ERR(gpio_ick))
|
2005-09-07 18:20:26 +02:00
|
|
|
printk("Could not get arm_gpio_ck\n");
|
|
|
|
else
|
2006-01-18 00:33:51 +01:00
|
|
|
clk_enable(gpio_ick);
|
2005-11-10 15:26:50 +01:00
|
|
|
}
|
2007-11-30 01:15:11 +01:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP2)
|
|
|
|
if (cpu_class_is_omap2()) {
|
2005-11-10 15:26:50 +01:00
|
|
|
gpio_ick = clk_get(NULL, "gpios_ick");
|
|
|
|
if (IS_ERR(gpio_ick))
|
|
|
|
printk("Could not get gpios_ick\n");
|
|
|
|
else
|
2006-01-18 00:33:51 +01:00
|
|
|
clk_enable(gpio_ick);
|
2005-11-10 15:26:50 +01:00
|
|
|
gpio_fck = clk_get(NULL, "gpios_fck");
|
2006-09-25 11:51:08 +02:00
|
|
|
if (IS_ERR(gpio_fck))
|
2005-11-10 15:26:50 +01:00
|
|
|
printk("Could not get gpios_fck\n");
|
|
|
|
else
|
2006-01-18 00:33:51 +01:00
|
|
|
clk_enable(gpio_fck);
|
2006-12-07 02:14:08 +01:00
|
|
|
|
|
|
|
/*
|
2007-11-30 01:15:11 +01:00
|
|
|
* On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
|
2006-12-07 02:14:08 +01:00
|
|
|
*/
|
2007-11-30 01:15:11 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2430)
|
2006-12-07 02:14:08 +01:00
|
|
|
if (cpu_is_omap2430()) {
|
|
|
|
gpio5_ick = clk_get(NULL, "gpio5_ick");
|
|
|
|
if (IS_ERR(gpio5_ick))
|
|
|
|
printk("Could not get gpio5_ick\n");
|
|
|
|
else
|
|
|
|
clk_enable(gpio5_ick);
|
|
|
|
gpio5_fck = clk_get(NULL, "gpio5_fck");
|
|
|
|
if (IS_ERR(gpio5_fck))
|
|
|
|
printk("Could not get gpio5_fck\n");
|
|
|
|
else
|
|
|
|
clk_enable(gpio5_fck);
|
|
|
|
}
|
|
|
|
#endif
|
2007-11-30 01:15:11 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-05-28 23:16:04 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
|
|
|
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
2007-11-30 01:15:11 +01:00
|
|
|
for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
|
|
|
|
sprintf(clk_name, "gpio%d_ick", i + 1);
|
|
|
|
gpio_iclks[i] = clk_get(NULL, clk_name);
|
|
|
|
if (IS_ERR(gpio_iclks[i]))
|
|
|
|
printk(KERN_ERR "Could not get %s\n", clk_name);
|
|
|
|
else
|
|
|
|
clk_enable(gpio_iclks[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2005-11-10 15:26:50 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2006-04-02 18:46:23 +02:00
|
|
|
if (cpu_is_omap15xx()) {
|
2005-07-10 20:58:15 +02:00
|
|
|
gpio_bank_count = 2;
|
|
|
|
gpio_bank = gpio_bank_1510;
|
2009-10-20 00:25:20 +02:00
|
|
|
bank_size = SZ_2K;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX)
|
|
|
|
if (cpu_is_omap16xx()) {
|
|
|
|
gpio_bank_count = 5;
|
|
|
|
gpio_bank = gpio_bank_1610;
|
2009-10-20 00:25:20 +02:00
|
|
|
bank_size = SZ_2K;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
|
|
|
if (cpu_is_omap7xx()) {
|
2009-03-24 02:07:40 +01:00
|
|
|
gpio_bank_count = 7;
|
2009-09-22 11:02:58 +02:00
|
|
|
gpio_bank = gpio_bank_7xx;
|
2009-10-20 00:25:20 +02:00
|
|
|
bank_size = SZ_2K;
|
2009-03-24 02:07:40 +01:00
|
|
|
}
|
|
|
|
#endif
|
2010-02-12 21:26:47 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
2006-12-07 02:14:08 +01:00
|
|
|
if (cpu_is_omap242x()) {
|
2005-09-07 18:20:26 +02:00
|
|
|
gpio_bank_count = 4;
|
2006-12-07 02:14:08 +01:00
|
|
|
gpio_bank = gpio_bank_242x;
|
|
|
|
}
|
|
|
|
if (cpu_is_omap243x()) {
|
|
|
|
gpio_bank_count = 5;
|
|
|
|
gpio_bank = gpio_bank_243x;
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2007-11-30 01:15:11 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2007-11-30 01:15:11 +01:00
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
gpio_bank_count = OMAP34XX_NR_GPIOS;
|
|
|
|
gpio_bank = gpio_bank_34xx;
|
|
|
|
}
|
2009-05-28 23:16:04 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
gpio_bank_count = OMAP34XX_NR_GPIOS;
|
|
|
|
gpio_bank = gpio_bank_44xx;
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
#endif
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
|
|
int j, gpio_count = 16;
|
|
|
|
|
|
|
|
bank = &gpio_bank[i];
|
|
|
|
spin_lock_init(&bank->lock);
|
2009-10-20 00:25:20 +02:00
|
|
|
|
|
|
|
/* Static mapping, never released */
|
|
|
|
bank->base = ioremap(bank->pbase, bank_size);
|
|
|
|
if (!bank->base) {
|
|
|
|
printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (bank_is_mpuio(bank))
|
2008-09-05 16:49:14 +02:00
|
|
|
__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
|
2008-01-13 00:35:04 +01:00
|
|
|
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
|
|
|
|
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
|
|
|
|
}
|
2008-01-13 00:35:04 +01:00
|
|
|
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
|
|
|
|
__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
|
2005-09-07 18:20:26 +02:00
|
|
|
__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2009-09-22 11:02:58 +02:00
|
|
|
if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
|
|
|
|
__raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
|
|
|
|
__raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2009-09-22 11:02:58 +02:00
|
|
|
gpio_count = 32; /* 7xx has 32-bit GPIOs */
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2008-01-13 00:35:04 +01:00
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2010-02-15 18:27:25 +01:00
|
|
|
if ((bank->method == METHOD_GPIO_24XX) ||
|
|
|
|
(bank->method == METHOD_GPIO_44XX)) {
|
2006-12-07 02:13:52 +01:00
|
|
|
static const u32 non_wakeup_gpios[] = {
|
|
|
|
0xe203ffc0, 0x08700040
|
|
|
|
};
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(0xffffffff, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_IRQSTATUSCLR0);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writew(0x0015, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_SYSCONFIG);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(0x00000000, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_DEBOUNCENABLE);
|
2010-02-15 18:27:25 +01:00
|
|
|
/*
|
|
|
|
* Initialize interface clock ungated,
|
|
|
|
* module enabled
|
|
|
|
*/
|
|
|
|
__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
|
|
|
|
} else {
|
|
|
|
__raw_writel(0x00000000, bank->base +
|
|
|
|
OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
__raw_writel(0xffffffff, bank->base +
|
|
|
|
OMAP24XX_GPIO_IRQSTATUS1);
|
|
|
|
__raw_writew(0x0015, bank->base +
|
|
|
|
OMAP24XX_GPIO_SYSCONFIG);
|
|
|
|
__raw_writel(0x00000000, bank->base +
|
|
|
|
OMAP24XX_GPIO_DEBOUNCE_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize interface clock ungated,
|
|
|
|
* module enabled
|
|
|
|
*/
|
|
|
|
__raw_writel(0, bank->base +
|
|
|
|
OMAP24XX_GPIO_CTRL);
|
|
|
|
}
|
2008-12-22 13:27:12 +01:00
|
|
|
if (cpu_is_omap24xx() &&
|
|
|
|
i < ARRAY_SIZE(non_wakeup_gpios))
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->non_wakeup_gpios = non_wakeup_gpios[i];
|
2005-09-07 18:20:26 +02:00
|
|
|
gpio_count = 32;
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
#endif
|
2009-11-22 19:11:25 +01:00
|
|
|
|
|
|
|
bank->mod_usage = 0;
|
2008-03-03 21:43:23 +01:00
|
|
|
/* REVISIT eventually switch from OMAP-specific gpio structs
|
|
|
|
* over to the generic ones
|
|
|
|
*/
|
2008-12-11 02:35:27 +01:00
|
|
|
bank->chip.request = omap_gpio_request;
|
|
|
|
bank->chip.free = omap_gpio_free;
|
2008-03-03 21:43:23 +01:00
|
|
|
bank->chip.direction_input = gpio_input;
|
|
|
|
bank->chip.get = gpio_get;
|
|
|
|
bank->chip.direction_output = gpio_output;
|
|
|
|
bank->chip.set = gpio_set;
|
2008-12-11 02:35:25 +01:00
|
|
|
bank->chip.to_irq = gpio_2irq;
|
2008-03-03 21:43:23 +01:00
|
|
|
if (bank_is_mpuio(bank)) {
|
|
|
|
bank->chip.label = "mpuio";
|
2008-09-03 11:15:26 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
gpio: sysfs interface
This adds a simple sysfs interface for GPIOs.
/sys/class/gpio
/export ... asks the kernel to export a GPIO to userspace
/unexport ... to return a GPIO to the kernel
/gpioN ... for each exported GPIO #N
/value ... always readable, writes fail for input GPIOs
/direction ... r/w as: in, out (default low); write high, low
/gpiochipN ... for each gpiochip; #N is its first GPIO
/base ... (r/o) same as N
/label ... (r/o) descriptive, not necessarily unique
/ngpio ... (r/o) number of GPIOs; numbered N .. N+(ngpio - 1)
GPIOs claimed by kernel code may be exported by its owner using a new
gpio_export() call, which should be most useful for driver debugging.
Such exports may optionally be done without a "direction" attribute.
Userspace may ask to take over a GPIO by writing to a sysfs control file,
helping to cope with incomplete board support or other "one-off"
requirements that don't merit full kernel support:
echo 23 > /sys/class/gpio/export
... will gpio_request(23, "sysfs") and gpio_export(23);
use /sys/class/gpio/gpio-23/direction to (re)configure it,
when that GPIO can be used as both input and output.
echo 23 > /sys/class/gpio/unexport
... will gpio_free(23), when it was exported as above
The extra D-space footprint is a few hundred bytes, except for the sysfs
resources associated with each exported GPIO. The additional I-space
footprint is about two thirds of the current size of gpiolib (!). Since
no /dev node creation is involved, no "udev" support is needed.
Related changes:
* This adds a device pointer to "struct gpio_chip". When GPIO
providers initialize that, sysfs gpio class devices become children of
that device instead of being "virtual" devices.
* The (few) gpio_chip providers which have such a device node have
been updated.
* Some gpio_chip drivers also needed to update their module "owner"
field ... for which missing kerneldoc was added.
* Some gpio_chips don't support input GPIOs. Those GPIOs are now
flagged appropriately when the chip is registered.
Based on previous patches, and discussion both on and off LKML.
A Documentation/ABI/testing/sysfs-gpio update is ready to submit once this
merges to mainline.
[akpm@linux-foundation.org: a few maintenance build fixes]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Cc: Greg KH <greg@kroah.com>
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 10:46:07 +02:00
|
|
|
bank->chip.dev = &omap_mpuio_device.dev;
|
|
|
|
#endif
|
2008-03-03 21:43:23 +01:00
|
|
|
bank->chip.base = OMAP_MPUIO(0);
|
|
|
|
} else {
|
|
|
|
bank->chip.label = "gpio";
|
|
|
|
bank->chip.base = gpio;
|
|
|
|
gpio += gpio_count;
|
|
|
|
}
|
|
|
|
bank->chip.ngpio = gpio_count;
|
|
|
|
|
|
|
|
gpiochip_add(&bank->chip);
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
for (j = bank->virtual_irq_start;
|
|
|
|
j < bank->virtual_irq_start + gpio_count; j++) {
|
2008-02-26 20:10:50 +01:00
|
|
|
lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
|
2006-12-07 02:14:10 +01:00
|
|
|
set_irq_chip_data(j, bank);
|
2006-12-07 02:13:59 +01:00
|
|
|
if (bank_is_mpuio(bank))
|
2005-07-10 20:58:15 +02:00
|
|
|
set_irq_chip(j, &mpuio_irq_chip);
|
|
|
|
else
|
|
|
|
set_irq_chip(j, &gpio_irq_chip);
|
2006-11-23 12:41:32 +01:00
|
|
|
set_irq_handler(j, handle_simple_irq);
|
2005-07-10 20:58:15 +02:00
|
|
|
set_irq_flags(j, IRQF_VALID);
|
|
|
|
}
|
|
|
|
set_irq_chained_handler(bank->irq, gpio_irq_handler);
|
|
|
|
set_irq_data(bank->irq, bank);
|
2008-12-11 02:35:24 +01:00
|
|
|
|
2009-05-28 23:16:04 +02:00
|
|
|
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
2008-12-11 02:35:24 +01:00
|
|
|
sprintf(clk_name, "gpio%d_dbck", i + 1);
|
|
|
|
bank->dbck = clk_get(NULL, clk_name);
|
|
|
|
if (IS_ERR(bank->dbck))
|
|
|
|
printk(KERN_ERR "Could not get %s\n", clk_name);
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable system clock for GPIO module.
|
|
|
|
* The CAM_CLK_CTRL *is* really the right place. */
|
2005-09-07 18:20:26 +02:00
|
|
|
if (cpu_is_omap16xx())
|
2005-07-10 20:58:15 +02:00
|
|
|
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
|
|
|
|
|
2006-12-07 02:13:48 +01:00
|
|
|
/* Enable autoidle for the OCP interface */
|
|
|
|
if (cpu_is_omap24xx())
|
|
|
|
omap_writel(1 << 0, 0x48019010);
|
2007-11-30 01:15:11 +01:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
omap_writel(1 << 0, 0x48306814);
|
2008-01-13 00:35:04 +01:00
|
|
|
|
2009-10-20 00:25:20 +02:00
|
|
|
omap_gpio_show_rev();
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
2005-09-07 18:20:26 +02:00
|
|
|
static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
void __iomem *wake_status;
|
|
|
|
void __iomem *wake_clear;
|
|
|
|
void __iomem *wake_set;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
|
|
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2008-11-26 23:35:16 +01:00
|
|
|
wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
|
2005-09-07 18:20:26 +02:00
|
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->saved_wakeup = __raw_readl(wake_status);
|
|
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
|
|
__raw_writel(bank->suspend_wakeup, wake_set);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_gpio_resume(struct sys_device *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2008-11-26 23:35:16 +01:00
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
void __iomem *wake_clear;
|
|
|
|
void __iomem *wake_set;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2006-09-25 11:41:45 +02:00
|
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
2005-09-07 18:20:26 +02:00
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
|
|
__raw_writel(bank->saved_wakeup, wake_set);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct sysdev_class omap_gpio_sysclass = {
|
2007-12-20 02:09:39 +01:00
|
|
|
.name = "gpio",
|
2005-09-07 18:20:26 +02:00
|
|
|
.suspend = omap_gpio_suspend,
|
|
|
|
.resume = omap_gpio_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct sys_device omap_gpio_device = {
|
|
|
|
.id = 0,
|
|
|
|
.cls = &omap_gpio_sysclass,
|
|
|
|
};
|
2006-12-07 02:13:52 +01:00
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2006-12-07 02:13:52 +01:00
|
|
|
|
|
|
|
static int workaround_enabled;
|
|
|
|
|
|
|
|
void omap2_gpio_prepare_for_retention(void)
|
|
|
|
{
|
|
|
|
int i, c = 0;
|
2008-12-22 13:27:12 +01:00
|
|
|
int min = 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2008-12-22 13:27:12 +01:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
min = 1;
|
2006-12-07 02:13:52 +01:00
|
|
|
/* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
|
|
|
|
* IRQs will be generated. See OMAP2420 Errata item 1.101. */
|
2008-12-22 13:27:12 +01:00
|
|
|
for (i = min; i < gpio_bank_count; i++) {
|
2006-12-07 02:13:52 +01:00
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
u32 l1, l2;
|
|
|
|
|
|
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
|
|
continue;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_DATAIN);
|
|
|
|
l1 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
l2 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_DATAIN);
|
|
|
|
l1 = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_FALLINGDETECT);
|
|
|
|
l2 = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->saved_fallingdetect = l1;
|
|
|
|
bank->saved_risingdetect = l2;
|
|
|
|
l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
|
l2 &= ~bank->enabled_non_wakeup_gpios;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
__raw_writel(l1, bank->base +
|
|
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(l2, bank->base +
|
|
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
c++;
|
|
|
|
}
|
|
|
|
if (!c) {
|
|
|
|
workaround_enabled = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
workaround_enabled = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
void omap2_gpio_resume_after_retention(void)
|
|
|
|
{
|
|
|
|
int i;
|
2008-12-22 13:27:12 +01:00
|
|
|
int min = 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
|
|
|
if (!workaround_enabled)
|
|
|
|
return;
|
2008-12-22 13:27:12 +01:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
min = 1;
|
|
|
|
for (i = min; i < gpio_bank_count; i++) {
|
2006-12-07 02:13:52 +01:00
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
2009-08-28 19:51:36 +02:00
|
|
|
u32 l, gen, gen0, gen1;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
|
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
|
|
continue;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
__raw_writel(bank->saved_fallingdetect,
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(bank->saved_risingdetect,
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(bank->saved_fallingdetect,
|
2009-07-28 15:27:30 +02:00
|
|
|
bank->base + OMAP4_GPIO_FALLINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(bank->saved_risingdetect,
|
2009-07-28 15:27:30 +02:00
|
|
|
bank->base + OMAP4_GPIO_RISINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
/* Check if any of the non-wakeup interrupt GPIOs have changed
|
|
|
|
* state. If so, generate an IRQ by software. This is
|
|
|
|
* horribly racy, but it's the best we can do to work around
|
|
|
|
* this silicon bug. */
|
|
|
|
l ^= bank->saved_datain;
|
2008-12-22 13:27:12 +01:00
|
|
|
l &= bank->enabled_non_wakeup_gpios;
|
2009-08-28 19:51:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* No need to generate IRQs for the rising edge for gpio IRQs
|
|
|
|
* configured with falling edge only; and vice versa.
|
|
|
|
*/
|
|
|
|
gen0 = l & bank->saved_fallingdetect;
|
|
|
|
gen0 &= bank->saved_datain;
|
|
|
|
|
|
|
|
gen1 = l & bank->saved_risingdetect;
|
|
|
|
gen1 &= ~(bank->saved_datain);
|
|
|
|
|
|
|
|
/* FIXME: Consider GPIO IRQs with level detections properly! */
|
|
|
|
gen = l & (~(bank->saved_fallingdetect) &
|
|
|
|
~(bank->saved_risingdetect));
|
|
|
|
/* Consider all GPIO IRQs needed to be updated */
|
|
|
|
gen |= gen0 | gen1;
|
|
|
|
|
|
|
|
if (gen) {
|
2006-12-07 02:13:52 +01:00
|
|
|
u32 old0, old1;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2010-03-03 17:21:08 +01:00
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
2010-02-15 18:27:25 +01:00
|
|
|
old0 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
old1 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old0 | gen, bank->base +
|
2009-08-28 19:51:36 +02:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old1 | gen, bank->base +
|
2009-08-28 19:51:36 +02:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old0, bank->base +
|
2010-02-15 18:27:25 +01:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old1, bank->base +
|
2010-02-15 18:27:25 +01:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
old0 = __raw_readl(bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
old1 = __raw_readl(bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old0 | l, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old1 | l, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old0, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old1, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2008-09-26 14:17:48 +02:00
|
|
|
/* save the registers of bank 2-6 */
|
|
|
|
void omap_gpio_save_context(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* saving banks from 2-6 only since GPIO1 is in WKUP */
|
|
|
|
for (i = 1; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
gpio_context[i].sysconfig =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
|
|
|
|
gpio_context[i].irqenable1 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
gpio_context[i].irqenable2 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
|
gpio_context[i].wake_en =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
|
gpio_context[i].ctrl =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
gpio_context[i].oe =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
|
|
|
|
gpio_context[i].leveldetect0 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
gpio_context[i].leveldetect1 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
gpio_context[i].risingdetect =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
gpio_context[i].fallingdetect =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
gpio_context[i].dataout =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
|
gpio_context[i].setwkuena =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
|
|
|
|
gpio_context[i].setdataout =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* restore the required registers of bank 2-6 */
|
|
|
|
void omap_gpio_restore_context(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 1; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
__raw_writel(gpio_context[i].sysconfig,
|
|
|
|
bank->base + OMAP24XX_GPIO_SYSCONFIG);
|
|
|
|
__raw_writel(gpio_context[i].irqenable1,
|
|
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
__raw_writel(gpio_context[i].irqenable2,
|
|
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
|
__raw_writel(gpio_context[i].wake_en,
|
|
|
|
bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
|
__raw_writel(gpio_context[i].ctrl,
|
|
|
|
bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
__raw_writel(gpio_context[i].oe,
|
|
|
|
bank->base + OMAP24XX_GPIO_OE);
|
|
|
|
__raw_writel(gpio_context[i].leveldetect0,
|
|
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
__raw_writel(gpio_context[i].leveldetect1,
|
|
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
__raw_writel(gpio_context[i].risingdetect,
|
|
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
__raw_writel(gpio_context[i].fallingdetect,
|
|
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(gpio_context[i].dataout,
|
|
|
|
bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
|
__raw_writel(gpio_context[i].setwkuena,
|
|
|
|
bank->base + OMAP24XX_GPIO_SETWKUENA);
|
|
|
|
__raw_writel(gpio_context[i].setdataout,
|
|
|
|
bank->base + OMAP24XX_GPIO_SETDATAOUT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
/*
|
|
|
|
* This may get called early from board specific init
|
2005-11-10 15:26:50 +01:00
|
|
|
* for boards that have interrupts routed via FPGA.
|
2005-07-10 20:58:15 +02:00
|
|
|
*/
|
2006-12-07 02:13:59 +01:00
|
|
|
int __init omap_gpio_init(void)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
|
|
|
if (!initialized)
|
|
|
|
return _omap_gpio_init();
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
static int __init omap_gpio_sysinit(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (!initialized)
|
|
|
|
ret = _omap_gpio_init();
|
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
mpuio_init();
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
2007-11-30 01:15:11 +01:00
|
|
|
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
|
2005-09-07 18:20:26 +02:00
|
|
|
if (ret == 0) {
|
|
|
|
ret = sysdev_class_register(&omap_gpio_sysclass);
|
|
|
|
if (ret == 0)
|
|
|
|
ret = sysdev_register(&omap_gpio_device);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
arch_initcall(omap_gpio_sysinit);
|
2006-12-07 02:13:53 +01:00
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
|
|
|
|
#include <linux/debugfs.h>
|
|
|
|
#include <linux/seq_file.h>
|
|
|
|
|
|
|
|
static int dbg_gpio_show(struct seq_file *s, void *unused)
|
|
|
|
{
|
|
|
|
unsigned i, j, gpio;
|
|
|
|
|
|
|
|
for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = gpio_bank + i;
|
|
|
|
unsigned bankwidth = 16;
|
|
|
|
u32 mask = 1;
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (bank_is_mpuio(bank))
|
2006-12-07 02:13:53 +01:00
|
|
|
gpio = OMAP_MPUIO(0);
|
2009-09-23 19:56:19 +02:00
|
|
|
else if (cpu_class_is_omap2() || cpu_is_omap7xx())
|
2006-12-07 02:13:53 +01:00
|
|
|
bankwidth = 32;
|
|
|
|
|
|
|
|
for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
|
|
|
|
unsigned irq, value, is_in, irqstat;
|
2008-03-03 21:43:23 +01:00
|
|
|
const char *label;
|
2006-12-07 02:13:53 +01:00
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
label = gpiochip_is_requested(&bank->chip, j);
|
|
|
|
if (!label)
|
2006-12-07 02:13:53 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
irq = bank->virtual_irq_start + j;
|
2008-12-11 02:35:25 +01:00
|
|
|
value = gpio_get_value(gpio);
|
2006-12-07 02:13:53 +01:00
|
|
|
is_in = gpio_is_input(bank, mask);
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (bank_is_mpuio(bank))
|
2008-03-03 21:43:23 +01:00
|
|
|
seq_printf(s, "MPUIO %2d ", j);
|
2006-12-07 02:13:53 +01:00
|
|
|
else
|
2008-03-03 21:43:23 +01:00
|
|
|
seq_printf(s, "GPIO %3d ", gpio);
|
2008-12-11 02:35:24 +01:00
|
|
|
seq_printf(s, "(%-20.20s): %s %s",
|
2008-03-03 21:43:23 +01:00
|
|
|
label,
|
2006-12-07 02:13:53 +01:00
|
|
|
is_in ? "in " : "out",
|
|
|
|
value ? "hi" : "lo");
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
/* FIXME for at least omap2, show pullup/pulldown state */
|
|
|
|
|
2006-12-07 02:13:53 +01:00
|
|
|
irqstat = irq_desc[irq].status;
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
2006-12-07 02:13:53 +01:00
|
|
|
if (is_in && ((bank->suspend_wakeup & mask)
|
|
|
|
|| irqstat & IRQ_TYPE_SENSE_MASK)) {
|
|
|
|
char *trigger = NULL;
|
|
|
|
|
|
|
|
switch (irqstat & IRQ_TYPE_SENSE_MASK) {
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
|
|
trigger = "falling";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
|
|
trigger = "rising";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
|
|
trigger = "bothedge";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
|
|
trigger = "low";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
|
|
trigger = "high";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_NONE:
|
2008-03-03 21:43:23 +01:00
|
|
|
trigger = "(?)";
|
2006-12-07 02:13:53 +01:00
|
|
|
break;
|
|
|
|
}
|
2008-03-03 21:43:23 +01:00
|
|
|
seq_printf(s, ", irq-%d %-8s%s",
|
2006-12-07 02:13:53 +01:00
|
|
|
irq, trigger,
|
|
|
|
(bank->suspend_wakeup & mask)
|
|
|
|
? " wakeup" : "");
|
|
|
|
}
|
2009-01-15 12:09:53 +01:00
|
|
|
#endif
|
2006-12-07 02:13:53 +01:00
|
|
|
seq_printf(s, "\n");
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (bank_is_mpuio(bank)) {
|
2006-12-07 02:13:53 +01:00
|
|
|
seq_printf(s, "\n");
|
|
|
|
gpio = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dbg_gpio_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
2006-12-07 02:13:59 +01:00
|
|
|
return single_open(file, dbg_gpio_show, &inode->i_private);
|
2006-12-07 02:13:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations debug_fops = {
|
|
|
|
.open = dbg_gpio_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init omap_gpio_debuginit(void)
|
|
|
|
{
|
2006-12-07 02:13:59 +01:00
|
|
|
(void) debugfs_create_file("omap_gpio", S_IRUGO,
|
|
|
|
NULL, NULL, &debug_fops);
|
2006-12-07 02:13:53 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
late_initcall(omap_gpio_debuginit);
|
|
|
|
#endif
|