2005-04-17 00:20:36 +02:00
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/*
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* linux/drivers/ide/pci/sl82c105.c
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*
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* SL82C105/Winbond 553 IDE driver
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*
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* Maintainer unknown.
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*
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* Drive tuning added from Rebel.com's kernel sources
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* -- Russell King (15/11/98) linux@arm.linux.org.uk
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*
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* Merge in Russell's HW workarounds, fix various problems
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* with the timing registers setup.
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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2007-05-05 22:03:49 +02:00
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*
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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2005-04-17 00:20:36 +02:00
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(arg) printk arg
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#else
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#define DBG(fmt,...)
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#endif
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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#define CTRL_IDE_IRQB (1 << 30)
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#define CTRL_IDE_IRQA (1 << 28)
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#define CTRL_LEGIRQ (1 << 11)
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#define CTRL_P1F16 (1 << 5)
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#define CTRL_P1EN (1 << 4)
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#define CTRL_P0F16 (1 << 1)
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#define CTRL_P0EN (1 << 0)
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/*
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2007-05-05 22:03:49 +02:00
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* Convert a PIO mode and cycle time to the required on/off times
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* for the interface. This has protection against runaway timings.
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2005-04-17 00:20:36 +02:00
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*/
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2007-07-20 01:11:56 +02:00
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static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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unsigned int cmd_on, cmd_off;
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2007-07-20 01:11:55 +02:00
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u8 iordy = 0;
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2005-04-17 00:20:36 +02:00
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2007-07-20 01:11:56 +02:00
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cmd_on = (ide_pio_timings[pio].active_time + 29) / 30;
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cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
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2005-04-17 00:20:36 +02:00
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if (cmd_on == 0)
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cmd_on = 1;
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if (cmd_off == 0)
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cmd_off = 1;
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2007-07-20 01:11:56 +02:00
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if (pio > 2 || ide_dev_has_iordy(drive->id))
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2007-07-20 01:11:55 +02:00
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iordy = 0x40;
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return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
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2005-04-17 00:20:36 +02:00
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}
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/*
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2007-05-05 22:03:49 +02:00
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* Configure the chipset for PIO mode.
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2005-04-17 00:20:36 +02:00
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*/
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2007-05-05 22:03:49 +02:00
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static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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u16 drv_ctrl;
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2005-04-17 00:20:36 +02:00
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2007-05-05 22:03:49 +02:00
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DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
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2005-04-17 00:20:36 +02:00
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2007-07-20 01:11:58 +02:00
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pio = ide_get_best_pio_mode(drive, pio, 5);
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2005-04-17 00:20:36 +02:00
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2007-07-20 01:11:56 +02:00
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drv_ctrl = get_pio_timings(drive, pio);
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2007-05-16 00:51:44 +02:00
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/*
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* Store the PIO timings so that we can restore them
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* in case DMA will be turned off...
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*/
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drive->drive_data &= 0xffff0000;
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drive->drive_data |= drv_ctrl;
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2005-04-17 00:20:36 +02:00
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2007-05-05 22:03:49 +02:00
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if (!drive->using_dma) {
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2005-04-17 00:20:36 +02:00
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/*
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* If we are actually using MW DMA, then we can not
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* reprogram the interface drive control register.
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*/
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2007-05-05 22:03:49 +02:00
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word (dev, reg, &drv_ctrl);
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2005-04-17 00:20:36 +02:00
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}
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2007-05-05 22:03:49 +02:00
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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2007-07-20 01:11:56 +02:00
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ide_xfer_verbose(pio + XFER_PIO_0),
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ide_pio_cycle_time(drive, pio), drv_ctrl);
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2007-05-05 22:03:49 +02:00
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return pio;
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2005-04-17 00:20:36 +02:00
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}
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2007-05-16 00:51:44 +02:00
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/*
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* Configure the drive and chipset for a new transfer speed.
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*/
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2007-10-11 23:53:59 +02:00
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static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
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2007-05-16 00:51:44 +02:00
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{
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static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
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u16 drv_ctrl;
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DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
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drive->name, ide_xfer_verbose(speed)));
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switch (speed) {
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
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/*
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* Store the DMA timings so that we can actually program
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* them when DMA will be turned on...
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*/
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drive->drive_data &= 0x0000ffff;
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drive->drive_data |= (unsigned long)drv_ctrl << 16;
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/*
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* If we are already using DMA, we just reprogram
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* the drive control register.
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*/
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if (drive->using_dma) {
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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pci_write_config_word(dev, reg, drv_ctrl);
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}
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break;
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case XFER_PIO_5:
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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(void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
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break;
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default:
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return -1;
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}
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return ide_config_drive_speed(drive, speed);
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}
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2005-04-17 00:20:36 +02:00
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/*
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2007-05-05 22:03:49 +02:00
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* Check to see if the drive and chipset are capable of DMA mode.
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2005-04-17 00:20:36 +02:00
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*/
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2007-05-05 22:03:49 +02:00
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static int sl82c105_ide_dma_check(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
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2005-04-17 00:20:36 +02:00
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2007-05-16 00:51:46 +02:00
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if (ide_tune_dma(drive))
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2007-05-05 22:03:49 +02:00
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return 0;
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2005-04-17 00:20:36 +02:00
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2007-02-17 02:40:26 +01:00
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return -1;
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2005-04-17 00:20:36 +02:00
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}
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/*
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* The SL82C105 holds off all IDE interrupts while in DMA mode until
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* all DMA activity is completed. Sometimes this causes problems (eg,
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* when the drive wants to report an error condition).
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*
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* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
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* state machine. We need to kick this to work around various bugs.
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*/
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static inline void sl82c105_reset_host(struct pci_dev *dev)
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{
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u16 val;
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pci_read_config_word(dev, 0x7e, &val);
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pci_write_config_word(dev, 0x7e, val | (1 << 2));
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pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
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}
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/*
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* If we get an IRQ timeout, it might be that the DMA state machine
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* got confused. Fix from Todd Inglett. Details from Winbond.
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*
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* This function is called when the IDE timer expires, the drive
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* indicates that it is READY, and we were waiting for DMA to complete.
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*/
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2007-07-09 23:17:54 +02:00
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static void sl82c105_dma_lost_irq(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
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u8 dma_cmd;
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2005-04-17 00:20:36 +02:00
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2007-05-05 22:03:49 +02:00
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printk("sl82c105: lost IRQ, resetting host\n");
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2005-04-17 00:20:36 +02:00
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/*
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* Check the raw interrupt from the drive.
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*/
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pci_read_config_dword(dev, 0x40, &val);
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if (val & mask)
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printk("sl82c105: drive was requesting IRQ, but host lost it\n");
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/*
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* Was DMA enabled? If so, disable it - we're resetting the
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* host. The IDE layer will be handling the drive for us.
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*/
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2007-05-05 22:03:49 +02:00
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dma_cmd = inb(hwif->dma_command);
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if (dma_cmd & 1) {
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outb(dma_cmd & ~1, hwif->dma_command);
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2005-04-17 00:20:36 +02:00
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printk("sl82c105: DMA was enabled\n");
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}
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sl82c105_reset_host(dev);
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}
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/*
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* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
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* Winbond recommend that the DMA state machine is reset prior to
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* setting the bus master DMA enable bit.
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*
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* The generic IDE core will have disabled the BMEN bit before this
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* function is called.
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*/
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2007-05-05 22:03:49 +02:00
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static void sl82c105_dma_start(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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2005-04-17 00:20:36 +02:00
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sl82c105_reset_host(dev);
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ide_dma_start(drive);
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}
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2007-07-09 23:17:54 +02:00
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static void sl82c105_dma_timeout(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-07-09 23:17:54 +02:00
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DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
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2005-04-17 00:20:36 +02:00
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2007-07-09 23:17:54 +02:00
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sl82c105_reset_host(HWIF(drive)->pci_dev);
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ide_dma_timeout(drive);
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2005-04-17 00:20:36 +02:00
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}
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2007-05-05 22:03:49 +02:00
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static int sl82c105_ide_dma_on(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int rc, reg = 0x44 + drive->dn * 4;
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2005-04-17 00:20:36 +02:00
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DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
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2007-05-05 22:03:49 +02:00
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rc = __ide_dma_on(drive);
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if (rc == 0) {
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2007-05-16 00:51:44 +02:00
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pci_write_config_word(dev, reg, drive->drive_data >> 16);
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2007-05-05 22:03:49 +02:00
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printk(KERN_INFO "%s: DMA enabled\n", drive->name);
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}
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return rc;
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2005-04-17 00:20:36 +02:00
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}
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2007-02-17 02:40:26 +01:00
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static void sl82c105_dma_off_quietly(ide_drive_t *drive)
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2005-04-17 00:20:36 +02:00
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{
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2007-05-05 22:03:49 +02:00
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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2005-04-17 00:20:36 +02:00
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2007-02-17 02:40:26 +01:00
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DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
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2007-05-05 22:03:49 +02:00
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pci_write_config_word(dev, reg, drive->drive_data);
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2007-02-17 02:40:26 +01:00
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ide_dma_off_quietly(drive);
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2005-04-17 00:20:36 +02:00
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}
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/*
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* Ok, that is nasty, but we must make sure the DMA timings
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* won't be used for a PIO access. The solution here is
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* to make sure the 16 bits mode is diabled on the channel
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* when DMA is enabled, thus causing the chip to use PIO0
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* timings for those operations.
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*/
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static void sl82c105_selectproc(ide_drive_t *drive)
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{
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2007-05-05 22:03:49 +02:00
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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2005-04-17 00:20:36 +02:00
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u32 val, old, mask;
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//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
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mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
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2006-12-08 11:40:01 +01:00
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old = val = (u32)pci_get_drvdata(dev);
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2005-04-17 00:20:36 +02:00
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if (drive->using_dma)
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val &= ~mask;
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else
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val |= mask;
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if (old != val) {
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pci_write_config_dword(dev, 0x40, val);
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2006-12-08 11:40:01 +01:00
|
|
|
pci_set_drvdata(dev, (void *)val);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ATA reset will clear the 16 bits mode in the control
|
|
|
|
* register, we need to update our cache
|
|
|
|
*/
|
|
|
|
static void sl82c105_resetproc(ide_drive_t *drive)
|
|
|
|
{
|
2006-12-08 11:40:01 +01:00
|
|
|
struct pci_dev *dev = HWIF(drive)->pci_dev;
|
2005-04-17 00:20:36 +02:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
|
|
|
|
|
|
|
|
pci_read_config_dword(dev, 0x40, &val);
|
2006-12-08 11:40:01 +01:00
|
|
|
pci_set_drvdata(dev, (void *)val);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We only deal with PIO mode here - DMA mode 'using_dma' is not
|
|
|
|
* initialised at the point that this function is called.
|
|
|
|
*/
|
2007-05-05 22:03:49 +02:00
|
|
|
static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2007-05-05 22:03:49 +02:00
|
|
|
DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-05-05 22:03:49 +02:00
|
|
|
pio = sl82c105_tune_pio(drive, pio);
|
|
|
|
(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Return the revision of the Winbond bridge
|
|
|
|
* which this function is part of.
|
|
|
|
*/
|
|
|
|
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct pci_dev *bridge;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The bridge should be part of the same device, but function 0.
|
|
|
|
*/
|
2007-05-16 00:51:46 +02:00
|
|
|
bridge = pci_get_bus_and_slot(dev->bus->number,
|
2005-04-17 00:20:36 +02:00
|
|
|
PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
|
|
|
|
if (!bridge)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure it is a Winbond 553 and is an ISA bridge.
|
|
|
|
*/
|
|
|
|
if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
|
|
|
|
bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
|
2007-05-16 00:51:46 +02:00
|
|
|
bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
|
|
|
|
pci_dev_put(bridge);
|
2005-04-17 00:20:36 +02:00
|
|
|
return -1;
|
2007-05-16 00:51:46 +02:00
|
|
|
}
|
2005-04-17 00:20:36 +02:00
|
|
|
/*
|
|
|
|
* We need to find function 0's revision, not function 1
|
|
|
|
*/
|
2007-05-16 00:51:46 +02:00
|
|
|
pci_dev_put(bridge);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
2007-06-09 00:46:36 +02:00
|
|
|
return bridge->revision;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable the PCI device
|
|
|
|
*
|
|
|
|
* --BenH: It's arch fixup code that should enable channels that
|
|
|
|
* have not been enabled by firmware. I decided we can still enable
|
|
|
|
* channel 0 here at least, but channel 1 has to be enabled by
|
|
|
|
* firmware or arch code. We still set both to 16 bits mode.
|
|
|
|
*/
|
2005-07-03 16:36:56 +02:00
|
|
|
static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
DBG(("init_chipset_sl82c105()\n"));
|
|
|
|
|
|
|
|
pci_read_config_dword(dev, 0x40, &val);
|
|
|
|
val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
|
|
|
|
pci_write_config_dword(dev, 0x40, val);
|
2006-12-08 11:40:01 +01:00
|
|
|
pci_set_drvdata(dev, (void *)val);
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
return dev->irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2007-05-05 22:03:49 +02:00
|
|
|
* Initialise IDE channel
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
2005-07-03 16:36:56 +02:00
|
|
|
static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
2005-11-12 17:57:29 +01:00
|
|
|
unsigned int rev;
|
2006-12-08 11:40:01 +01:00
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
|
|
|
|
|
2007-05-05 22:03:49 +02:00
|
|
|
hwif->tuneproc = &sl82c105_tune_drive;
|
2007-05-16 00:51:44 +02:00
|
|
|
hwif->speedproc = &sl82c105_tune_chipset;
|
2007-05-05 22:03:49 +02:00
|
|
|
hwif->selectproc = &sl82c105_selectproc;
|
|
|
|
hwif->resetproc = &sl82c105_resetproc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We support 32-bit I/O on this interface, and
|
|
|
|
* it doesn't have problems with interrupts.
|
|
|
|
*/
|
|
|
|
hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
|
|
|
|
hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
|
2006-12-08 11:40:01 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We always autotune PIO, this is done before DMA is checked,
|
|
|
|
* so there's no risk of accidentally disabling DMA
|
|
|
|
*/
|
2007-05-05 22:03:49 +02:00
|
|
|
hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
if (!hwif->dma_base)
|
|
|
|
return;
|
|
|
|
|
2005-11-12 17:57:29 +01:00
|
|
|
rev = sl82c105_bridge_revision(hwif->pci_dev);
|
|
|
|
if (rev <= 5) {
|
|
|
|
/*
|
|
|
|
* Never ever EVER under any circumstances enable
|
|
|
|
* DMA when the bridge is this old.
|
|
|
|
*/
|
2007-05-05 22:03:49 +02:00
|
|
|
printk(" %s: Winbond W83C553 bridge revision %d, "
|
|
|
|
"BM-DMA disabled\n", hwif->name, rev);
|
|
|
|
return;
|
2005-11-12 17:57:29 +01:00
|
|
|
}
|
2007-05-05 22:03:49 +02:00
|
|
|
|
|
|
|
hwif->atapi_dma = 1;
|
2007-05-16 00:51:44 +02:00
|
|
|
hwif->mwdma_mask = 0x07;
|
2007-05-05 22:03:49 +02:00
|
|
|
|
|
|
|
hwif->ide_dma_check = &sl82c105_ide_dma_check;
|
|
|
|
hwif->ide_dma_on = &sl82c105_ide_dma_on;
|
|
|
|
hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
|
2007-07-09 23:17:54 +02:00
|
|
|
hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
|
2007-05-05 22:03:49 +02:00
|
|
|
hwif->dma_start = &sl82c105_dma_start;
|
2007-07-09 23:17:54 +02:00
|
|
|
hwif->dma_timeout = &sl82c105_dma_timeout;
|
2007-05-05 22:03:49 +02:00
|
|
|
|
|
|
|
if (!noautodma)
|
|
|
|
hwif->autodma = 1;
|
|
|
|
hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
|
|
|
|
|
|
|
|
if (hwif->mate)
|
|
|
|
hwif->serialized = hwif->mate->serialized = 1;
|
2005-04-17 00:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static ide_pci_device_t sl82c105_chipset __devinitdata = {
|
|
|
|
.name = "W82C105",
|
|
|
|
.init_chipset = init_chipset_sl82c105,
|
|
|
|
.init_hwif = init_hwif_sl82c105,
|
|
|
|
.autodma = NOAUTODMA,
|
|
|
|
.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
|
|
|
|
.bootable = ON_BOARD,
|
2007-07-20 01:11:59 +02:00
|
|
|
.pio_mask = ATA_PIO5,
|
2005-04-17 00:20:36 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
|
|
|
return ide_setup_pci_device(dev, &sl82c105_chipset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_device_id sl82c105_pci_tbl[] = {
|
2006-06-28 13:27:02 +02:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
|
2005-04-17 00:20:36 +02:00
|
|
|
{ 0, },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
|
|
|
|
|
|
|
|
static struct pci_driver driver = {
|
|
|
|
.name = "W82C105_IDE",
|
|
|
|
.id_table = sl82c105_pci_tbl,
|
|
|
|
.probe = sl82c105_init_one,
|
|
|
|
};
|
|
|
|
|
2007-01-27 13:46:56 +01:00
|
|
|
static int __init sl82c105_ide_init(void)
|
2005-04-17 00:20:36 +02:00
|
|
|
{
|
|
|
|
return ide_pci_register_driver(&driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(sl82c105_ide_init);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
|
|
|
|
MODULE_LICENSE("GPL");
|