2005-07-28 03:36:22 +02:00
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/*
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* sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
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*
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* Copyright 2005 Tejun Heo
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*
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* Based on preview driver from Silicon Image.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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2005-10-30 20:39:11 +01:00
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#include <linux/device.h>
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2005-07-28 03:36:22 +02:00
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#include <scsi/scsi_host.h>
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2005-11-07 06:59:37 +01:00
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#include <scsi/scsi_cmnd.h>
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2005-07-28 03:36:22 +02:00
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#include <linux/libata.h>
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#define DRV_NAME "sata_sil24"
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2007-09-23 06:19:54 +02:00
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#define DRV_VERSION "1.1"
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2005-07-28 03:36:22 +02:00
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/*
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* Port request block (PRB) 32 bytes
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*/
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struct sil24_prb {
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2006-06-06 05:31:14 +02:00
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__le16 ctrl;
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__le16 prot;
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__le32 rx_cnt;
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2005-07-28 03:36:22 +02:00
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u8 fis[6 * 4];
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};
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/*
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* Scatter gather entry (SGE) 16 bytes
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*/
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struct sil24_sge {
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2006-06-06 05:31:14 +02:00
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__le64 addr;
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__le32 cnt;
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__le32 flags;
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2005-07-28 03:36:22 +02:00
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};
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/*
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* Port multiplier
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*/
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struct sil24_port_multiplier {
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2006-06-06 05:31:14 +02:00
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__le32 diag;
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__le32 sactive;
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2005-07-28 03:36:22 +02:00
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};
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enum {
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2007-02-01 07:06:36 +01:00
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SIL24_HOST_BAR = 0,
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SIL24_PORT_BAR = 2,
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2007-11-22 10:46:57 +01:00
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/* sil24 fetches in chunks of 64bytes. The first block
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* contains the PRB and two SGEs. From the second block, it's
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* consisted of four SGEs and called SGT. Calculate the
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* number of SGTs that fit into one page.
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*/
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SIL24_PRB_SZ = sizeof(struct sil24_prb)
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+ 2 * sizeof(struct sil24_sge),
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SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
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/ (4 * sizeof(struct sil24_sge)),
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/* This will give us one unused SGEs for ATA. This extra SGE
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* will be used to store CDB for ATAPI devices.
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*/
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SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
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2005-07-28 03:36:22 +02:00
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/*
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* Global controller registers (128 bytes @ BAR0)
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*/
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/* 32 bit regs */
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HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
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HOST_CTRL = 0x40,
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HOST_IRQ_STAT = 0x44,
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HOST_PHY_CFG = 0x48,
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HOST_BIST_CTRL = 0x50,
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HOST_BIST_PTRN = 0x54,
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HOST_BIST_STAT = 0x58,
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HOST_MEM_BIST_STAT = 0x5c,
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HOST_FLASH_CMD = 0x70,
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/* 8 bit regs */
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HOST_FLASH_DATA = 0x74,
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HOST_TRANSITION_DETECT = 0x75,
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HOST_GPIO_CTRL = 0x76,
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HOST_I2C_ADDR = 0x78, /* 32 bit */
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HOST_I2C_DATA = 0x7c,
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HOST_I2C_XFER_CNT = 0x7e,
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HOST_I2C_CTRL = 0x7f,
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/* HOST_SLOT_STAT bits */
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HOST_SSTAT_ATTN = (1 << 31),
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2006-04-11 15:32:18 +02:00
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/* HOST_CTRL bits */
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HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
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HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
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HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
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HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
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HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
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2006-07-03 09:07:27 +02:00
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HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
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2006-04-11 15:32:18 +02:00
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2005-07-28 03:36:22 +02:00
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/*
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* Port registers
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* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
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*/
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PORT_REGS_SIZE = 0x2000,
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2006-05-31 11:27:57 +02:00
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2006-10-16 01:47:18 +02:00
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PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
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2006-05-31 11:27:57 +02:00
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PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
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2005-07-28 03:36:22 +02:00
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2006-10-16 01:47:18 +02:00
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PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
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2006-10-16 01:47:18 +02:00
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PORT_PMP_STATUS = 0x0000, /* port device status offset */
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PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
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PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
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2005-07-28 03:36:22 +02:00
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/* 32 bit regs */
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2005-08-17 06:09:18 +02:00
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PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
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PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
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PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
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PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
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PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
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2005-07-28 03:36:22 +02:00
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PORT_ACTIVATE_UPPER_ADDR= 0x101c,
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2005-08-17 06:09:18 +02:00
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PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
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PORT_CMD_ERR = 0x1024, /* command error number */
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2005-07-28 03:36:22 +02:00
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PORT_FIS_CFG = 0x1028,
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PORT_FIFO_THRES = 0x102c,
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/* 16 bit regs */
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PORT_DECODE_ERR_CNT = 0x1040,
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PORT_DECODE_ERR_THRESH = 0x1042,
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PORT_CRC_ERR_CNT = 0x1044,
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PORT_CRC_ERR_THRESH = 0x1046,
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PORT_HSHK_ERR_CNT = 0x1048,
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PORT_HSHK_ERR_THRESH = 0x104a,
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/* 32 bit regs */
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PORT_PHY_CFG = 0x1050,
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PORT_SLOT_STAT = 0x1800,
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PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
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2006-10-16 01:47:18 +02:00
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PORT_CONTEXT = 0x1e04,
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2005-07-28 03:36:22 +02:00
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PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
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PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
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PORT_SCONTROL = 0x1f00,
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PORT_SSTATUS = 0x1f04,
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PORT_SERROR = 0x1f08,
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PORT_SACTIVE = 0x1f0c,
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/* PORT_CTRL_STAT bits */
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PORT_CS_PORT_RST = (1 << 0), /* port reset */
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PORT_CS_DEV_RST = (1 << 1), /* device reset */
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PORT_CS_INIT = (1 << 2), /* port initialize */
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PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
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2005-11-16 08:56:49 +01:00
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PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
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2006-10-16 01:47:18 +02:00
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PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
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2005-08-17 06:09:13 +02:00
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PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
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2006-10-16 01:47:18 +02:00
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PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
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2005-08-17 06:09:13 +02:00
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PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
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2005-07-28 03:36:22 +02:00
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/* PORT_IRQ_STAT/ENABLE_SET/CLR */
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/* bits[11:0] are masked */
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PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
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PORT_IRQ_ERROR = (1 << 1), /* command execution error */
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PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
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PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
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PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
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PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
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2006-04-11 15:32:18 +02:00
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PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
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PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
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PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
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PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
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PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
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2006-04-11 15:32:18 +02:00
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PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
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2005-07-28 03:36:22 +02:00
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2006-05-15 13:58:32 +02:00
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DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
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2006-05-31 11:28:20 +02:00
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PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
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2007-09-23 06:14:11 +02:00
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PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
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2006-05-15 13:58:32 +02:00
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2005-07-28 03:36:22 +02:00
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/* bits[27:16] are unmasked (raw) */
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PORT_IRQ_RAW_SHIFT = 16,
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PORT_IRQ_MASKED_MASK = 0x7ff,
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PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
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/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
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PORT_IRQ_STEER_SHIFT = 30,
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PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
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/* PORT_CMD_ERR constants */
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PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
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PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
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PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
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PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
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PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
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PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
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PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
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PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
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PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
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PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
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PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
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PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
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PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
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PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
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PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
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PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
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PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
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PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
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PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
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2006-04-11 15:32:18 +02:00
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PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
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2005-07-28 03:36:22 +02:00
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PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
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2005-08-17 06:09:18 +02:00
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PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
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2005-07-28 03:36:22 +02:00
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2005-11-16 08:56:49 +01:00
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/* bits of PRB control field */
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PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
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PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
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PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
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PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
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PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
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/* PRB protocol field */
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PRB_PROT_PACKET = (1 << 0),
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PRB_PROT_TCQ = (1 << 1),
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PRB_PROT_NCQ = (1 << 2),
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PRB_PROT_READ = (1 << 3),
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PRB_PROT_WRITE = (1 << 4),
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PRB_PROT_TRANSPARENT = (1 << 5),
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2005-07-28 03:36:22 +02:00
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/*
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* Other constants
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*/
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SGE_TRM = (1 << 31), /* Last SGE in chain */
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2005-11-16 08:56:49 +01:00
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SGE_LNK = (1 << 30), /* linked list
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Points to SGT, not SGE */
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SGE_DRD = (1 << 29), /* discard data read (/dev/null)
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data address ignored */
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2005-07-28 03:36:22 +02:00
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2006-05-15 14:03:56 +02:00
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SIL24_MAX_CMDS = 31,
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2005-07-28 03:36:22 +02:00
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/* board id */
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BID_SIL3124 = 0,
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BID_SIL3132 = 1,
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2005-10-09 15:35:46 +02:00
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BID_SIL3131 = 2,
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2005-07-28 03:36:22 +02:00
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2006-04-11 15:32:18 +02:00
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/* host flags */
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SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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2006-05-15 14:03:56 +02:00
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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2007-09-23 06:14:11 +02:00
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ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
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2007-09-23 06:19:54 +02:00
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ATA_FLAG_AN | ATA_FLAG_PMP,
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2006-04-11 15:32:19 +02:00
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SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
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2006-04-11 15:32:18 +02:00
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2005-07-28 03:36:22 +02:00
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IRQ_STAT_4PORTS = 0xf,
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};
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2005-11-18 06:16:45 +01:00
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struct sil24_ata_block {
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2005-07-28 03:36:22 +02:00
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struct sil24_prb prb;
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2007-11-22 10:46:57 +01:00
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struct sil24_sge sge[SIL24_MAX_SGE];
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2005-07-28 03:36:22 +02:00
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};
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2005-11-18 06:16:45 +01:00
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struct sil24_atapi_block {
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struct sil24_prb prb;
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u8 cdb[16];
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2007-11-22 10:46:57 +01:00
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struct sil24_sge sge[SIL24_MAX_SGE];
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2005-11-18 06:16:45 +01:00
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};
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union sil24_cmd_block {
|
|
|
|
struct sil24_ata_block ata;
|
|
|
|
struct sil24_atapi_block atapi;
|
|
|
|
};
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
static struct sil24_cerr_info {
|
|
|
|
unsigned int err_mask, action;
|
|
|
|
const char *desc;
|
|
|
|
} sil24_cerr_db[] = {
|
2007-10-26 09:12:41 +02:00
|
|
|
[0] = { AC_ERR_DEV, 0,
|
2006-05-15 13:58:32 +02:00
|
|
|
"device error" },
|
2007-10-26 09:12:41 +02:00
|
|
|
[PORT_CERR_DEV] = { AC_ERR_DEV, 0,
|
2006-05-15 13:58:32 +02:00
|
|
|
"device error via D2H FIS" },
|
2007-10-26 09:12:41 +02:00
|
|
|
[PORT_CERR_SDB] = { AC_ERR_DEV, 0,
|
2006-05-15 13:58:32 +02:00
|
|
|
"device error via SDB FIS" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"error in data FIS" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"failed to transmit command FIS" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"protocol mismatch" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"data directon mismatch" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"ran out of SGEs while writing" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"ran out of SGEs while reading" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"invalid data directon for ATAPI CDB" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
|
2008-01-13 05:49:22 +01:00
|
|
|
"SGT not on qword boundary" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI target abort while fetching SGT" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI master abort while fetching SGT" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI parity error while fetching SGT" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PRB not on qword boundary" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI target abort while fetching PRB" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI master abort while fetching PRB" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI parity error while fetching PRB" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"undefined error while transferring data" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI target abort while transferring data" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI master abort while transferring data" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"PCI parity error while transferring data" },
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
[PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
|
2006-05-15 13:58:32 +02:00
|
|
|
"FIS received while sending service FIS" },
|
|
|
|
};
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
/*
|
|
|
|
* ap->private_data
|
|
|
|
*
|
|
|
|
* The preview driver always returned 0 for status. We emulate it
|
|
|
|
* here from the previous interrupt.
|
|
|
|
*/
|
|
|
|
struct sil24_port_priv {
|
2005-11-18 06:16:45 +01:00
|
|
|
union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
|
2005-07-28 03:36:22 +02:00
|
|
|
dma_addr_t cmd_block_dma; /* DMA base addr for them */
|
2005-10-06 04:43:39 +02:00
|
|
|
struct ata_taskfile tf; /* Cached taskfile registers */
|
2007-09-23 06:19:54 +02:00
|
|
|
int do_port_rst;
|
2005-07-28 03:36:22 +02:00
|
|
|
};
|
|
|
|
|
2007-03-02 01:56:15 +01:00
|
|
|
static void sil24_dev_config(struct ata_device *dev);
|
2005-07-28 03:36:22 +02:00
|
|
|
static u8 sil24_check_status(struct ata_port *ap);
|
2007-07-16 07:29:40 +02:00
|
|
|
static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
|
|
|
|
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
|
2005-10-06 18:43:19 +02:00
|
|
|
static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
|
2007-09-23 06:19:54 +02:00
|
|
|
static int sil24_qc_defer(struct ata_queued_cmd *qc);
|
2005-07-28 03:36:22 +02:00
|
|
|
static void sil24_qc_prep(struct ata_queued_cmd *qc);
|
2006-01-23 05:09:36 +01:00
|
|
|
static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
|
2005-07-28 03:36:22 +02:00
|
|
|
static void sil24_irq_clear(struct ata_port *ap);
|
2007-09-23 06:19:54 +02:00
|
|
|
static void sil24_pmp_attach(struct ata_port *ap);
|
|
|
|
static void sil24_pmp_detach(struct ata_port *ap);
|
2006-05-15 13:58:32 +02:00
|
|
|
static void sil24_freeze(struct ata_port *ap);
|
|
|
|
static void sil24_thaw(struct ata_port *ap);
|
|
|
|
static void sil24_error_handler(struct ata_port *ap);
|
|
|
|
static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
|
2005-07-28 03:36:22 +02:00
|
|
|
static int sil24_port_start(struct ata_port *ap);
|
|
|
|
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
2006-08-15 07:49:30 +02:00
|
|
|
#ifdef CONFIG_PM
|
2006-07-03 09:07:27 +02:00
|
|
|
static int sil24_pci_device_resume(struct pci_dev *pdev);
|
2007-09-23 06:19:54 +02:00
|
|
|
static int sil24_port_resume(struct ata_port *ap);
|
2006-08-15 07:49:30 +02:00
|
|
|
#endif
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2005-11-10 17:04:11 +01:00
|
|
|
static const struct pci_device_id sil24_pci_tbl[] = {
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
|
|
|
|
{ PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
|
2007-03-13 05:48:00 +01:00
|
|
|
{ PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
|
2006-09-28 04:20:11 +02:00
|
|
|
{ PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
|
|
|
|
{ PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
|
|
|
|
|
2005-10-09 15:31:33 +02:00
|
|
|
{ } /* terminate list */
|
2005-07-28 03:36:22 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver sil24_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = sil24_pci_tbl,
|
|
|
|
.probe = sil24_init_one,
|
2007-01-20 08:00:28 +01:00
|
|
|
.remove = ata_pci_remove_one,
|
2006-08-15 07:49:30 +02:00
|
|
|
#ifdef CONFIG_PM
|
2006-07-03 09:07:27 +02:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = sil24_pci_device_resume,
|
2006-08-15 07:49:30 +02:00
|
|
|
#endif
|
2005-07-28 03:36:22 +02:00
|
|
|
};
|
|
|
|
|
2005-11-07 06:59:37 +01:00
|
|
|
static struct scsi_host_template sil24_sht = {
|
2005-07-28 03:36:22 +02:00
|
|
|
.module = THIS_MODULE,
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.ioctl = ata_scsi_ioctl,
|
|
|
|
.queuecommand = ata_scsi_queuecmd,
|
2006-05-15 14:03:56 +02:00
|
|
|
.change_queue_depth = ata_scsi_change_queue_depth,
|
|
|
|
.can_queue = SIL24_MAX_CMDS,
|
2005-07-28 03:36:22 +02:00
|
|
|
.this_id = ATA_SHT_THIS_ID,
|
2007-11-22 10:46:57 +01:00
|
|
|
.sg_tablesize = SIL24_MAX_SGE,
|
2005-07-28 03:36:22 +02:00
|
|
|
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
|
|
|
.emulated = ATA_SHT_EMULATED,
|
|
|
|
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
|
|
|
.proc_name = DRV_NAME,
|
|
|
|
.dma_boundary = ATA_DMA_BOUNDARY,
|
|
|
|
.slave_configure = ata_scsi_slave_config,
|
2006-05-31 11:28:09 +02:00
|
|
|
.slave_destroy = ata_scsi_slave_destroy,
|
2005-07-28 03:36:22 +02:00
|
|
|
.bios_param = ata_std_bios_param,
|
|
|
|
};
|
|
|
|
|
2005-10-22 20:27:05 +02:00
|
|
|
static const struct ata_port_operations sil24_ops = {
|
2005-11-18 06:16:45 +01:00
|
|
|
.dev_config = sil24_dev_config,
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
.check_status = sil24_check_status,
|
|
|
|
.check_altstatus = sil24_check_status,
|
|
|
|
.dev_select = ata_noop_dev_select,
|
|
|
|
|
2005-10-06 18:43:19 +02:00
|
|
|
.tf_read = sil24_tf_read,
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
.qc_defer = sil24_qc_defer,
|
2005-07-28 03:36:22 +02:00
|
|
|
.qc_prep = sil24_qc_prep,
|
|
|
|
.qc_issue = sil24_qc_issue,
|
|
|
|
|
|
|
|
.irq_clear = sil24_irq_clear,
|
|
|
|
|
|
|
|
.scr_read = sil24_scr_read,
|
|
|
|
.scr_write = sil24_scr_write,
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
.pmp_attach = sil24_pmp_attach,
|
|
|
|
.pmp_detach = sil24_pmp_detach,
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
.freeze = sil24_freeze,
|
|
|
|
.thaw = sil24_thaw,
|
|
|
|
.error_handler = sil24_error_handler,
|
|
|
|
.post_internal_cmd = sil24_post_internal_cmd,
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
.port_start = sil24_port_start,
|
2007-09-23 06:19:54 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
.port_resume = sil24_port_resume,
|
|
|
|
#endif
|
2005-07-28 03:36:22 +02:00
|
|
|
};
|
|
|
|
|
2005-10-09 15:35:46 +02:00
|
|
|
/*
|
2006-08-24 09:19:22 +02:00
|
|
|
* Use bits 30-31 of port_flags to encode available port numbers.
|
2005-10-09 15:35:46 +02:00
|
|
|
* Current maxium is 4.
|
|
|
|
*/
|
|
|
|
#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
|
|
|
|
#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
static const struct ata_port_info sil24_port_info[] = {
|
2005-07-28 03:36:22 +02:00
|
|
|
/* sil_3124 */
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
|
2006-04-11 15:32:19 +02:00
|
|
|
SIL24_FLAG_PCIX_IRQ_WOC,
|
2005-07-28 03:36:22 +02:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-09 18:16:50 +02:00
|
|
|
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
2005-07-28 03:36:22 +02:00
|
|
|
.port_ops = &sil24_ops,
|
|
|
|
},
|
2006-03-24 15:56:57 +01:00
|
|
|
/* sil_3132 */
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
|
2005-10-09 15:35:46 +02:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-09 18:16:50 +02:00
|
|
|
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
2005-10-09 15:35:46 +02:00
|
|
|
.port_ops = &sil24_ops,
|
|
|
|
},
|
|
|
|
/* sil_3131/sil_3531 */
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
.flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
|
2005-07-28 03:36:22 +02:00
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-09 18:16:50 +02:00
|
|
|
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
2005-07-28 03:36:22 +02:00
|
|
|
.port_ops = &sil24_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
static int sil24_tag(int tag)
|
|
|
|
{
|
|
|
|
if (unlikely(ata_tag_internal(tag)))
|
|
|
|
return 0;
|
|
|
|
return tag;
|
|
|
|
}
|
|
|
|
|
2007-03-02 01:56:15 +01:00
|
|
|
static void sil24_dev_config(struct ata_device *dev)
|
2005-11-18 06:16:45 +01:00
|
|
|
{
|
2007-08-06 11:36:22 +02:00
|
|
|
void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
|
2005-11-18 06:16:45 +01:00
|
|
|
|
2006-02-12 15:32:58 +01:00
|
|
|
if (dev->cdb_len == 16)
|
2005-11-18 06:16:45 +01:00
|
|
|
writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
|
|
|
|
else
|
|
|
|
writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
|
|
|
|
}
|
|
|
|
|
2007-07-16 07:29:39 +02:00
|
|
|
static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
|
2005-10-06 04:43:39 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2007-07-16 07:29:39 +02:00
|
|
|
struct sil24_prb __iomem *prb;
|
2005-10-29 07:38:44 +02:00
|
|
|
u8 fis[6 * 4];
|
2005-10-06 04:43:39 +02:00
|
|
|
|
2007-07-16 07:29:39 +02:00
|
|
|
prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
|
|
|
|
memcpy_fromio(fis, prb->fis, sizeof(fis));
|
|
|
|
ata_tf_from_fis(fis, tf);
|
2005-10-06 04:43:39 +02:00
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static u8 sil24_check_status(struct ata_port *ap)
|
|
|
|
{
|
2005-10-06 04:43:39 +02:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
|
|
|
return pp->tf.command;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sil24_scr_map[] = {
|
|
|
|
[SCR_CONTROL] = 0,
|
|
|
|
[SCR_STATUS] = 1,
|
|
|
|
[SCR_ERROR] = 2,
|
|
|
|
[SCR_ACTIVE] = 3,
|
|
|
|
};
|
|
|
|
|
2007-07-16 07:29:40 +02:00
|
|
|
static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *scr_addr = ap->ioaddr.scr_addr;
|
2007-07-16 07:29:40 +02:00
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
|
2005-10-29 07:38:44 +02:00
|
|
|
void __iomem *addr;
|
2005-07-28 03:36:22 +02:00
|
|
|
addr = scr_addr + sil24_scr_map[sc_reg] * 4;
|
2007-07-16 07:29:40 +02:00
|
|
|
*val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
|
|
|
|
return 0;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
2007-07-16 07:29:40 +02:00
|
|
|
return -EINVAL;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2007-07-16 07:29:40 +02:00
|
|
|
static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *scr_addr = ap->ioaddr.scr_addr;
|
2007-07-16 07:29:40 +02:00
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
|
2005-10-29 07:38:44 +02:00
|
|
|
void __iomem *addr;
|
2005-07-28 03:36:22 +02:00
|
|
|
addr = scr_addr + sil24_scr_map[sc_reg] * 4;
|
|
|
|
writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
|
2007-07-16 07:29:40 +02:00
|
|
|
return 0;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
2007-07-16 07:29:40 +02:00
|
|
|
return -EINVAL;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2005-10-06 18:43:19 +02:00
|
|
|
static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|
|
|
{
|
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
|
|
|
*tf = pp->tf;
|
|
|
|
}
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
static void sil24_config_port(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
|
|
|
|
|
|
|
/* configure IRQ WoC */
|
|
|
|
if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
|
|
|
|
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
|
|
|
|
else
|
|
|
|
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
|
|
|
|
|
|
|
|
/* zero error counters. */
|
|
|
|
writel(0x8000, port + PORT_DECODE_ERR_THRESH);
|
|
|
|
writel(0x8000, port + PORT_CRC_ERR_THRESH);
|
|
|
|
writel(0x8000, port + PORT_HSHK_ERR_THRESH);
|
|
|
|
writel(0x0000, port + PORT_DECODE_ERR_CNT);
|
|
|
|
writel(0x0000, port + PORT_CRC_ERR_CNT);
|
|
|
|
writel(0x0000, port + PORT_HSHK_ERR_CNT);
|
|
|
|
|
|
|
|
/* always use 64bit activation */
|
|
|
|
writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
|
|
|
|
|
|
|
|
/* clear port multiplier enable and resume bits */
|
|
|
|
writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
|
|
|
|
}
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
static void sil24_config_pmp(struct ata_port *ap, int attached)
|
|
|
|
{
|
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
|
|
|
|
|
|
|
if (attached)
|
|
|
|
writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
|
|
|
|
else
|
|
|
|
writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sil24_clear_pmp(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
|
|
|
|
|
|
|
|
for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
|
|
|
|
void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
|
|
|
|
|
|
|
|
writel(0, pmp_base + PORT_PMP_STATUS);
|
|
|
|
writel(0, pmp_base + PORT_PMP_QACTIVE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
static int sil24_init_port(struct ata_port *ap)
|
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2007-09-23 06:19:54 +02:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
2006-04-11 15:32:19 +02:00
|
|
|
u32 tmp;
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
/* clear PMP error status */
|
|
|
|
if (ap->nr_pmp_links)
|
|
|
|
sil24_clear_pmp(ap);
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
|
|
|
|
ata_wait_register(port + PORT_CTRL_STAT,
|
|
|
|
PORT_CS_INIT, PORT_CS_INIT, 10, 100);
|
|
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
|
|
|
PORT_CS_RDY, 0, 10, 100);
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
|
|
|
|
pp->do_port_rst = 1;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
ap->link.eh_context.i.action |= ATA_EH_RESET;
|
2006-04-11 15:32:19 +02:00
|
|
|
return -EIO;
|
2007-09-23 06:19:54 +02:00
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-16 07:29:39 +02:00
|
|
|
static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
|
|
|
|
const struct ata_taskfile *tf,
|
|
|
|
int is_cmd, u32 ctrl,
|
|
|
|
unsigned long timeout_msec)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2005-11-18 06:14:01 +01:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
2005-11-18 06:16:45 +01:00
|
|
|
struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
|
2005-11-18 06:14:01 +01:00
|
|
|
dma_addr_t paddr = pp->cmd_block_dma;
|
2007-07-16 07:29:39 +02:00
|
|
|
u32 irq_enabled, irq_mask, irq_stat;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
prb->ctrl = cpu_to_le16(ctrl);
|
|
|
|
ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
|
|
|
|
|
|
|
|
/* temporarily plug completion and error interrupts */
|
|
|
|
irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
|
|
|
|
writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
|
|
|
|
|
|
|
|
writel((u32)paddr, port + PORT_CMD_ACTIVATE);
|
|
|
|
writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
|
|
|
|
|
|
|
|
irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
|
|
|
|
irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
|
|
|
|
10, timeout_msec);
|
|
|
|
|
|
|
|
writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
|
|
|
|
irq_stat >>= PORT_IRQ_RAW_SHIFT;
|
|
|
|
|
|
|
|
if (irq_stat & PORT_IRQ_COMPLETE)
|
|
|
|
rc = 0;
|
|
|
|
else {
|
|
|
|
/* force port into known state */
|
|
|
|
sil24_init_port(ap);
|
|
|
|
|
|
|
|
if (irq_stat & PORT_IRQ_ERROR)
|
|
|
|
rc = -EIO;
|
|
|
|
else
|
|
|
|
rc = -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* restore IRQ enabled */
|
|
|
|
writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
|
2007-07-16 07:29:39 +02:00
|
|
|
int pmp, unsigned long deadline)
|
2007-07-16 07:29:39 +02:00
|
|
|
{
|
2007-08-06 11:36:23 +02:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-07-16 07:29:39 +02:00
|
|
|
unsigned long timeout_msec = 0;
|
2007-07-16 07:29:39 +02:00
|
|
|
struct ata_taskfile tf;
|
2006-04-11 15:22:29 +02:00
|
|
|
const char *reason;
|
2007-07-16 07:29:39 +02:00
|
|
|
int rc;
|
2005-11-18 06:14:01 +01:00
|
|
|
|
2006-02-10 15:58:48 +01:00
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
if (ata_link_offline(link)) {
|
2006-03-11 03:42:34 +01:00
|
|
|
DPRINTK("PHY reports no device\n");
|
|
|
|
*class = ATA_DEV_NONE;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
/* put the port into known state */
|
|
|
|
if (sil24_init_port(ap)) {
|
2007-10-26 06:03:37 +02:00
|
|
|
reason = "port not ready";
|
2006-04-11 15:32:19 +02:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
/* do SRST */
|
2007-07-16 07:29:39 +02:00
|
|
|
if (time_after(deadline, jiffies))
|
|
|
|
timeout_msec = jiffies_to_msecs(deadline - jiffies);
|
2005-11-18 06:14:01 +01:00
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
ata_tf_init(link->device, &tf); /* doesn't really matter */
|
2007-07-16 07:29:39 +02:00
|
|
|
rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
|
|
|
|
timeout_msec);
|
2007-07-16 07:29:39 +02:00
|
|
|
if (rc == -EBUSY) {
|
|
|
|
reason = "timeout";
|
|
|
|
goto err;
|
|
|
|
} else if (rc) {
|
|
|
|
reason = "SRST command error";
|
2006-04-11 15:22:29 +02:00
|
|
|
goto err;
|
2006-02-10 15:58:48 +01:00
|
|
|
}
|
2006-03-11 03:42:34 +01:00
|
|
|
|
2007-07-16 07:29:39 +02:00
|
|
|
sil24_read_tf(ap, 0, &tf);
|
|
|
|
*class = ata_dev_classify(&tf);
|
2006-03-11 03:42:34 +01:00
|
|
|
|
2006-02-10 15:58:48 +01:00
|
|
|
if (*class == ATA_DEV_UNKNOWN)
|
|
|
|
*class = ATA_DEV_NONE;
|
2005-11-18 06:14:01 +01:00
|
|
|
|
2006-03-11 03:42:34 +01:00
|
|
|
out:
|
2006-02-10 15:58:48 +01:00
|
|
|
DPRINTK("EXIT, class=%u\n", *class);
|
2005-11-18 06:14:01 +01:00
|
|
|
return 0;
|
2006-04-11 15:22:29 +02:00
|
|
|
|
|
|
|
err:
|
2007-08-06 11:36:23 +02:00
|
|
|
ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
|
2006-04-11 15:22:29 +02:00
|
|
|
return -EIO;
|
2005-11-18 06:14:01 +01:00
|
|
|
}
|
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
static int sil24_softreset(struct ata_link *link, unsigned int *class,
|
2007-07-16 07:29:39 +02:00
|
|
|
unsigned long deadline)
|
|
|
|
{
|
2007-09-23 06:19:54 +02:00
|
|
|
return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
|
2007-07-16 07:29:39 +02:00
|
|
|
}
|
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
static int sil24_hardreset(struct ata_link *link, unsigned int *class,
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 08:50:52 +01:00
|
|
|
unsigned long deadline)
|
2006-02-10 15:58:48 +01:00
|
|
|
{
|
2007-08-06 11:36:23 +02:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2007-09-23 06:19:54 +02:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
|
|
|
int did_port_rst = 0;
|
2006-04-11 15:32:19 +02:00
|
|
|
const char *reason;
|
2006-05-31 11:27:59 +02:00
|
|
|
int tout_msec, rc;
|
2006-04-11 15:32:19 +02:00
|
|
|
u32 tmp;
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
retry:
|
|
|
|
/* Sometimes, DEV_RST is not enough to recover the controller.
|
|
|
|
* This happens often after PM DMA CS errata.
|
|
|
|
*/
|
|
|
|
if (pp->do_port_rst) {
|
|
|
|
ata_port_printk(ap, KERN_WARNING, "controller in dubious "
|
|
|
|
"state, performing PORT_RST\n");
|
|
|
|
|
|
|
|
writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
|
|
|
|
msleep(10);
|
|
|
|
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
|
|
|
|
ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
|
|
|
|
10, 5000);
|
|
|
|
|
|
|
|
/* restore port configuration */
|
|
|
|
sil24_config_port(ap);
|
|
|
|
sil24_config_pmp(ap, ap->nr_pmp_links);
|
|
|
|
|
|
|
|
pp->do_port_rst = 0;
|
|
|
|
did_port_rst = 1;
|
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
/* sil24 does the right thing(tm) without any protection */
|
2007-08-06 11:36:23 +02:00
|
|
|
sata_set_spd(link);
|
2006-04-11 15:32:19 +02:00
|
|
|
|
|
|
|
tout_msec = 100;
|
2007-08-06 11:36:23 +02:00
|
|
|
if (ata_link_online(link))
|
2006-04-11 15:32:19 +02:00
|
|
|
tout_msec = 5000;
|
|
|
|
|
|
|
|
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
|
|
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
2007-10-26 06:03:37 +02:00
|
|
|
PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
|
|
|
|
tout_msec);
|
2006-04-11 15:32:19 +02:00
|
|
|
|
2006-05-31 11:27:59 +02:00
|
|
|
/* SStatus oscillates between zero and valid status after
|
|
|
|
* DEV_RST, debounce it.
|
2006-04-11 15:32:19 +02:00
|
|
|
*/
|
2007-08-06 11:36:23 +02:00
|
|
|
rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
|
2006-05-31 11:27:59 +02:00
|
|
|
if (rc) {
|
|
|
|
reason = "PHY debouncing failed";
|
|
|
|
goto err;
|
|
|
|
}
|
2006-04-11 15:32:19 +02:00
|
|
|
|
|
|
|
if (tmp & PORT_CS_DEV_RST) {
|
2007-08-06 11:36:23 +02:00
|
|
|
if (ata_link_offline(link))
|
2006-04-11 15:32:19 +02:00
|
|
|
return 0;
|
|
|
|
reason = "link not ready";
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2006-05-31 11:27:59 +02:00
|
|
|
/* Sil24 doesn't store signature FIS after hardreset, so we
|
|
|
|
* can't wait for BSY to clear. Some devices take a long time
|
|
|
|
* to get ready and those devices will choke if we don't wait
|
|
|
|
* for BSY clearance here. Tell libata to perform follow-up
|
|
|
|
* softreset.
|
2006-04-11 15:32:19 +02:00
|
|
|
*/
|
2006-05-31 11:27:59 +02:00
|
|
|
return -EAGAIN;
|
2006-04-11 15:32:19 +02:00
|
|
|
|
|
|
|
err:
|
2007-09-23 06:19:54 +02:00
|
|
|
if (!did_port_rst) {
|
|
|
|
pp->do_port_rst = 1;
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
2007-08-06 11:36:23 +02:00
|
|
|
ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
|
2006-04-11 15:32:19 +02:00
|
|
|
return -EIO;
|
2006-02-10 15:58:48 +01:00
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
|
2005-11-18 06:16:45 +01:00
|
|
|
struct sil24_sge *sge)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2005-10-19 04:14:54 +02:00
|
|
|
struct scatterlist *sg;
|
2007-10-18 22:21:18 +02:00
|
|
|
struct sil24_sge *last_sge = NULL;
|
2007-12-05 08:43:11 +01:00
|
|
|
unsigned int si;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2007-12-05 08:43:11 +01:00
|
|
|
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
2005-07-28 03:36:22 +02:00
|
|
|
sge->addr = cpu_to_le64(sg_dma_address(sg));
|
|
|
|
sge->cnt = cpu_to_le32(sg_dma_len(sg));
|
2007-10-18 22:21:18 +02:00
|
|
|
sge->flags = 0;
|
|
|
|
|
|
|
|
last_sge = sge;
|
2005-10-19 04:14:54 +02:00
|
|
|
sge++;
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
2007-10-18 22:21:18 +02:00
|
|
|
|
2007-12-05 08:43:11 +01:00
|
|
|
last_sge->flags = cpu_to_le32(SGE_TRM);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
static int sil24_qc_defer(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_link *link = qc->dev->link;
|
|
|
|
struct ata_port *ap = link->ap;
|
|
|
|
u8 prot = qc->tf.protocol;
|
2008-01-10 07:47:56 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* There is a bug in the chip:
|
|
|
|
* Port LRAM Causes the PRB/SGT Data to be Corrupted
|
|
|
|
* If the host issues a read request for LRAM and SActive registers
|
|
|
|
* while active commands are available in the port, PRB/SGT data in
|
|
|
|
* the LRAM can become corrupted. This issue applies only when
|
|
|
|
* reading from, but not writing to, the LRAM.
|
|
|
|
*
|
|
|
|
* Therefore, reading LRAM when there is no particular error [and
|
|
|
|
* other commands may be outstanding] is prohibited.
|
|
|
|
*
|
|
|
|
* To avoid this bug there are two situations where a command must run
|
|
|
|
* exclusive of any other commands on the port:
|
|
|
|
*
|
|
|
|
* - ATAPI commands which check the sense data
|
|
|
|
* - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
|
|
|
|
* set.
|
|
|
|
*
|
|
|
|
*/
|
2007-11-27 11:28:53 +01:00
|
|
|
int is_excl = (ata_is_atapi(prot) ||
|
2008-01-10 07:47:56 +01:00
|
|
|
(qc->flags & ATA_QCFLAG_RESULT_TF));
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
if (unlikely(ap->excl_link)) {
|
|
|
|
if (link == ap->excl_link) {
|
|
|
|
if (ap->nr_active_links)
|
|
|
|
return ATA_DEFER_PORT;
|
|
|
|
qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
|
|
|
|
} else
|
|
|
|
return ATA_DEFER_PORT;
|
2008-01-10 07:47:56 +01:00
|
|
|
} else if (unlikely(is_excl)) {
|
2007-09-23 06:19:54 +02:00
|
|
|
ap->excl_link = link;
|
|
|
|
if (ap->nr_active_links)
|
|
|
|
return ATA_DEFER_PORT;
|
|
|
|
qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ata_std_qc_defer(qc);
|
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static void sil24_qc_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
2006-05-15 14:03:56 +02:00
|
|
|
union sil24_cmd_block *cb;
|
2005-11-18 06:16:45 +01:00
|
|
|
struct sil24_prb *prb;
|
|
|
|
struct sil24_sge *sge;
|
2006-04-11 15:32:19 +02:00
|
|
|
u16 ctrl = 0;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
cb = &pp->cmd_block[sil24_tag(qc->tag)];
|
|
|
|
|
2007-11-27 11:28:53 +01:00
|
|
|
if (!ata_is_atapi(qc->tf.protocol)) {
|
2005-11-18 06:16:45 +01:00
|
|
|
prb = &cb->ata.prb;
|
|
|
|
sge = cb->ata.sge;
|
2007-11-27 11:28:53 +01:00
|
|
|
} else {
|
2005-11-18 06:16:45 +01:00
|
|
|
prb = &cb->atapi.prb;
|
|
|
|
sge = cb->atapi.sge;
|
|
|
|
memset(cb->atapi.cdb, 0, 32);
|
2006-02-12 15:32:58 +01:00
|
|
|
memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
|
2005-11-18 06:16:45 +01:00
|
|
|
|
2007-11-27 11:28:53 +01:00
|
|
|
if (ata_is_data(qc->tf.protocol)) {
|
2005-11-18 06:16:45 +01:00
|
|
|
if (qc->tf.flags & ATA_TFLAG_WRITE)
|
2006-04-11 15:32:19 +02:00
|
|
|
ctrl = PRB_CTRL_PACKET_WRITE;
|
2005-11-18 06:16:45 +01:00
|
|
|
else
|
2006-04-11 15:32:19 +02:00
|
|
|
ctrl = PRB_CTRL_PACKET_READ;
|
|
|
|
}
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2006-04-11 15:32:19 +02:00
|
|
|
prb->ctrl = cpu_to_le16(ctrl);
|
2007-09-23 06:19:54 +02:00
|
|
|
ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
|
|
|
if (qc->flags & ATA_QCFLAG_DMAMAP)
|
2005-11-18 06:16:45 +01:00
|
|
|
sil24_fill_sg(qc, sge);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2006-01-23 05:09:36 +01:00
|
|
|
static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2006-05-15 14:03:56 +02:00
|
|
|
unsigned int tag = sil24_tag(qc->tag);
|
|
|
|
dma_addr_t paddr;
|
|
|
|
void __iomem *activate;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
|
|
|
|
activate = port + PORT_CMD_ACTIVATE + tag * 8;
|
|
|
|
|
|
|
|
writel((u32)paddr, activate);
|
|
|
|
writel((u64)paddr >> 32, activate + 4);
|
2006-04-11 15:32:19 +02:00
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sil24_irq_clear(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
/* unused */
|
|
|
|
}
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
static void sil24_pmp_attach(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
sil24_config_pmp(ap, 1);
|
|
|
|
sil24_init_port(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sil24_pmp_detach(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
sil24_init_port(ap);
|
|
|
|
sil24_config_pmp(ap, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
|
|
|
|
unsigned long deadline)
|
|
|
|
{
|
|
|
|
return sil24_do_softreset(link, class, link->pmp, deadline);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
|
|
|
|
unsigned long deadline)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = sil24_init_port(link->ap);
|
|
|
|
if (rc) {
|
|
|
|
ata_link_printk(link, KERN_ERR,
|
|
|
|
"hardreset failed (port not ready)\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
return sata_pmp_std_hardreset(link, class, deadline);
|
|
|
|
}
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
static void sil24_freeze(struct ata_port *ap)
|
2005-11-18 06:09:05 +01:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2005-11-18 06:09:05 +01:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
/* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
|
|
|
|
* PORT_IRQ_ENABLE instead.
|
|
|
|
*/
|
|
|
|
writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
|
2005-11-18 06:09:05 +01:00
|
|
|
}
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
static void sil24_thaw(struct ata_port *ap)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2005-07-28 03:36:22 +02:00
|
|
|
u32 tmp;
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
/* clear IRQ */
|
|
|
|
tmp = readl(port + PORT_IRQ_STAT);
|
|
|
|
writel(tmp, port + PORT_IRQ_STAT);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
/* turn IRQ back on */
|
|
|
|
writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
static void sil24_error_intr(struct ata_port *ap)
|
2005-08-17 06:08:57 +02:00
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2007-07-16 07:29:39 +02:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
2007-09-23 06:19:54 +02:00
|
|
|
struct ata_queued_cmd *qc = NULL;
|
|
|
|
struct ata_link *link;
|
|
|
|
struct ata_eh_info *ehi;
|
|
|
|
int abort = 0, freeze = 0;
|
2006-05-15 13:58:32 +02:00
|
|
|
u32 irq_stat;
|
2005-08-17 06:08:57 +02:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
/* on error, we need to clear IRQ explicitly */
|
2005-08-17 06:08:57 +02:00
|
|
|
irq_stat = readl(port + PORT_IRQ_STAT);
|
2006-05-15 13:58:32 +02:00
|
|
|
writel(irq_stat, port + PORT_IRQ_STAT);
|
2005-10-06 04:43:29 +02:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
/* first, analyze and record host port events */
|
2007-09-23 06:19:54 +02:00
|
|
|
link = &ap->link;
|
|
|
|
ehi = &link->eh_info;
|
2006-05-15 13:58:32 +02:00
|
|
|
ata_ehi_clear_desc(ehi);
|
2005-10-06 04:43:29 +02:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
|
2005-08-17 06:08:57 +02:00
|
|
|
|
2007-09-23 06:14:11 +02:00
|
|
|
if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
|
|
|
|
ata_ehi_push_desc(ehi, "SDB notify");
|
2007-09-23 06:14:13 +02:00
|
|
|
sata_async_notification(ap);
|
2007-09-23 06:14:11 +02:00
|
|
|
}
|
|
|
|
|
2006-05-31 11:28:20 +02:00
|
|
|
if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
|
|
|
|
ata_ehi_hotplugged(ehi);
|
2007-07-16 07:29:39 +02:00
|
|
|
ata_ehi_push_desc(ehi, "%s",
|
|
|
|
irq_stat & PORT_IRQ_PHYRDY_CHG ?
|
|
|
|
"PHY RDY changed" : "device exchanged");
|
2006-05-15 13:58:32 +02:00
|
|
|
freeze = 1;
|
2005-10-06 04:43:39 +02:00
|
|
|
}
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
if (irq_stat & PORT_IRQ_UNK_FIS) {
|
|
|
|
ehi->err_mask |= AC_ERR_HSM;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
ehi->action |= ATA_EH_RESET;
|
2007-07-16 07:29:39 +02:00
|
|
|
ata_ehi_push_desc(ehi, "unknown FIS");
|
2006-05-15 13:58:32 +02:00
|
|
|
freeze = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* deal with command error */
|
|
|
|
if (irq_stat & PORT_IRQ_ERROR) {
|
|
|
|
struct sil24_cerr_info *ci = NULL;
|
|
|
|
unsigned int err_mask = 0, action = 0;
|
2007-09-23 06:19:54 +02:00
|
|
|
u32 context, cerr;
|
|
|
|
int pmp;
|
|
|
|
|
|
|
|
abort = 1;
|
|
|
|
|
|
|
|
/* DMA Context Switch Failure in Port Multiplier Mode
|
|
|
|
* errata. If we have active commands to 3 or more
|
|
|
|
* devices, any error condition on active devices can
|
|
|
|
* corrupt DMA context switching.
|
|
|
|
*/
|
|
|
|
if (ap->nr_active_links >= 3) {
|
|
|
|
ehi->err_mask |= AC_ERR_OTHER;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
ehi->action |= ATA_EH_RESET;
|
2007-09-23 06:19:54 +02:00
|
|
|
ata_ehi_push_desc(ehi, "PMP DMA CS errata");
|
2007-09-23 06:19:54 +02:00
|
|
|
pp->do_port_rst = 1;
|
2007-09-23 06:19:54 +02:00
|
|
|
freeze = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* find out the offending link and qc */
|
|
|
|
if (ap->nr_pmp_links) {
|
|
|
|
context = readl(port + PORT_CONTEXT);
|
|
|
|
pmp = (context >> 5) & 0xf;
|
|
|
|
|
|
|
|
if (pmp < ap->nr_pmp_links) {
|
|
|
|
link = &ap->pmp_link[pmp];
|
|
|
|
ehi = &link->eh_info;
|
|
|
|
qc = ata_qc_from_tag(ap, link->active_tag);
|
|
|
|
|
|
|
|
ata_ehi_clear_desc(ehi);
|
|
|
|
ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
|
|
|
|
irq_stat);
|
|
|
|
} else {
|
|
|
|
err_mask |= AC_ERR_HSM;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
action |= ATA_EH_RESET;
|
2007-09-23 06:19:54 +02:00
|
|
|
freeze = 1;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
qc = ata_qc_from_tag(ap, link->active_tag);
|
2006-05-15 13:58:32 +02:00
|
|
|
|
|
|
|
/* analyze CMD_ERR */
|
|
|
|
cerr = readl(port + PORT_CMD_ERR);
|
|
|
|
if (cerr < ARRAY_SIZE(sil24_cerr_db))
|
|
|
|
ci = &sil24_cerr_db[cerr];
|
|
|
|
|
|
|
|
if (ci && ci->desc) {
|
|
|
|
err_mask |= ci->err_mask;
|
|
|
|
action |= ci->action;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
if (action & ATA_EH_RESET)
|
2008-01-13 06:04:16 +01:00
|
|
|
freeze = 1;
|
2007-07-16 07:29:39 +02:00
|
|
|
ata_ehi_push_desc(ehi, "%s", ci->desc);
|
2006-05-15 13:58:32 +02:00
|
|
|
} else {
|
|
|
|
err_mask |= AC_ERR_OTHER;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
action |= ATA_EH_RESET;
|
2008-01-13 06:04:16 +01:00
|
|
|
freeze = 1;
|
2007-07-16 07:29:39 +02:00
|
|
|
ata_ehi_push_desc(ehi, "unknown command error %d",
|
2006-05-15 13:58:32 +02:00
|
|
|
cerr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* record error info */
|
|
|
|
if (qc) {
|
2007-07-16 07:29:39 +02:00
|
|
|
sil24_read_tf(ap, qc->tag, &pp->tf);
|
2006-05-15 13:58:32 +02:00
|
|
|
qc->err_mask |= err_mask;
|
|
|
|
} else
|
|
|
|
ehi->err_mask |= err_mask;
|
|
|
|
|
|
|
|
ehi->action |= action;
|
2007-09-23 06:19:54 +02:00
|
|
|
|
|
|
|
/* if PMP, resume */
|
|
|
|
if (ap->nr_pmp_links)
|
|
|
|
writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
|
2005-12-05 08:38:02 +01:00
|
|
|
}
|
2006-05-15 13:58:32 +02:00
|
|
|
|
|
|
|
/* freeze or abort */
|
|
|
|
if (freeze)
|
|
|
|
ata_port_freeze(ap);
|
2007-09-23 06:19:54 +02:00
|
|
|
else if (abort) {
|
|
|
|
if (qc)
|
|
|
|
ata_link_abort(qc->dev->link);
|
|
|
|
else
|
|
|
|
ata_port_abort(ap);
|
|
|
|
}
|
2005-08-17 06:08:57 +02:00
|
|
|
}
|
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
static void sil24_finish_qc(struct ata_queued_cmd *qc)
|
|
|
|
{
|
2007-07-16 07:29:39 +02:00
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
if (qc->flags & ATA_QCFLAG_RESULT_TF)
|
2007-07-16 07:29:39 +02:00
|
|
|
sil24_read_tf(ap, qc->tag, &pp->tf);
|
2006-05-15 14:03:56 +02:00
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static inline void sil24_host_intr(struct ata_port *ap)
|
|
|
|
{
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2006-05-15 14:03:56 +02:00
|
|
|
u32 slot_stat, qc_active;
|
|
|
|
int rc;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2007-09-23 05:37:05 +02:00
|
|
|
/* If PCIX_IRQ_WOC, there's an inherent race window between
|
|
|
|
* clearing IRQ pending status and reading PORT_SLOT_STAT
|
|
|
|
* which may cause spurious interrupts afterwards. This is
|
|
|
|
* unavoidable and much better than losing interrupts which
|
|
|
|
* happens if IRQ pending is cleared after reading
|
|
|
|
* PORT_SLOT_STAT.
|
|
|
|
*/
|
|
|
|
if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
|
|
|
|
writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
slot_stat = readl(port + PORT_SLOT_STAT);
|
2006-04-11 15:32:19 +02:00
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
|
|
|
|
sil24_error_intr(ap);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-05-15 14:03:56 +02:00
|
|
|
qc_active = slot_stat & ~HOST_SSTAT_ATTN;
|
|
|
|
rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
|
|
|
|
if (rc > 0)
|
|
|
|
return;
|
|
|
|
if (rc < 0) {
|
2007-08-06 11:36:22 +02:00
|
|
|
struct ata_eh_info *ehi = &ap->link.eh_info;
|
2006-05-15 14:03:56 +02:00
|
|
|
ehi->err_mask |= AC_ERR_HSM;
|
libata: prefer hardreset
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by itself is okay but during operation PHY event
or other error conditions can trigger hardreset and the device may
end up with different configuration.
For example, after a hardreset, previously unlockable HPA can be
unlocked resulting in different device size and thus revalidation
failure. Similar condition can occur during or after resume.
* Certain ATAPI devices require hardreset to recover after certain
error conditions. On PATA, this is done by issuing the DEVICE RESET
command. On SATA, COMRESET has equivalent effect. The problem is
that DEVICE RESET needs its own execution protocol.
For SFF controllers with bare TF access, it can be easily
implemented but more advanced controllers (e.g. ahci and sata_sil24)
require specialized implementations. Simply using hardreset solves
the problem nicely.
* COMRESET initialization sequence is the norm in SATA land and many
SATA devices don't work properly if only SRST is used. For example,
some PMPs behave this way and libata works around by always issuing
hardreset if the host supports PMP.
Like the above example, libata has developed a number of mechanisms
aiming to promote softreset to hardreset if softreset is not going
to work. This approach is time consuming and error prone.
Also, note that, dependingon how you read the specs, it could be
argued that PMP fan-out ports require COMRESET to start operation.
In fact, all the PMPs on the market except one don't work properly
if COMRESET is not issued to fan-out ports after PMP reset.
* COMRESET is an integral part of SATA connection and any working
device should be able to handle COMRESET properly. After all, it's
the way to signal hardreset during reboot. This is the most used
and recommended (at least by the ahci spec) method of resetting
devices.
So, this patch makes libata prefer hardreset over softreset by making
the following changes.
* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever
ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is
now only used to tell prereset whether soft or hard reset will be
issued.
* Strip out now unneeded promote-to-hardreset logics from
ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and
other places.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-01-23 16:05:14 +01:00
|
|
|
ehi->action |= ATA_EH_RESET;
|
2006-05-15 14:03:56 +02:00
|
|
|
ata_port_freeze(ap);
|
2006-05-15 13:58:32 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-09-23 05:37:05 +02:00
|
|
|
/* spurious interrupts are expected if PCIX_IRQ_WOC */
|
|
|
|
if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
|
2006-05-15 13:58:32 +02:00
|
|
|
ata_port_printk(ap, KERN_INFO, "spurious interrupt "
|
2006-05-15 14:03:56 +02:00
|
|
|
"(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
|
2007-08-06 11:36:22 +02:00
|
|
|
slot_stat, ap->link.active_tag, ap->link.sactive);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 15:55:46 +02:00
|
|
|
static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
|
2005-07-28 03:36:22 +02:00
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_host *host = dev_instance;
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
|
2005-07-28 03:36:22 +02:00
|
|
|
unsigned handled = 0;
|
|
|
|
u32 status;
|
|
|
|
int i;
|
|
|
|
|
2007-02-01 07:06:36 +01:00
|
|
|
status = readl(host_base + HOST_IRQ_STAT);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2005-08-17 06:08:52 +02:00
|
|
|
if (status == 0xffffffff) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
|
|
|
|
"PCI fault or device removal?\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
if (!(status & IRQ_STAT_4PORTS))
|
|
|
|
goto out;
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_lock(&host->lock);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
for (i = 0; i < host->n_ports; i++)
|
2005-07-28 03:36:22 +02:00
|
|
|
if (status & (1 << i)) {
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_port *ap = host->ports[i];
|
2006-04-02 11:51:52 +02:00
|
|
|
if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
|
2007-07-03 01:10:25 +02:00
|
|
|
sil24_host_intr(ap);
|
2005-08-17 06:08:47 +02:00
|
|
|
handled++;
|
|
|
|
} else
|
|
|
|
printk(KERN_ERR DRV_NAME
|
|
|
|
": interrupt from disabled port %d\n", i);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
spin_unlock(&host->lock);
|
2005-07-28 03:36:22 +02:00
|
|
|
out:
|
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
2006-05-15 13:58:32 +02:00
|
|
|
static void sil24_error_handler(struct ata_port *ap)
|
|
|
|
{
|
2007-09-23 06:19:54 +02:00
|
|
|
struct sil24_port_priv *pp = ap->private_data;
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
if (sil24_init_port(ap))
|
2006-05-15 13:58:32 +02:00
|
|
|
ata_eh_freeze_port(ap);
|
|
|
|
|
|
|
|
/* perform recovery */
|
2007-09-23 06:19:54 +02:00
|
|
|
sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
|
|
|
|
ata_std_postreset, sata_pmp_std_prereset,
|
|
|
|
sil24_pmp_softreset, sil24_pmp_hardreset,
|
|
|
|
sata_pmp_std_postreset);
|
2007-09-23 06:19:54 +02:00
|
|
|
|
|
|
|
pp->do_port_rst = 0;
|
2006-05-15 13:58:32 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
|
|
|
|
/* make DMA engine forget about the failed command */
|
2007-09-23 06:19:54 +02:00
|
|
|
if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
|
|
|
|
ata_eh_freeze_port(ap);
|
2006-05-15 13:58:32 +02:00
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static int sil24_port_start(struct ata_port *ap)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct device *dev = ap->host->dev;
|
2005-07-28 03:36:22 +02:00
|
|
|
struct sil24_port_priv *pp;
|
2005-11-18 06:16:45 +01:00
|
|
|
union sil24_cmd_block *cb;
|
2006-05-15 14:03:56 +02:00
|
|
|
size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
|
2005-07-28 03:36:22 +02:00
|
|
|
dma_addr_t cb_dma;
|
|
|
|
|
2007-01-20 08:00:28 +01:00
|
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
2005-07-28 03:36:22 +02:00
|
|
|
if (!pp)
|
2007-01-20 08:00:28 +01:00
|
|
|
return -ENOMEM;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2005-10-06 04:43:39 +02:00
|
|
|
pp->tf.command = ATA_DRDY;
|
|
|
|
|
2007-01-20 08:00:28 +01:00
|
|
|
cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
|
2005-11-05 04:08:00 +01:00
|
|
|
if (!cb)
|
2007-01-20 08:00:28 +01:00
|
|
|
return -ENOMEM;
|
2005-07-28 03:36:22 +02:00
|
|
|
memset(cb, 0, cb_size);
|
|
|
|
|
|
|
|
pp->cmd_block = cb;
|
|
|
|
pp->cmd_block_dma = cb_dma;
|
|
|
|
|
|
|
|
ap->private_data = pp;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
static void sil24_init_controller(struct ata_host *host)
|
2006-07-03 09:07:27 +02:00
|
|
|
{
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
|
2006-07-03 09:07:27 +02:00
|
|
|
u32 tmp;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* GPIO off */
|
|
|
|
writel(0, host_base + HOST_FLASH_CMD);
|
|
|
|
|
|
|
|
/* clear global reset & mask interrupts during initialization */
|
|
|
|
writel(0, host_base + HOST_CTRL);
|
|
|
|
|
|
|
|
/* init ports */
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
2007-09-23 06:19:54 +02:00
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
void __iomem *port = ap->ioaddr.cmd_addr;
|
2006-07-03 09:07:27 +02:00
|
|
|
|
|
|
|
/* Initial PHY setting */
|
|
|
|
writel(0x20c, port + PORT_PHY_CFG);
|
|
|
|
|
|
|
|
/* Clear port RST */
|
|
|
|
tmp = readl(port + PORT_CTRL_STAT);
|
|
|
|
if (tmp & PORT_CS_PORT_RST) {
|
|
|
|
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
|
|
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
|
|
|
PORT_CS_PORT_RST,
|
|
|
|
PORT_CS_PORT_RST, 10, 100);
|
|
|
|
if (tmp & PORT_CS_PORT_RST)
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
dev_printk(KERN_ERR, host->dev,
|
2007-10-26 06:03:37 +02:00
|
|
|
"failed to clear port RST\n");
|
2006-07-03 09:07:27 +02:00
|
|
|
}
|
|
|
|
|
2007-09-23 06:19:54 +02:00
|
|
|
/* configure port */
|
|
|
|
sil24_config_port(ap);
|
2006-07-03 09:07:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Turn on interrupts */
|
|
|
|
writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
|
|
|
|
}
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
2007-11-22 10:46:57 +01:00
|
|
|
extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
|
2007-10-26 06:03:37 +02:00
|
|
|
static int printed_version;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
struct ata_port_info pi = sil24_port_info[ent->driver_data];
|
|
|
|
const struct ata_port_info *ppi[] = { &pi, NULL };
|
|
|
|
void __iomem * const *iomap;
|
|
|
|
struct ata_host *host;
|
2005-07-28 03:36:22 +02:00
|
|
|
int i, rc;
|
2006-04-11 15:32:19 +02:00
|
|
|
u32 tmp;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2007-11-22 10:46:57 +01:00
|
|
|
/* cause link error if sil24_cmd_block is sized wrongly */
|
|
|
|
if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
|
|
|
|
__MARKER__sil24_cmd_block_is_sized_wrongly = 1;
|
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
if (!printed_version++)
|
2005-10-30 20:39:11 +01:00
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
/* acquire resources */
|
2007-01-20 08:00:28 +01:00
|
|
|
rc = pcim_enable_device(pdev);
|
2005-07-28 03:36:22 +02:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2007-02-01 07:06:36 +01:00
|
|
|
rc = pcim_iomap_regions(pdev,
|
|
|
|
(1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
|
|
|
|
DRV_NAME);
|
2005-07-28 03:36:22 +02:00
|
|
|
if (rc)
|
2007-01-20 08:00:28 +01:00
|
|
|
return rc;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
iomap = pcim_iomap_table(pdev);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
/* apply workaround for completion IRQ loss on PCI-X errata */
|
|
|
|
if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
|
|
|
|
tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
|
|
|
|
if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
|
|
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
|
|
|
"Applying completion IRQ loss on PCI-X "
|
|
|
|
"errata fix\n");
|
|
|
|
else
|
|
|
|
pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
|
|
|
|
}
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
/* allocate and fill host */
|
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi,
|
|
|
|
SIL24_FLAG2NPORTS(ppi[0]->flags));
|
|
|
|
if (!host)
|
|
|
|
return -ENOMEM;
|
|
|
|
host->iomap = iomap;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
2007-08-18 06:14:55 +02:00
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
size_t offset = ap->port_no * PORT_REGS_SIZE;
|
|
|
|
void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
host->ports[i]->ioaddr.cmd_addr = port;
|
|
|
|
host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
|
2005-07-28 03:36:22 +02:00
|
|
|
|
2007-08-18 06:14:55 +02:00
|
|
|
ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
|
|
|
|
ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
}
|
2005-07-28 03:36:22 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
/* configure and activate the device */
|
2006-04-11 15:32:19 +02:00
|
|
|
if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"64-bit DMA enable failed\n");
|
2007-01-20 08:00:28 +01:00
|
|
|
return rc;
|
2006-04-11 15:32:19 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"32-bit DMA enable failed\n");
|
2007-01-20 08:00:28 +01:00
|
|
|
return rc;
|
2006-04-11 15:32:19 +02:00
|
|
|
}
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"32-bit consistent DMA enable failed\n");
|
2007-01-20 08:00:28 +01:00
|
|
|
return rc;
|
2006-04-11 15:32:19 +02:00
|
|
|
}
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
sil24_init_controller(host);
|
2005-07-28 03:36:22 +02:00
|
|
|
|
|
|
|
pci_set_master(pdev);
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
|
|
|
|
&sil24_sht);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
2006-08-15 07:49:30 +02:00
|
|
|
#ifdef CONFIG_PM
|
2006-07-03 09:07:27 +02:00
|
|
|
static int sil24_pci_device_resume(struct pci_dev *pdev)
|
|
|
|
{
|
2006-08-24 09:19:22 +02:00
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
2007-02-01 07:06:36 +01:00
|
|
|
void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
|
2006-12-26 11:39:50 +01:00
|
|
|
int rc;
|
2006-07-03 09:07:27 +02:00
|
|
|
|
2006-12-26 11:39:50 +01:00
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-07-03 09:07:27 +02:00
|
|
|
|
|
|
|
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
|
2007-02-01 07:06:36 +01:00
|
|
|
writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
|
2006-07-03 09:07:27 +02:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 16:44:08 +02:00
|
|
|
sil24_init_controller(host);
|
2006-07-03 09:07:27 +02:00
|
|
|
|
2006-08-24 09:19:22 +02:00
|
|
|
ata_host_resume(host);
|
2006-07-03 09:07:27 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-09-23 06:19:54 +02:00
|
|
|
|
|
|
|
static int sil24_port_resume(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
sil24_config_pmp(ap, ap->nr_pmp_links);
|
|
|
|
return 0;
|
|
|
|
}
|
2006-08-15 07:49:30 +02:00
|
|
|
#endif
|
2006-07-03 09:07:27 +02:00
|
|
|
|
2005-07-28 03:36:22 +02:00
|
|
|
static int __init sil24_init(void)
|
|
|
|
{
|
2006-08-10 11:13:18 +02:00
|
|
|
return pci_register_driver(&sil24_pci_driver);
|
2005-07-28 03:36:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit sil24_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&sil24_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Tejun Heo");
|
|
|
|
MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
|
|
|
|
|
|
|
|
module_init(sil24_init);
|
|
|
|
module_exit(sil24_exit);
|