2007-09-26 02:57:13 +02:00
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/*
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2009-11-08 16:39:55 +01:00
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Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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2007-09-26 02:57:13 +02:00
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt61pci
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Abstract: rt61pci device specific routines.
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Supported chipsets: RT2561, RT2561s, RT2661.
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*/
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2008-03-09 22:44:54 +01:00
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#include <linux/crc-itu-t.h>
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2007-09-26 02:57:13 +02:00
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/slab.h>
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2007-09-26 02:57:13 +02:00
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#include <linux/pci.h>
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#include <linux/eeprom_93cx6.h>
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#include "rt2x00.h"
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#include "rt2x00pci.h"
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#include "rt61pci.h"
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2008-08-06 17:27:31 +02:00
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/*
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* Allow hardware encryption to be disabled.
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*/
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2011-12-19 15:08:01 +01:00
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static bool modparam_nohwcrypt = false;
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2008-08-06 17:27:31 +02:00
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module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
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2007-09-26 02:57:13 +02:00
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/*
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* Register access.
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* BBP and RF register require indirect register access,
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* and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
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* These indirect registers work with busy bits,
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* and we will try maximal REGISTER_BUSY_COUNT times to access
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* the register while taking a REGISTER_BUSY_DELAY us delay
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2009-11-09 09:45:50 +01:00
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* between each attempt. When the busy bit is still set at that time,
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2007-09-26 02:57:13 +02:00
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* the access attempt is considered to have failed,
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* and we will print an error.
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*/
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2008-11-10 19:41:40 +01:00
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#define WAIT_FOR_BBP(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
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#define WAIT_FOR_RF(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
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#define WAIT_FOR_MCU(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
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H2M_MAILBOX_CSR_OWNER, (__reg))
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2007-09-26 02:57:13 +02:00
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2007-10-27 13:41:25 +02:00
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static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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2007-09-26 02:57:13 +02:00
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const unsigned int word, const u8 value)
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{
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u32 reg;
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2008-11-09 23:40:46 +01:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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/*
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2008-11-10 19:41:40 +01:00
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* Wait until the BBP becomes available, afterwards we
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* can safely write the new data into the register.
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2007-09-26 02:57:13 +02:00
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*/
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2008-11-10 19:41:40 +01:00
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if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
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rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
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rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
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rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
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}
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2008-11-09 23:40:46 +01:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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}
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2007-10-27 13:41:25 +02:00
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static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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2007-09-26 02:57:13 +02:00
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const unsigned int word, u8 *value)
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{
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u32 reg;
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2008-11-09 23:40:46 +01:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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/*
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2008-11-10 19:41:40 +01:00
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* Wait until the BBP becomes available, afterwards we
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* can safely write the read request into the register.
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* After the data has been written, we wait until hardware
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* returns the correct value, if at any time the register
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* doesn't become available in time, reg will be 0xffffffff
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* which means we return 0xff to the caller.
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2007-09-26 02:57:13 +02:00
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*/
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2008-11-10 19:41:40 +01:00
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if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
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rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
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2007-09-26 02:57:13 +02:00
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2008-11-10 19:41:40 +01:00
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rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
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2007-09-26 02:57:13 +02:00
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2008-11-10 19:41:40 +01:00
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WAIT_FOR_BBP(rt2x00dev, ®);
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}
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2007-09-26 02:57:13 +02:00
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*value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
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2008-11-09 23:40:46 +01:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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}
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2007-10-27 13:41:25 +02:00
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static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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2007-09-26 02:57:13 +02:00
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const unsigned int word, const u32 value)
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{
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u32 reg;
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2008-11-09 23:40:46 +01:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2008-11-10 19:41:40 +01:00
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/*
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* Wait until the RF becomes available, afterwards we
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* can safely write the new data into the register.
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*/
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if (WAIT_FOR_RF(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
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rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
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rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
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rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
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rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
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rt2x00_rf_write(rt2x00dev, word, value);
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2007-09-26 02:57:13 +02:00
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}
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2008-11-09 23:40:46 +01:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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}
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2007-10-27 13:41:25 +02:00
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static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
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2007-09-26 02:57:13 +02:00
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const u8 command, const u8 token,
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const u8 arg0, const u8 arg1)
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{
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u32 reg;
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2008-11-09 23:40:46 +01:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2008-11-10 19:41:40 +01:00
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/*
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* Wait until the MCU becomes available, afterwards we
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* can safely write the new data into the register.
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*/
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if (WAIT_FOR_MCU(rt2x00dev, ®)) {
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
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rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
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rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
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rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
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rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
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rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
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}
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2008-11-09 23:40:46 +01:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 02:57:13 +02:00
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}
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static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
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eeprom->reg_data_clock =
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!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
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eeprom->reg_chip_select =
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!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
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}
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static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg = 0;
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rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
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!!eeprom->reg_data_clock);
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rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
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}
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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static const struct rt2x00debug rt61pci_rt2x00debug = {
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.owner = THIS_MODULE,
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.csr = {
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2008-10-29 19:41:03 +01:00
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.read = rt2x00pci_register_read,
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.write = rt2x00pci_register_write,
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.flags = RT2X00DEBUGFS_OFFSET,
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.word_base = CSR_REG_BASE,
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2007-09-26 02:57:13 +02:00
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.word_size = sizeof(u32),
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.word_count = CSR_REG_SIZE / sizeof(u32),
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},
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.eeprom = {
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.read = rt2x00_eeprom_read,
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.write = rt2x00_eeprom_write,
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2008-10-29 19:41:03 +01:00
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.word_base = EEPROM_BASE,
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2007-09-26 02:57:13 +02:00
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.word_size = sizeof(u16),
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.word_count = EEPROM_SIZE / sizeof(u16),
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},
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.bbp = {
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.read = rt61pci_bbp_read,
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.write = rt61pci_bbp_write,
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2008-10-29 19:41:03 +01:00
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.word_base = BBP_BASE,
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2007-09-26 02:57:13 +02:00
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.word_size = sizeof(u8),
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.word_count = BBP_SIZE / sizeof(u8),
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},
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.rf = {
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.read = rt2x00_rf_read,
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.write = rt61pci_rf_write,
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2008-10-29 19:41:03 +01:00
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.word_base = RF_BASE,
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2007-09-26 02:57:13 +02:00
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.word_size = sizeof(u32),
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.word_count = RF_SIZE / sizeof(u32),
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},
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};
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#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
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static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
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2012-08-31 19:22:13 +02:00
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return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
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2007-09-26 02:57:13 +02:00
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}
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2008-09-08 19:07:15 +02:00
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#ifdef CONFIG_RT2X00_LIB_LEDS
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2008-03-31 15:53:44 +02:00
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static void rt61pci_brightness_set(struct led_classdev *led_cdev,
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2008-02-03 15:53:40 +01:00
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enum led_brightness brightness)
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{
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struct rt2x00_led *led =
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container_of(led_cdev, struct rt2x00_led, led_dev);
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unsigned int enabled = brightness != LED_OFF;
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unsigned int a_mode =
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(enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
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unsigned int bg_mode =
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(enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
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if (led->type == LED_TYPE_RADIO) {
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rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
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MCU_LEDCS_RADIO_STATUS, enabled);
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rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
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(led->rt2x00dev->led_mcu_reg & 0xff),
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((led->rt2x00dev->led_mcu_reg >> 8)));
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} else if (led->type == LED_TYPE_ASSOC) {
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rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
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MCU_LEDCS_LINK_BG_STATUS, bg_mode);
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rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
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MCU_LEDCS_LINK_A_STATUS, a_mode);
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rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
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(led->rt2x00dev->led_mcu_reg & 0xff),
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((led->rt2x00dev->led_mcu_reg >> 8)));
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} else if (led->type == LED_TYPE_QUALITY) {
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/*
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* The brightness is divided into 6 levels (0 - 5),
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* this means we need to convert the brightness
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* argument into the matching level within that range.
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*/
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rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
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brightness / (LED_FULL / 6), 0);
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}
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}
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2008-03-31 15:53:44 +02:00
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static int rt61pci_blink_set(struct led_classdev *led_cdev,
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unsigned long *delay_on,
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unsigned long *delay_off)
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{
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struct rt2x00_led *led =
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container_of(led_cdev, struct rt2x00_led, led_dev);
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u32 reg;
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rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
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rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
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rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
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rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
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return 0;
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}
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2008-06-03 20:30:01 +02:00
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static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
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struct rt2x00_led *led,
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enum led_type type)
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{
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led->rt2x00dev = rt2x00dev;
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led->type = type;
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led->led_dev.brightness_set = rt61pci_brightness_set;
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led->led_dev.blink_set = rt61pci_blink_set;
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led->flags = LED_INITIALIZED;
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}
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2008-09-08 19:07:15 +02:00
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#endif /* CONFIG_RT2X00_LIB_LEDS */
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2008-02-03 15:53:40 +01:00
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2007-09-26 02:57:13 +02:00
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/*
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* Configuration handlers.
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*/
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2008-08-04 16:38:02 +02:00
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static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
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struct rt2x00lib_crypto *crypto,
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struct ieee80211_key_conf *key)
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{
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struct hw_key_entry key_entry;
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struct rt2x00_field32 field;
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u32 mask;
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u32 reg;
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if (crypto->cmd == SET_KEY) {
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/*
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* rt2x00lib can't determine the correct free
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* key_idx for shared keys. We have 1 register
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* with key valid bits. The goal is simple, read
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* the register, if that is full we have no slots
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* left.
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* Note that each BSS is allowed to have up to 4
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* shared keys, so put a mask over the allowed
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* entries.
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*/
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mask = (0xf << crypto->bssidx);
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rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
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reg &= mask;
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if (reg && reg == mask)
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return -ENOSPC;
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2008-09-22 19:40:04 +02:00
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key->hw_key_idx += reg ? ffz(reg) : 0;
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2008-08-04 16:38:02 +02:00
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/*
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* Upload key to hardware
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*/
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memcpy(key_entry.key, crypto->key,
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sizeof(key_entry.key));
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memcpy(key_entry.tx_mic, crypto->tx_mic,
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sizeof(key_entry.tx_mic));
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memcpy(key_entry.rx_mic, crypto->rx_mic,
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sizeof(key_entry.rx_mic));
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reg = SHARED_KEY_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&key_entry, sizeof(key_entry));
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/*
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* The cipher types are stored over 2 registers.
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* bssidx 0 and 1 keys are stored in SEC_CSR1 and
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* bssidx 1 and 2 keys are stored in SEC_CSR5.
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* Using the correct defines correctly will cause overhead,
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* so just calculate the correct offset.
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*/
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if (key->hw_key_idx < 8) {
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field.bit_offset = (3 * key->hw_key_idx);
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field.bit_mask = 0x7 << field.bit_offset;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
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rt2x00_set_field32(®, field, crypto->cipher);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
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} else {
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field.bit_offset = (3 * (key->hw_key_idx - 8));
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field.bit_mask = 0x7 << field.bit_offset;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
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rt2x00_set_field32(®, field, crypto->cipher);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
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}
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/*
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* The driver does not support the IV/EIV generation
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* in hardware. However it doesn't support the IV/EIV
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* inside the ieee80211 frame either, but requires it
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2009-11-09 09:45:50 +01:00
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* to be provided separately for the descriptor.
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2008-08-04 16:38:02 +02:00
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* rt2x00lib will cut the IV/EIV data out of all frames
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* given to us by mac80211, but we must tell mac80211
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* to generate the IV/EIV data.
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*/
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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}
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/*
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* SEC_CSR0 contains only single-bit fields to indicate
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* a particular key is valid. Because using the FIELD32()
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2009-11-09 09:45:50 +01:00
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* defines directly will cause a lot of overhead, we use
|
2008-08-04 16:38:02 +02:00
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* a calculation to determine the correct bit directly.
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*/
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mask = 1 << key->hw_key_idx;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
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if (crypto->cmd == SET_KEY)
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reg |= mask;
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else if (crypto->cmd == DISABLE_KEY)
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reg &= ~mask;
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rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
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return 0;
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}
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static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
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struct rt2x00lib_crypto *crypto,
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struct ieee80211_key_conf *key)
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{
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struct hw_pairwise_ta_entry addr_entry;
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struct hw_key_entry key_entry;
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u32 mask;
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u32 reg;
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if (crypto->cmd == SET_KEY) {
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/*
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* rt2x00lib can't determine the correct free
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* key_idx for pairwise keys. We have 2 registers
|
2009-11-09 09:45:50 +01:00
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* with key valid bits. The goal is simple: read
|
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* the first register. If that is full, move to
|
2008-08-04 16:38:02 +02:00
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* the next register.
|
2009-11-09 09:45:50 +01:00
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* When both registers are full, we drop the key.
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* Otherwise, we use the first invalid entry.
|
2008-08-04 16:38:02 +02:00
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*/
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rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
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if (reg && reg == ~0) {
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key->hw_key_idx = 32;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
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if (reg && reg == ~0)
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return -ENOSPC;
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}
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|
2008-09-22 19:40:04 +02:00
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key->hw_key_idx += reg ? ffz(reg) : 0;
|
2008-08-04 16:38:02 +02:00
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/*
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* Upload key to hardware
|
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|
*/
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memcpy(key_entry.key, crypto->key,
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sizeof(key_entry.key));
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memcpy(key_entry.tx_mic, crypto->tx_mic,
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sizeof(key_entry.tx_mic));
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memcpy(key_entry.rx_mic, crypto->rx_mic,
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sizeof(key_entry.rx_mic));
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memset(&addr_entry, 0, sizeof(addr_entry));
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memcpy(&addr_entry, crypto->address, ETH_ALEN);
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addr_entry.cipher = crypto->cipher;
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reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&key_entry, sizeof(key_entry));
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reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&addr_entry, sizeof(addr_entry));
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/*
|
2009-11-09 09:45:50 +01:00
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* Enable pairwise lookup table for given BSS idx.
|
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|
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* Without this, received frames will not be decrypted
|
2008-08-04 16:38:02 +02:00
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* by the hardware.
|
|
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|
*/
|
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rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
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reg |= (1 << crypto->bssidx);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
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|
|
|
|
|
|
|
/*
|
|
|
|
* The driver does not support the IV/EIV generation
|
|
|
|
* in hardware. However it doesn't support the IV/EIV
|
|
|
|
* inside the ieee80211 frame either, but requires it
|
tree-wide: Assorted spelling fixes
In particular, several occurances of funny versions of 'success',
'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address',
'beginning', 'desirable', 'separate' and 'necessary' are fixed.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Joe Perches <joe@perches.com>
Cc: Junio C Hamano <gitster@pobox.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-02-03 01:01:28 +01:00
|
|
|
* to be provided separately for the descriptor.
|
2008-08-04 16:38:02 +02:00
|
|
|
* rt2x00lib will cut the IV/EIV data out of all frames
|
|
|
|
* given to us by mac80211, but we must tell mac80211
|
|
|
|
* to generate the IV/EIV data.
|
|
|
|
*/
|
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|
|
key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
|
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|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
|
|
|
|
* a particular key is valid. Because using the FIELD32()
|
2009-11-09 09:45:50 +01:00
|
|
|
* defines directly will cause a lot of overhead, we use
|
2008-08-04 16:38:02 +02:00
|
|
|
* a calculation to determine the correct bit directly.
|
|
|
|
*/
|
|
|
|
if (key->hw_key_idx < 32) {
|
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|
|
mask = 1 << key->hw_key_idx;
|
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rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
|
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|
|
if (crypto->cmd == SET_KEY)
|
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|
|
reg |= mask;
|
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|
|
else if (crypto->cmd == DISABLE_KEY)
|
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|
|
reg &= ~mask;
|
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|
|
rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
|
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|
|
} else {
|
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|
|
mask = 1 << (key->hw_key_idx - 32);
|
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|
|
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rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
|
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|
|
if (crypto->cmd == SET_KEY)
|
|
|
|
reg |= mask;
|
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|
|
else if (crypto->cmd == DISABLE_KEY)
|
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|
|
reg &= ~mask;
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-03-25 14:13:18 +01:00
|
|
|
static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const unsigned int filter_flags)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start configuration steps.
|
|
|
|
* Note that the version error will always be dropped
|
|
|
|
* and broadcast frames will always be accepted since
|
|
|
|
* there is no filter for it at this time.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
|
|
|
|
!(filter_flags & FIF_FCSFAIL));
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
|
|
|
|
!(filter_flags & FIF_PLCPFAIL));
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
|
2009-08-08 23:55:55 +02:00
|
|
|
!(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
|
2008-03-25 14:13:18 +01:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
|
|
|
|
!(filter_flags & FIF_PROMISC_IN_BSS));
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
|
2008-03-31 15:24:53 +02:00
|
|
|
!(filter_flags & FIF_PROMISC_IN_BSS) &&
|
|
|
|
!rt2x00dev->intf_ap_count);
|
2008-03-25 14:13:18 +01:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
|
|
|
|
!(filter_flags & FIF_ALLMULTI));
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
|
|
|
|
!(filter_flags & FIF_CONTROL));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
}
|
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00_intf *intf,
|
|
|
|
struct rt2x00intf_conf *conf,
|
|
|
|
const unsigned int flags)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
u32 reg;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
if (flags & CONFIG_UPDATE_TYPE) {
|
|
|
|
/*
|
|
|
|
* Enable synchronisation.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
if (flags & CONFIG_UPDATE_MAC) {
|
|
|
|
reg = le32_to_cpu(conf->mac[1]);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
|
|
|
|
conf->mac[1] = cpu_to_le32(reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
|
|
|
|
conf->mac, sizeof(conf->mac));
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
if (flags & CONFIG_UPDATE_BSSID) {
|
|
|
|
reg = le32_to_cpu(conf->bssid[1]);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
|
|
|
|
conf->bssid[1] = cpu_to_le32(reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
|
|
|
|
conf->bssid, sizeof(conf->bssid));
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2008-03-25 14:13:18 +01:00
|
|
|
static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
|
2010-09-08 20:56:32 +02:00
|
|
|
struct rt2x00lib_erp *erp,
|
|
|
|
u32 changed)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
|
2009-09-06 15:14:23 +02:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
|
2009-05-21 19:16:46 +02:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
|
2010-09-08 20:56:32 +02:00
|
|
|
if (changed & BSS_CHANGED_ERP_PREAMBLE) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
|
|
|
|
!!erp->short_preamble);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-09-08 20:56:32 +02:00
|
|
|
if (changed & BSS_CHANGED_BASIC_RATES)
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
|
|
|
|
erp->basic_rates);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-09-08 20:56:32 +02:00
|
|
|
if (changed & BSS_CHANGED_BEACON_INT) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
|
|
|
|
erp->beacon_int * 16);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
}
|
2009-05-21 19:16:46 +02:00
|
|
|
|
2010-09-08 20:56:32 +02:00
|
|
|
if (changed & BSS_CHANGED_ERP_SLOT) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-09-08 20:56:32 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
|
2007-10-13 16:26:23 +02:00
|
|
|
struct antenna_setup *ant)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u8 r3;
|
|
|
|
u8 r4;
|
|
|
|
u8 r77;
|
|
|
|
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 3, &r3);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 4, &r4);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 77, &r77);
|
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
|
2007-10-27 13:39:57 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the RX antenna.
|
|
|
|
*/
|
2007-10-13 16:26:23 +02:00
|
|
|
switch (ant->rx) {
|
2007-09-26 02:57:13 +02:00
|
|
|
case ANTENNA_HW_DIVERSITY:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
|
2008-01-24 19:38:38 +01:00
|
|
|
(rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case ANTENNA_A:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
|
2008-01-24 19:38:38 +01:00
|
|
|
if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
|
|
|
else
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case ANTENNA_B:
|
2008-03-09 22:45:21 +01:00
|
|
|
default:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
|
2008-01-24 19:38:38 +01:00
|
|
|
if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
|
|
|
else
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 77, r77);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 3, r3);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 4, r4);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
|
2007-10-13 16:26:23 +02:00
|
|
|
struct antenna_setup *ant)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u8 r3;
|
|
|
|
u8 r4;
|
|
|
|
u8 r77;
|
|
|
|
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 3, &r3);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 4, &r4);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 77, &r77);
|
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
|
2011-04-18 15:27:06 +02:00
|
|
|
!test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2007-10-27 13:39:57 +02:00
|
|
|
/*
|
|
|
|
* Configure the RX antenna.
|
|
|
|
*/
|
2007-10-13 16:26:23 +02:00
|
|
|
switch (ant->rx) {
|
2007-09-26 02:57:13 +02:00
|
|
|
case ANTENNA_HW_DIVERSITY:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case ANTENNA_A:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case ANTENNA_B:
|
2008-03-09 22:45:21 +01:00
|
|
|
default:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 77, r77);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 3, r3);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 4, r4);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const int p1, const int p2)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
|
|
|
|
|
2012-08-31 19:22:13 +02:00
|
|
|
rt2x00_set_field32(®, MAC_CSR13_DIR4, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR13_VAL4, p1);
|
2007-10-27 13:41:53 +02:00
|
|
|
|
2012-08-31 19:22:13 +02:00
|
|
|
rt2x00_set_field32(®, MAC_CSR13_DIR3, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2);
|
2007-10-27 13:41:53 +02:00
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
|
2007-10-13 16:26:23 +02:00
|
|
|
struct antenna_setup *ant)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u8 r3;
|
|
|
|
u8 r4;
|
|
|
|
u8 r77;
|
|
|
|
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 3, &r3);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 4, &r4);
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 77, &r77);
|
2007-10-27 13:39:57 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the RX antenna.
|
|
|
|
*/
|
|
|
|
switch (ant->rx) {
|
|
|
|
case ANTENNA_A:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
|
|
|
rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
|
2007-10-27 13:39:57 +02:00
|
|
|
break;
|
|
|
|
case ANTENNA_HW_DIVERSITY:
|
|
|
|
/*
|
2008-03-09 22:45:21 +01:00
|
|
|
* FIXME: Antenna selection for the rf 2529 is very confusing
|
|
|
|
* in the legacy driver. Just default to antenna B until the
|
|
|
|
* legacy code can be properly translated into rt2x00 code.
|
2007-10-27 13:39:57 +02:00
|
|
|
*/
|
|
|
|
case ANTENNA_B:
|
2008-03-09 22:45:21 +01:00
|
|
|
default:
|
2007-10-27 13:41:53 +02:00
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
|
|
|
rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
|
2007-10-27 13:39:57 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 77, r77);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt61pci_bbp_write(rt2x00dev, 3, r3);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 4, r4);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct antenna_sel {
|
|
|
|
u8 word;
|
|
|
|
/*
|
|
|
|
* value[0] -> non-LNA
|
|
|
|
* value[1] -> LNA
|
|
|
|
*/
|
|
|
|
u8 value[2];
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct antenna_sel antenna_sel_a[] = {
|
|
|
|
{ 96, { 0x58, 0x78 } },
|
|
|
|
{ 104, { 0x38, 0x48 } },
|
|
|
|
{ 75, { 0xfe, 0x80 } },
|
|
|
|
{ 86, { 0xfe, 0x80 } },
|
|
|
|
{ 88, { 0xfe, 0x80 } },
|
|
|
|
{ 35, { 0x60, 0x60 } },
|
|
|
|
{ 97, { 0x58, 0x58 } },
|
|
|
|
{ 98, { 0x58, 0x58 } },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct antenna_sel antenna_sel_bg[] = {
|
|
|
|
{ 96, { 0x48, 0x68 } },
|
|
|
|
{ 104, { 0x2c, 0x3c } },
|
|
|
|
{ 75, { 0xfe, 0x80 } },
|
|
|
|
{ 86, { 0xfe, 0x80 } },
|
|
|
|
{ 88, { 0xfe, 0x80 } },
|
|
|
|
{ 35, { 0x50, 0x50 } },
|
|
|
|
{ 97, { 0x48, 0x48 } },
|
|
|
|
{ 98, { 0x48, 0x48 } },
|
|
|
|
};
|
|
|
|
|
2008-10-29 17:17:57 +01:00
|
|
|
static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct antenna_setup *ant)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
const struct antenna_sel *sel;
|
|
|
|
unsigned int lna;
|
|
|
|
unsigned int i;
|
|
|
|
u32 reg;
|
|
|
|
|
2008-03-09 22:45:21 +01:00
|
|
|
/*
|
|
|
|
* We should never come here because rt2x00lib is supposed
|
|
|
|
* to catch this and send us the correct antenna explicitely.
|
|
|
|
*/
|
|
|
|
BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
|
|
|
|
ant->tx == ANTENNA_SW_DIVERSITY);
|
|
|
|
|
2008-01-24 19:38:38 +01:00
|
|
|
if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
|
2007-09-26 02:57:13 +02:00
|
|
|
sel = antenna_sel_a;
|
2011-04-18 15:27:06 +02:00
|
|
|
lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
} else {
|
|
|
|
sel = antenna_sel_bg;
|
2011-04-18 15:27:06 +02:00
|
|
|
lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2007-10-27 13:41:53 +02:00
|
|
|
for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
|
|
|
|
rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
|
|
|
|
|
2007-10-13 16:26:42 +02:00
|
|
|
rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
|
2008-01-24 19:38:38 +01:00
|
|
|
rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
|
2007-10-13 16:26:42 +02:00
|
|
|
rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
|
2008-01-24 19:38:38 +01:00
|
|
|
rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
|
2007-10-13 16:26:42 +02:00
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
|
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
|
2007-10-13 16:26:23 +02:00
|
|
|
rt61pci_config_antenna_5x(rt2x00dev, ant);
|
2009-12-23 00:03:25 +01:00
|
|
|
else if (rt2x00_rf(rt2x00dev, RF2527))
|
2007-10-13 16:26:23 +02:00
|
|
|
rt61pci_config_antenna_2x(rt2x00dev, ant);
|
2009-12-23 00:03:25 +01:00
|
|
|
else if (rt2x00_rf(rt2x00dev, RF2529)) {
|
2011-04-18 15:27:06 +02:00
|
|
|
if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
|
2007-10-13 16:26:23 +02:00
|
|
|
rt61pci_config_antenna_2x(rt2x00dev, ant);
|
2007-09-26 02:57:13 +02:00
|
|
|
else
|
2007-10-13 16:26:23 +02:00
|
|
|
rt61pci_config_antenna_2529(rt2x00dev, ant);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-29 17:17:57 +01:00
|
|
|
static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00lib_conf *libconf)
|
|
|
|
{
|
|
|
|
u16 eeprom;
|
|
|
|
short lna_gain = 0;
|
|
|
|
|
|
|
|
if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
|
2011-04-18 15:27:06 +02:00
|
|
|
if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
|
2008-10-29 17:17:57 +01:00
|
|
|
lna_gain += 14;
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
|
|
|
|
lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
|
|
|
|
} else {
|
2011-04-18 15:27:06 +02:00
|
|
|
if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
|
2008-10-29 17:17:57 +01:00
|
|
|
lna_gain += 14;
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
|
|
|
|
lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00dev->lna_gain = lna_gain;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rf_channel *rf, const int txpower)
|
|
|
|
{
|
|
|
|
u8 r3;
|
|
|
|
u8 r94;
|
|
|
|
u8 smart;
|
|
|
|
|
|
|
|
rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
|
|
|
|
rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
|
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
|
2008-10-29 17:17:57 +01:00
|
|
|
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 3, &r3);
|
|
|
|
rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 3, r3);
|
|
|
|
|
|
|
|
r94 = 6;
|
|
|
|
if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
|
|
|
|
r94 += txpower - MAX_TXPOWER;
|
|
|
|
else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
|
|
|
|
r94 += txpower;
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 94, r94);
|
|
|
|
|
|
|
|
rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
|
|
|
|
|
udelay(200);
|
|
|
|
|
|
|
|
rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
|
|
|
|
|
udelay(200);
|
|
|
|
|
|
|
|
rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
|
|
|
rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
|
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const int txpower)
|
|
|
|
{
|
|
|
|
struct rf_channel rf;
|
|
|
|
|
|
|
|
rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
|
|
|
|
rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
|
|
|
|
rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
|
|
|
|
rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
|
|
|
|
|
|
|
|
rt61pci_config_channel(rt2x00dev, &rf, txpower);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
|
2007-10-06 13:34:52 +02:00
|
|
|
struct rt2x00lib_conf *libconf)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
2008-10-29 17:17:57 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
|
2010-06-14 22:12:54 +02:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
|
2008-10-29 17:17:57 +01:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
|
|
|
|
libconf->conf->long_frame_max_tx_count);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
|
|
|
|
libconf->conf->short_frame_max_tx_count);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-12-20 10:52:42 +01:00
|
|
|
static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00lib_conf *libconf)
|
|
|
|
{
|
|
|
|
enum dev_state state =
|
|
|
|
(libconf->conf->flags & IEEE80211_CONF_PS) ?
|
|
|
|
STATE_SLEEP : STATE_AWAKE;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
if (state == STATE_SLEEP) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN,
|
2009-05-23 21:09:28 +02:00
|
|
|
rt2x00dev->beacon_int - 10);
|
2008-12-20 10:52:42 +01:00
|
|
|
rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP,
|
|
|
|
libconf->conf->listen_interval - 1);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5);
|
|
|
|
|
|
|
|
/* We must first disable autowake before it can be enabled */
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
|
|
|
|
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
|
|
|
|
|
|
|
|
rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
|
|
|
|
} else {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
|
|
|
|
|
|
|
|
rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
struct rt2x00lib_conf *libconf,
|
|
|
|
const unsigned int flags)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-08-06 16:22:17 +02:00
|
|
|
/* Always recalculate LNA gain before changing configuration */
|
|
|
|
rt61pci_config_lna_gain(rt2x00dev, libconf);
|
|
|
|
|
2008-10-29 17:17:57 +01:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
|
2007-10-06 13:34:52 +02:00
|
|
|
rt61pci_config_channel(rt2x00dev, &libconf->rf,
|
|
|
|
libconf->conf->power_level);
|
2008-10-29 17:17:57 +01:00
|
|
|
if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
|
|
|
|
!(flags & IEEE80211_CONF_CHANGE_CHANNEL))
|
2007-10-06 13:34:52 +02:00
|
|
|
rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
|
2008-10-29 17:17:57 +01:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
|
|
|
|
rt61pci_config_retry_limit(rt2x00dev, libconf);
|
2008-12-20 10:52:42 +01:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_PS)
|
|
|
|
rt61pci_config_ps(rt2x00dev, libconf);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Link tuning
|
|
|
|
*/
|
2007-10-13 16:26:12 +02:00
|
|
|
static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update FCS error count from register.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
|
2007-10-13 16:26:12 +02:00
|
|
|
qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Update False CCA count from register.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
|
2007-10-13 16:26:12 +02:00
|
|
|
qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2008-12-20 10:54:54 +01:00
|
|
|
static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual, u8 vgc_level)
|
2008-12-20 10:54:22 +01:00
|
|
|
{
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->vgc_level != vgc_level) {
|
2008-12-20 10:54:22 +01:00
|
|
|
rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
|
2008-12-20 10:54:54 +01:00
|
|
|
qual->vgc_level = vgc_level;
|
|
|
|
qual->vgc_level_reg = vgc_level;
|
2008-12-20 10:54:22 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-12-20 10:54:54 +01:00
|
|
|
static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-12-20 10:54:54 +01:00
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, 0x20);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2008-12-20 10:54:54 +01:00
|
|
|
static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual, const u32 count)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
u8 up_bound;
|
|
|
|
u8 low_bound;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Determine r17 bounds.
|
|
|
|
*/
|
2010-08-06 20:49:27 +02:00
|
|
|
if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
|
2007-09-26 02:57:13 +02:00
|
|
|
low_bound = 0x28;
|
|
|
|
up_bound = 0x48;
|
2011-04-18 15:27:06 +02:00
|
|
|
if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
|
2007-09-26 02:57:13 +02:00
|
|
|
low_bound += 0x10;
|
|
|
|
up_bound += 0x10;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
low_bound = 0x20;
|
|
|
|
up_bound = 0x40;
|
2011-04-18 15:27:06 +02:00
|
|
|
if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
|
2007-09-26 02:57:13 +02:00
|
|
|
low_bound += 0x10;
|
|
|
|
up_bound += 0x10;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
/*
|
|
|
|
* If we are not associated, we should go straight to the
|
|
|
|
* dynamic CCA tuning.
|
|
|
|
*/
|
|
|
|
if (!rt2x00dev->intf_associated)
|
|
|
|
goto dynamic_cca_tune;
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Special big-R17 for very short distance
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->rssi >= -35) {
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, 0x60);
|
2007-09-26 02:57:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Special big-R17 for short distance
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->rssi >= -58) {
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, up_bound);
|
2007-09-26 02:57:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Special big-R17 for middle-short distance
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->rssi >= -66) {
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
|
2007-09-26 02:57:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Special mid-R17 for middle distance
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->rssi >= -74) {
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
|
2007-09-26 02:57:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Special case: Change up_bound based on the rssi.
|
|
|
|
* Lower up_bound when rssi is weaker then -74 dBm.
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
up_bound -= 2 * (-74 - qual->rssi);
|
2007-09-26 02:57:13 +02:00
|
|
|
if (low_bound > up_bound)
|
|
|
|
up_bound = low_bound;
|
|
|
|
|
2008-12-20 10:54:54 +01:00
|
|
|
if (qual->vgc_level > up_bound) {
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, up_bound);
|
2007-09-26 02:57:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
dynamic_cca_tune:
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* r17 does not yet exceed upper limit, continue and base
|
|
|
|
* the r17 tuning on the false CCA count.
|
|
|
|
*/
|
2008-12-20 10:54:54 +01:00
|
|
|
if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
|
|
|
|
else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
|
|
|
|
rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2010-12-13 12:34:22 +01:00
|
|
|
/*
|
|
|
|
* Queue handlers.
|
|
|
|
*/
|
|
|
|
static void rt61pci_start_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
|
|
|
case QID_RX:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_BEACON:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_kick_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_VO:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_VI:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_BE:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_BK:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_stop_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_VO:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_VI:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_BE:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
2010-12-13 12:36:38 +01:00
|
|
|
case QID_AC_BK:
|
2010-12-13 12:34:22 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
|
|
|
|
break;
|
|
|
|
case QID_RX:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_BEACON:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
2011-01-30 13:19:08 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for possibly running tbtt tasklets.
|
|
|
|
*/
|
2011-08-06 13:13:48 +02:00
|
|
|
tasklet_kill(&rt2x00dev->tbtt_tasklet);
|
2010-12-13 12:34:22 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
2008-03-09 22:44:54 +01:00
|
|
|
* Firmware functions
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
|
|
|
static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
2010-02-13 20:55:49 +01:00
|
|
|
u16 chip;
|
2007-09-26 02:57:13 +02:00
|
|
|
char *fw_name;
|
|
|
|
|
2010-02-13 20:55:49 +01:00
|
|
|
pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
|
|
|
|
switch (chip) {
|
|
|
|
case RT2561_PCI_ID:
|
2007-09-26 02:57:13 +02:00
|
|
|
fw_name = FIRMWARE_RT2561;
|
|
|
|
break;
|
2010-02-13 20:55:49 +01:00
|
|
|
case RT2561s_PCI_ID:
|
2007-09-26 02:57:13 +02:00
|
|
|
fw_name = FIRMWARE_RT2561s;
|
|
|
|
break;
|
2010-02-13 20:55:49 +01:00
|
|
|
case RT2661_PCI_ID:
|
2007-09-26 02:57:13 +02:00
|
|
|
fw_name = FIRMWARE_RT2661;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fw_name = NULL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fw_name;
|
|
|
|
}
|
|
|
|
|
2009-01-28 00:33:47 +01:00
|
|
|
static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const u8 *data, const size_t len)
|
2008-03-09 22:44:54 +01:00
|
|
|
{
|
2009-01-28 00:33:47 +01:00
|
|
|
u16 fw_crc;
|
2008-03-09 22:44:54 +01:00
|
|
|
u16 crc;
|
|
|
|
|
|
|
|
/*
|
2009-01-28 00:33:47 +01:00
|
|
|
* Only support 8kb firmware files.
|
|
|
|
*/
|
|
|
|
if (len != 8192)
|
|
|
|
return FW_BAD_LENGTH;
|
|
|
|
|
|
|
|
/*
|
2009-11-09 09:45:50 +01:00
|
|
|
* The last 2 bytes in the firmware array are the crc checksum itself.
|
|
|
|
* This means that we should never pass those 2 bytes to the crc
|
2008-03-09 22:44:54 +01:00
|
|
|
* algorithm.
|
|
|
|
*/
|
2009-01-28 00:33:47 +01:00
|
|
|
fw_crc = (data[len - 2] << 8 | data[len - 1]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use the crc itu-t algorithm.
|
|
|
|
*/
|
2008-03-09 22:44:54 +01:00
|
|
|
crc = crc_itu_t(0, data, len - 2);
|
|
|
|
crc = crc_itu_t_byte(crc, 0);
|
|
|
|
crc = crc_itu_t_byte(crc, 0);
|
|
|
|
|
2009-01-28 00:33:47 +01:00
|
|
|
return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
|
2008-03-09 22:44:54 +01:00
|
|
|
}
|
|
|
|
|
2009-01-28 00:33:47 +01:00
|
|
|
static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const u8 *data, const size_t len)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for stable hardware.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
|
|
if (reg)
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!reg) {
|
|
|
|
ERROR(rt2x00dev, "Unstable hardware.\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Prepare MCU and mailbox for firmware loading.
|
|
|
|
*/
|
|
|
|
reg = 0;
|
|
|
|
rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write firmware to device.
|
|
|
|
*/
|
|
|
|
reg = 0;
|
|
|
|
rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
|
|
|
|
rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
|
|
|
|
data, len);
|
|
|
|
|
|
|
|
rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
|
|
|
|
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
|
|
|
|
if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == 100) {
|
|
|
|
ERROR(rt2x00dev, "MCU Control register not ready.\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2008-07-27 15:06:50 +02:00
|
|
|
/*
|
|
|
|
* Hardware needs another millisecond before it is ready.
|
|
|
|
*/
|
|
|
|
msleep(1);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Reset MAC and BBP registers.
|
|
|
|
*/
|
|
|
|
reg = 0;
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-03-09 22:44:54 +01:00
|
|
|
/*
|
|
|
|
* Initialization functions.
|
|
|
|
*/
|
2008-11-08 15:25:33 +01:00
|
|
|
static bool rt61pci_get_entry_state(struct queue_entry *entry)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-05-10 13:46:03 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 word;
|
|
|
|
|
2008-11-08 15:25:33 +01:00
|
|
|
if (entry->queue->qid == QID_RX) {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-11-08 15:25:33 +01:00
|
|
|
return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
|
|
|
|
} else {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
|
|
|
|
|
|
|
return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
|
|
|
|
rt2x00_get_field32(word, TXD_W0_VALID));
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2008-11-08 15:25:33 +01:00
|
|
|
static void rt61pci_clear_entry(struct queue_entry *entry)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-05-10 13:46:03 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2008-11-08 15:25:33 +01:00
|
|
|
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 word;
|
|
|
|
|
2008-11-08 15:25:33 +01:00
|
|
|
if (entry->queue->qid == QID_RX) {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 5, &word);
|
|
|
|
rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
|
|
|
|
skbdesc->skb_dma);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 5, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 0, word);
|
|
|
|
} else {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_VALID, 0);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 0, word);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2008-02-05 22:42:23 +01:00
|
|
|
static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-05-10 13:46:03 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv;
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize registers.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00dev->tx[0].limit);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00dev->tx[1].limit);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00dev->tx[2].limit);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00dev->tx[3].limit);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00dev->tx[0].desc_size / 4);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
|
2008-02-17 17:33:24 +01:00
|
|
|
rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
|
2008-02-17 17:33:24 +01:00
|
|
|
rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
|
2008-02-17 17:33:24 +01:00
|
|
|
rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
|
2008-02-17 17:33:24 +01:00
|
|
|
rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
|
2008-02-05 22:42:23 +01:00
|
|
|
rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
|
|
|
|
rt2x00dev->rx->desc_size / 4);
|
|
|
|
rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = rt2x00dev->rx->entries[0].priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
|
2008-02-17 17:33:24 +01:00
|
|
|
rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
|
|
|
|
rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
|
|
|
|
rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
|
|
|
|
rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
|
|
|
|
rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
|
|
|
|
rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
|
|
|
|
rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CCK TXD BBP registers
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* OFDM TXD BBP registers
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
|
|
|
|
|
2008-07-08 13:45:20 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
|
|
|
|
|
|
|
|
if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Invalidate all Shared Keys (SEC_CSR0),
|
|
|
|
* and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
|
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
/*
|
|
|
|
* Clear all beacons
|
|
|
|
* For the Beacon base registers we only need to clear
|
|
|
|
* the first byte since that byte contains the VALID and OWNER
|
|
|
|
* bits which (when set to 0) will invalidate the entire beacon.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* We must clear the error counters.
|
|
|
|
* These registers are cleared on read,
|
|
|
|
* so we may pass a useless variable to store the value.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
|
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
|
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset MAC and BBP registers.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-06-03 18:58:56 +02:00
|
|
|
static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
u8 value;
|
|
|
|
|
|
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
|
rt61pci_bbp_read(rt2x00dev, 0, &value);
|
|
|
|
if ((value != 0xff) && (value != 0x00))
|
2008-06-03 18:58:56 +02:00
|
|
|
return 0;
|
2007-09-26 02:57:13 +02:00
|
|
|
udelay(REGISTER_BUSY_DELAY);
|
|
|
|
}
|
|
|
|
|
|
|
|
ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
|
|
|
|
return -EACCES;
|
2008-06-03 18:58:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
u16 eeprom;
|
|
|
|
u8 reg_id;
|
|
|
|
u8 value;
|
|
|
|
|
|
|
|
if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
|
|
|
|
return -EACCES;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 3, 0x00);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 15, 0x30);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 22, 0x38);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 23, 0x06);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 34, 0x12);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 37, 0x07);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 41, 0x60);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 53, 0x10);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 54, 0x18);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 60, 0x10);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 61, 0x04);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 62, 0x04);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 99, 0x00);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 102, 0x16);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, 107, 0x04);
|
|
|
|
|
|
|
|
for (i = 0; i < EEPROM_BBP_SIZE; i++) {
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
|
|
|
|
|
|
|
|
if (eeprom != 0xffff && eeprom != 0x0000) {
|
|
|
|
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
|
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
|
|
|
|
rt61pci_bbp_write(rt2x00dev, reg_id, value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device state switch handlers.
|
|
|
|
*/
|
|
|
|
static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
|
|
|
|
enum dev_state state)
|
|
|
|
{
|
2011-01-30 13:20:52 +01:00
|
|
|
int mask = (state == STATE_RADIO_IRQ_OFF);
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 reg;
|
2011-01-30 13:19:08 +01:00
|
|
|
unsigned long flags;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When interrupts are being enabled, the interrupt registers
|
|
|
|
* should clear the register to assure a clean state.
|
|
|
|
*/
|
|
|
|
if (state == STATE_RADIO_IRQ_ON) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only toggle the interrupts bits we are going to use.
|
|
|
|
* Non-checked interrupt bits are disabled by default.
|
|
|
|
*/
|
2011-01-30 13:19:08 +01:00
|
|
|
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
|
|
|
|
rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
|
2010-09-08 20:57:10 +02:00
|
|
|
rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
|
|
|
|
rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
|
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
|
2010-09-08 20:57:10 +02:00
|
|
|
rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
|
2011-01-30 13:19:08 +01:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
|
|
|
|
if (state == STATE_RADIO_IRQ_OFF) {
|
|
|
|
/*
|
|
|
|
* Ensure that all tasklets are finished.
|
|
|
|
*/
|
2011-08-06 13:13:48 +02:00
|
|
|
tasklet_kill(&rt2x00dev->txstatus_tasklet);
|
|
|
|
tasklet_kill(&rt2x00dev->rxdone_tasklet);
|
|
|
|
tasklet_kill(&rt2x00dev->autowake_tasklet);
|
|
|
|
tasklet_kill(&rt2x00dev->tbtt_tasklet);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize all registers.
|
|
|
|
*/
|
2008-06-03 18:58:56 +02:00
|
|
|
if (unlikely(rt61pci_init_queues(rt2x00dev) ||
|
|
|
|
rt61pci_init_registers(rt2x00dev) ||
|
|
|
|
rt61pci_init_bbp(rt2x00dev)))
|
2007-09-26 02:57:13 +02:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable RX.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
/*
|
2009-01-28 00:32:33 +01:00
|
|
|
* Disable power
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
2009-01-28 00:32:33 +01:00
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
|
|
|
|
{
|
2010-05-13 21:16:03 +02:00
|
|
|
u32 reg, reg2;
|
2007-09-26 02:57:13 +02:00
|
|
|
unsigned int i;
|
|
|
|
char put_to_sleep;
|
|
|
|
|
|
|
|
put_to_sleep = (state != STATE_AWAKE);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
|
|
|
|
rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device is not guaranteed to be in the requested state yet.
|
|
|
|
* We must wait until the register indicates that the
|
|
|
|
* device has entered the correct state.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
2010-05-13 21:16:03 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®2);
|
|
|
|
state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
|
2008-06-03 18:58:56 +02:00
|
|
|
if (state == !put_to_sleep)
|
2007-09-26 02:57:13 +02:00
|
|
|
return 0;
|
2010-05-13 21:16:03 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
msleep(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|
|
|
enum dev_state state)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
case STATE_RADIO_ON:
|
|
|
|
retval = rt61pci_enable_radio(rt2x00dev);
|
|
|
|
break;
|
|
|
|
case STATE_RADIO_OFF:
|
|
|
|
rt61pci_disable_radio(rt2x00dev);
|
|
|
|
break;
|
2008-06-03 18:58:56 +02:00
|
|
|
case STATE_RADIO_IRQ_ON:
|
|
|
|
case STATE_RADIO_IRQ_OFF:
|
|
|
|
rt61pci_toggle_irq(rt2x00dev, state);
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case STATE_DEEP_SLEEP:
|
|
|
|
case STATE_SLEEP:
|
|
|
|
case STATE_STANDBY:
|
|
|
|
case STATE_AWAKE:
|
|
|
|
retval = rt61pci_set_state(rt2x00dev, state);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retval = -ENOTSUPP;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-06-03 18:58:56 +02:00
|
|
|
if (unlikely(retval))
|
|
|
|
ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
|
|
|
|
state, retval);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TX descriptor initialization
|
|
|
|
*/
|
2010-08-23 19:53:39 +02:00
|
|
|
static void rt61pci_write_tx_desc(struct queue_entry *entry,
|
2008-08-04 16:38:02 +02:00
|
|
|
struct txentry_desc *txdesc)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2010-08-23 19:53:39 +02:00
|
|
|
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2010-05-11 23:51:40 +02:00
|
|
|
__le32 *txd = entry_priv->desc;
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 word;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start writing the descriptor words.
|
|
|
|
*/
|
|
|
|
rt2x00_desc_read(txd, 1, &word);
|
2010-11-04 20:38:15 +01:00
|
|
|
rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
|
|
|
|
rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
|
|
|
|
rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
|
|
|
|
rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
|
2008-08-04 16:38:02 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
|
2008-07-20 18:03:38 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
|
|
|
|
test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
|
2008-05-10 13:44:14 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_desc_write(txd, 1, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(txd, 2, &word);
|
2011-03-03 19:42:35 +01:00
|
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
|
|
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
|
|
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
|
|
|
|
txdesc->u.plcp.length_low);
|
|
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
|
|
|
|
txdesc->u.plcp.length_high);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_desc_write(txd, 2, word);
|
|
|
|
|
2008-08-04 16:38:02 +02:00
|
|
|
if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
|
2008-12-02 18:19:48 +01:00
|
|
|
_rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
|
|
|
|
_rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
|
2008-08-04 16:38:02 +02:00
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_desc_read(txd, 5, &word);
|
2010-08-23 19:53:39 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
|
2008-05-10 13:44:14 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
|
|
|
|
skbdesc->entry->entry_idx);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W5_TX_POWER,
|
2010-08-23 19:53:39 +02:00
|
|
|
TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
|
|
|
|
rt2x00_desc_write(txd, 5, word);
|
|
|
|
|
2010-11-04 20:38:15 +01:00
|
|
|
if (entry->queue->qid != QID_BEACON) {
|
2010-05-11 23:51:38 +02:00
|
|
|
rt2x00_desc_read(txd, 6, &word);
|
|
|
|
rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
|
|
|
|
skbdesc->skb_dma);
|
|
|
|
rt2x00_desc_write(txd, 6, word);
|
2008-05-10 13:44:14 +02:00
|
|
|
|
2008-02-03 15:46:24 +01:00
|
|
|
rt2x00_desc_read(txd, 11, &word);
|
2010-05-03 22:43:05 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
|
|
|
|
txdesc->length);
|
2008-02-03 15:46:24 +01:00
|
|
|
rt2x00_desc_write(txd, 11, word);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-05-11 23:51:39 +02:00
|
|
|
/*
|
|
|
|
* Writing TXD word 0 must the last to prevent a race condition with
|
|
|
|
* the device, whereby the device may take hold of the TXD before we
|
|
|
|
* finished updating it.
|
|
|
|
*/
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_desc_read(txd, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_VALID, 1);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
|
2008-02-05 22:42:23 +01:00
|
|
|
test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_ACK,
|
2008-02-05 22:42:23 +01:00
|
|
|
test_bit(ENTRY_TXD_ACK, &txdesc->flags));
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
|
2008-02-05 22:42:23 +01:00
|
|
|
test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_OFDM,
|
2008-12-20 10:59:02 +01:00
|
|
|
(txdesc->rate_mode == RATE_MODE_OFDM));
|
2011-03-03 19:43:25 +01:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
|
2008-05-10 13:42:31 +02:00
|
|
|
test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
|
2008-08-04 16:38:02 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
|
|
|
|
test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
|
|
|
|
test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
|
2010-05-03 22:43:05 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_BURST,
|
2008-02-05 22:42:23 +01:00
|
|
|
test_bit(ENTRY_TXD_BURST, &txdesc->flags));
|
2008-08-04 16:38:02 +02:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_desc_write(txd, 0, word);
|
2010-05-11 23:51:40 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Register descriptor details in skb frame descriptor.
|
|
|
|
*/
|
|
|
|
skbdesc->desc = txd;
|
2010-11-04 20:38:15 +01:00
|
|
|
skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
|
|
|
|
TXD_DESC_SIZE;
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TX data initialization
|
|
|
|
*/
|
2010-05-08 23:40:25 +02:00
|
|
|
static void rt61pci_write_beacon(struct queue_entry *entry,
|
|
|
|
struct txentry_desc *txdesc)
|
2008-07-09 15:12:44 +02:00
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
2010-05-11 23:51:40 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2008-07-09 15:12:44 +02:00
|
|
|
unsigned int beacon_base;
|
2010-12-13 12:39:12 +01:00
|
|
|
unsigned int padding_len;
|
2011-02-14 15:52:25 +01:00
|
|
|
u32 orig_reg, reg;
|
2008-07-09 15:12:44 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable beaconing while we are reloading the beacon data,
|
|
|
|
* otherwise we might be sending out invalid data.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
2011-02-14 15:52:25 +01:00
|
|
|
orig_reg = reg;
|
2008-07-09 15:12:44 +02:00
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
|
2010-06-03 10:51:41 +02:00
|
|
|
/*
|
|
|
|
* Write the TX descriptor for the beacon.
|
|
|
|
*/
|
2010-08-23 19:53:39 +02:00
|
|
|
rt61pci_write_tx_desc(entry, txdesc);
|
2010-06-03 10:51:41 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Dump beacon to userspace through debugfs.
|
|
|
|
*/
|
|
|
|
rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
|
|
|
|
|
2008-07-09 15:12:44 +02:00
|
|
|
/*
|
2010-12-13 12:39:12 +01:00
|
|
|
* Write entire beacon with descriptor and padding to register.
|
2008-07-09 15:12:44 +02:00
|
|
|
*/
|
2010-12-13 12:39:12 +01:00
|
|
|
padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
|
2011-02-14 15:52:25 +01:00
|
|
|
if (padding_len && skb_pad(entry->skb, padding_len)) {
|
|
|
|
ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
|
|
|
|
/* skb freed by skb_pad() on failure */
|
|
|
|
entry->skb = NULL;
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-07-09 15:12:44 +02:00
|
|
|
beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
|
2010-05-11 23:51:40 +02:00
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
|
|
|
|
entry_priv->desc, TXINFO_SIZE);
|
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
|
2010-12-13 12:39:12 +01:00
|
|
|
entry->skb->data,
|
|
|
|
entry->skb->len + padding_len);
|
2008-07-09 15:12:44 +02:00
|
|
|
|
2010-05-08 23:40:24 +02:00
|
|
|
/*
|
|
|
|
* Enable beaconing again.
|
|
|
|
*
|
|
|
|
* For Wi-Fi faily generated beacons between participating
|
|
|
|
* stations. Set TBTT phase adaptive adjustment step to 8us.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
|
|
|
|
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
|
2008-07-09 15:12:44 +02:00
|
|
|
/*
|
|
|
|
* Clean up beacon skb.
|
|
|
|
*/
|
|
|
|
dev_kfree_skb_any(entry->skb);
|
|
|
|
entry->skb = NULL;
|
|
|
|
}
|
|
|
|
|
2011-01-30 13:16:03 +01:00
|
|
|
static void rt61pci_clear_beacon(struct queue_entry *entry)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable beaconing while we are reloading the beacon data,
|
|
|
|
* otherwise we might be sending out invalid data.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear beacon.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_write(rt2x00dev,
|
|
|
|
HW_BEACON_OFFSET(entry->entry_idx), 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable beaconing again.
|
|
|
|
*/
|
|
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* RX control handlers
|
|
|
|
*/
|
|
|
|
static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
|
|
|
|
{
|
2008-08-06 16:22:17 +02:00
|
|
|
u8 offset = rt2x00dev->lna_gain;
|
2007-09-26 02:57:13 +02:00
|
|
|
u8 lna;
|
|
|
|
|
|
|
|
lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
|
|
|
|
switch (lna) {
|
|
|
|
case 3:
|
2008-08-06 16:22:17 +02:00
|
|
|
offset += 90;
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-08-06 16:22:17 +02:00
|
|
|
offset += 74;
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
case 1:
|
2008-08-06 16:22:17 +02:00
|
|
|
offset += 64;
|
2007-09-26 02:57:13 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-06 20:49:27 +02:00
|
|
|
if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
|
2007-09-26 02:57:13 +02:00
|
|
|
if (lna == 3 || lna == 2)
|
|
|
|
offset += 10;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
|
|
|
|
}
|
|
|
|
|
2008-02-05 22:42:23 +01:00
|
|
|
static void rt61pci_fill_rxdone(struct queue_entry *entry,
|
2008-10-17 21:16:17 +02:00
|
|
|
struct rxdone_entry_desc *rxdesc)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2008-08-04 16:38:02 +02:00
|
|
|
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
2008-05-10 13:46:03 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 word0;
|
|
|
|
u32 word1;
|
|
|
|
|
2008-05-10 13:46:03 +02:00
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word0);
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 1, &word1);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
[PATCH] mac80211: revamp interface and filter configuration
Drivers are currently supposed to keep track of monitor
interfaces if they allow so-called "hard" monitor, and
they are also supposed to keep track of multicast etc.
This patch changes that, replaces the set_multicast_list()
callback with a new configure_filter() callback that takes
filter flags (FIF_*) instead of interface flags (IFF_*).
For a driver, this means it should open the filter as much
as necessary to get all frames requested by the filter flags.
Accordingly, the filter flags are named "positively", e.g.
FIF_ALLMULTI.
Multicast filtering is a bit special in that drivers that
have no multicast address filters need to allow multicast
frames through when either the FIF_ALLMULTI flag is set or
when the mc_count value is positive.
At the same time, drivers are no longer notified about
monitor interfaces at all, this means they now need to
implement the start() and stop() callbacks and the new
change_filter_flags() callback. Also, the start()/stop()
ordering changed, start() is now called *before* any
add_interface() as it really should be, and stop() after
any remove_interface().
The patch also changes the behaviour of setting the bssid
to multicast for scanning when IEEE80211_HW_NO_PROBE_FILTERING
is set; the IEEE80211_HW_NO_PROBE_FILTERING flag is removed
and the filter flag FIF_BCN_PRBRESP_PROMISC introduced.
This is a lot more efficient for hardware like b43 that
supports it and other hardware can still set the BSSID
to all-ones.
Driver modifications by Johannes Berg (b43 & iwlwifi), Michael Wu
(rtl8187, adm8211, and p54), Larry Finger (b43legacy), and
Ivo van Doorn (rt2x00).
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-09-17 07:29:23 +02:00
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
|
2008-02-05 22:42:23 +01:00
|
|
|
rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-05-08 23:40:20 +02:00
|
|
|
rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
|
|
|
|
rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
|
2008-08-04 16:38:02 +02:00
|
|
|
|
|
|
|
if (rxdesc->cipher != CIPHER_NONE) {
|
2008-12-02 18:19:48 +01:00
|
|
|
_rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
|
|
|
|
_rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
|
2008-12-02 22:50:33 +01:00
|
|
|
rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
|
|
|
|
|
2008-08-04 16:38:02 +02:00
|
|
|
_rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
|
2008-12-02 22:50:33 +01:00
|
|
|
rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
|
2008-08-04 16:38:02 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Hardware has stripped IV/EIV data from 802.11 frame during
|
2009-11-09 09:45:50 +01:00
|
|
|
* decryption. It has provided the data separately but rt2x00lib
|
2008-08-04 16:38:02 +02:00
|
|
|
* should decide if it should be reinserted.
|
|
|
|
*/
|
|
|
|
rxdesc->flags |= RX_FLAG_IV_STRIPPED;
|
|
|
|
|
|
|
|
/*
|
2011-01-30 13:23:22 +01:00
|
|
|
* The hardware has already checked the Michael Mic and has
|
|
|
|
* stripped it from the frame. Signal this to mac80211.
|
2008-08-04 16:38:02 +02:00
|
|
|
*/
|
|
|
|
rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
|
|
|
|
|
|
|
|
if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
|
|
|
|
rxdesc->flags |= RX_FLAG_DECRYPTED;
|
|
|
|
else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
|
|
|
|
rxdesc->flags |= RX_FLAG_MMIC_ERROR;
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Obtain the status about this packet.
|
2008-03-09 22:49:04 +01:00
|
|
|
* When frame was received with an OFDM bitrate,
|
|
|
|
* the signal is the PLCP value. If it was received with
|
|
|
|
* a CCK bitrate the signal is the rate in 100kbit/s.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
2008-02-05 22:42:23 +01:00
|
|
|
rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
|
2008-08-04 16:38:02 +02:00
|
|
|
rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
|
2008-02-05 22:42:23 +01:00
|
|
|
rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
|
2008-03-15 21:38:07 +01:00
|
|
|
|
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_OFDM))
|
|
|
|
rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
|
2008-08-29 21:07:16 +02:00
|
|
|
else
|
|
|
|
rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
|
2008-03-15 21:38:07 +01:00
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
|
|
|
|
rxdesc->dev_flags |= RXDONE_MY_BSS;
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Interrupt functions.
|
|
|
|
*/
|
|
|
|
static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
2008-02-05 22:42:23 +01:00
|
|
|
struct data_queue *queue;
|
|
|
|
struct queue_entry *entry;
|
|
|
|
struct queue_entry *entry_done;
|
2008-05-10 13:46:03 +02:00
|
|
|
struct queue_entry_priv_pci *entry_priv;
|
2008-02-05 22:42:23 +01:00
|
|
|
struct txdone_entry_desc txdesc;
|
2007-09-26 02:57:13 +02:00
|
|
|
u32 word;
|
|
|
|
u32 reg;
|
|
|
|
int type;
|
|
|
|
int index;
|
2010-06-14 22:13:37 +02:00
|
|
|
int i;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
2010-06-14 22:13:37 +02:00
|
|
|
* TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
|
|
|
|
* at most X times and also stop processing once the TX_STA_FIFO_VALID
|
|
|
|
* flag is not set anymore.
|
|
|
|
*
|
|
|
|
* The legacy drivers use X=TX_RING_SIZE but state in a comment
|
|
|
|
* that the TX_STA_FIFO stack has a size of 16. We stick to our
|
|
|
|
* tx ring size for now.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
2010-11-04 20:37:22 +01:00
|
|
|
for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
|
|
|
|
if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Skip this entry when it contains an invalid
|
2008-02-05 22:42:23 +01:00
|
|
|
* queue identication number.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
|
|
|
type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
|
2011-03-03 19:38:55 +01:00
|
|
|
queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
|
2008-02-05 22:42:23 +01:00
|
|
|
if (unlikely(!queue))
|
2007-09-26 02:57:13 +02:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Skip this entry when it contains an invalid
|
|
|
|
* index number.
|
|
|
|
*/
|
|
|
|
index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
|
2008-02-05 22:42:23 +01:00
|
|
|
if (unlikely(index >= queue->limit))
|
2007-09-26 02:57:13 +02:00
|
|
|
continue;
|
|
|
|
|
2008-02-05 22:42:23 +01:00
|
|
|
entry = &queue->entries[index];
|
2008-05-10 13:46:03 +02:00
|
|
|
entry_priv = entry->priv_data;
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
|
|
|
|
!rt2x00_get_field32(word, TXD_W0_VALID))
|
|
|
|
return;
|
|
|
|
|
2008-02-05 22:42:23 +01:00
|
|
|
entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
|
2007-11-12 15:03:12 +01:00
|
|
|
while (entry != entry_done) {
|
2008-02-05 22:42:23 +01:00
|
|
|
/* Catch up.
|
|
|
|
* Just report any entries we missed as failed.
|
|
|
|
*/
|
2007-11-12 15:03:12 +01:00
|
|
|
WARNING(rt2x00dev,
|
2008-02-05 22:42:23 +01:00
|
|
|
"TX status report missed for entry %d\n",
|
|
|
|
entry_done->entry_idx);
|
|
|
|
|
2010-09-08 20:57:40 +02:00
|
|
|
rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
|
2008-02-05 22:42:23 +01:00
|
|
|
entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
|
2007-11-12 15:03:12 +01:00
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Obtain the status about this packet.
|
|
|
|
*/
|
2008-05-10 13:42:06 +02:00
|
|
|
txdesc.flags = 0;
|
|
|
|
switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
|
|
|
|
case 0: /* Success, maybe with retry */
|
|
|
|
__set_bit(TXDONE_SUCCESS, &txdesc.flags);
|
|
|
|
break;
|
|
|
|
case 6: /* Failure, excessive retries */
|
|
|
|
__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
|
|
|
|
/* Don't break, this is a failed frame! */
|
|
|
|
default: /* Failure */
|
|
|
|
__set_bit(TXDONE_FAILURE, &txdesc.flags);
|
|
|
|
}
|
2008-02-05 22:42:23 +01:00
|
|
|
txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-06-14 22:12:54 +02:00
|
|
|
/*
|
|
|
|
* the frame was retried at least once
|
|
|
|
* -> hw used fallback rates
|
|
|
|
*/
|
|
|
|
if (txdesc.retry)
|
|
|
|
__set_bit(TXDONE_FALLBACK, &txdesc.flags);
|
|
|
|
|
2010-06-29 21:41:40 +02:00
|
|
|
rt2x00lib_txdone(entry, &txdesc);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-03-30 23:50:25 +02:00
|
|
|
static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
2012-08-03 12:49:14 +02:00
|
|
|
struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
|
2010-03-30 23:50:25 +02:00
|
|
|
|
|
|
|
rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
|
|
|
|
}
|
|
|
|
|
2011-04-18 15:31:31 +02:00
|
|
|
static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00_field32 irq_field)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
2011-01-30 13:19:08 +01:00
|
|
|
u32 reg;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
2011-01-30 13:19:08 +01:00
|
|
|
* Enable a single interrupt. The interrupt mask register
|
|
|
|
* access needs locking.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, irq_field, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00_field32 irq_field)
|
|
|
|
{
|
|
|
|
u32 reg;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2010-03-30 23:50:25 +02:00
|
|
|
/*
|
2011-01-30 13:19:08 +01:00
|
|
|
* Enable a single MCU interrupt. The interrupt mask register
|
|
|
|
* access needs locking.
|
2010-03-30 23:50:25 +02:00
|
|
|
*/
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
2010-03-30 23:50:25 +02:00
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, irq_field, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
|
2010-06-29 21:47:10 +02:00
|
|
|
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
static void rt61pci_txstatus_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
rt61pci_txdone(rt2x00dev);
|
2011-08-06 13:13:48 +02:00
|
|
|
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
|
|
|
rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_tbtt_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
rt2x00lib_beacondone(rt2x00dev);
|
2011-08-06 13:13:48 +02:00
|
|
|
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
|
|
|
rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_rxdone_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
2011-03-28 13:29:44 +02:00
|
|
|
if (rt2x00pci_rxdone(rt2x00dev))
|
2011-08-06 13:13:48 +02:00
|
|
|
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
|
|
|
else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
2011-03-28 13:29:44 +02:00
|
|
|
rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt61pci_autowake_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
rt61pci_wakeup(rt2x00dev);
|
|
|
|
rt2x00pci_register_write(rt2x00dev,
|
|
|
|
M2H_CMD_DONE_CSR, 0xffffffff);
|
2011-08-06 13:13:48 +02:00
|
|
|
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
|
|
|
rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
|
2011-01-30 13:19:08 +01:00
|
|
|
}
|
2010-07-11 12:26:48 +02:00
|
|
|
|
|
|
|
static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = dev_instance;
|
2011-01-30 13:19:08 +01:00
|
|
|
u32 reg_mcu, mask_mcu;
|
|
|
|
u32 reg, mask;
|
2010-07-11 12:26:48 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the interrupt sources & saved to local variable.
|
|
|
|
* Write register value back to clear pending interrupts.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
|
|
|
|
|
|
|
if (!reg && !reg_mcu)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
/*
|
|
|
|
* Schedule tasklets for interrupt handling.
|
|
|
|
*/
|
|
|
|
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
|
|
|
|
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
|
|
|
|
|
|
|
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
|
|
|
|
tasklet_schedule(&rt2x00dev->txstatus_tasklet);
|
|
|
|
|
|
|
|
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
|
|
|
|
tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
|
|
|
|
|
|
|
|
if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
|
|
|
|
tasklet_schedule(&rt2x00dev->autowake_tasklet);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
|
|
|
|
* for interrupts and interrupt masks we can just use the value of
|
|
|
|
* INT_SOURCE_CSR to create the interrupt mask.
|
|
|
|
*/
|
|
|
|
mask = reg;
|
|
|
|
mask_mcu = reg_mcu;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable all interrupts for which a tasklet was scheduled right now,
|
|
|
|
* the tasklet will reenable the appropriate interrupts.
|
|
|
|
*/
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_lock(&rt2x00dev->irqmask_lock);
|
2011-01-30 13:19:08 +01:00
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
|
|
|
reg |= mask;
|
|
|
|
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
2010-07-11 12:26:48 +02:00
|
|
|
|
2011-01-30 13:19:08 +01:00
|
|
|
rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
|
|
|
|
reg |= mask_mcu;
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
|
|
|
|
|
2011-03-03 19:45:16 +01:00
|
|
|
spin_unlock(&rt2x00dev->irqmask_lock);
|
2011-01-30 13:19:08 +01:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
2010-07-11 12:26:48 +02:00
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Device probe functions.
|
|
|
|
*/
|
|
|
|
static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
struct eeprom_93cx6 eeprom;
|
|
|
|
u32 reg;
|
|
|
|
u16 word;
|
|
|
|
u8 *mac;
|
|
|
|
s8 value;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
|
|
|
|
|
|
|
|
eeprom.data = rt2x00dev;
|
|
|
|
eeprom.register_read = rt61pci_eepromregister_read;
|
|
|
|
eeprom.register_write = rt61pci_eepromregister_write;
|
|
|
|
eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
|
|
|
|
PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
|
|
|
|
eeprom.reg_data_in = 0;
|
|
|
|
eeprom.reg_data_out = 0;
|
|
|
|
eeprom.reg_data_clock = 0;
|
|
|
|
eeprom.reg_chip_select = 0;
|
|
|
|
|
|
|
|
eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
|
|
|
|
EEPROM_SIZE / sizeof(u16));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start validation of the data that has been read.
|
|
|
|
*/
|
|
|
|
mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
|
|
|
|
if (!is_valid_ether_addr(mac)) {
|
2012-07-12 21:33:08 +02:00
|
|
|
eth_random_addr(mac);
|
2008-10-27 23:59:26 +01:00
|
|
|
EEPROM(rt2x00dev, "MAC: %pM\n", mac);
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
|
2007-10-13 16:26:18 +02:00
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
|
|
|
|
ANTENNA_B);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
|
|
|
|
ANTENNA_B);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
|
|
|
|
EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
|
2008-12-20 10:57:47 +01:00
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
|
|
|
|
EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
|
|
|
|
LED_MODE_DEFAULT);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
|
|
|
|
EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
|
|
|
|
EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
|
|
|
|
EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
|
|
|
|
} else {
|
|
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
|
|
|
|
if (value < -10 || value > 10)
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
|
|
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
|
|
|
|
if (value < -10 || value > 10)
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
|
2008-02-10 22:50:58 +01:00
|
|
|
EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
|
2007-09-26 02:57:13 +02:00
|
|
|
} else {
|
|
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
|
|
|
|
if (value < -10 || value > 10)
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
|
|
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
|
|
|
|
if (value < -10 || value > 10)
|
|
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
|
|
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u16 value;
|
|
|
|
u16 eeprom;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read EEPROM word for configuration.
|
|
|
|
*/
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Identify RF chipset.
|
|
|
|
*/
|
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
|
2010-02-13 20:55:49 +01:00
|
|
|
rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
|
|
|
|
value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
if (!rt2x00_rf(rt2x00dev, RF5225) &&
|
|
|
|
!rt2x00_rf(rt2x00dev, RF5325) &&
|
|
|
|
!rt2x00_rf(rt2x00dev, RF2527) &&
|
|
|
|
!rt2x00_rf(rt2x00dev, RF2529)) {
|
2007-09-26 02:57:13 +02:00
|
|
|
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2007-10-27 13:39:57 +02:00
|
|
|
/*
|
2009-07-17 21:39:19 +02:00
|
|
|
* Determine number of antennas.
|
2007-10-27 13:39:57 +02:00
|
|
|
*/
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
|
2007-10-27 13:39:57 +02:00
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Identify default antenna configuration.
|
|
|
|
*/
|
2007-10-13 16:26:23 +02:00
|
|
|
rt2x00dev->default_ant.tx =
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
|
2007-10-13 16:26:23 +02:00
|
|
|
rt2x00dev->default_ant.rx =
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read the Frame type.
|
|
|
|
*/
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
2009-11-09 09:45:50 +01:00
|
|
|
* Detect if this device has a hardware controlled radio.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Read frequency offset and RF programming sequence.
|
|
|
|
*/
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read external LNA informations.
|
|
|
|
*/
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
|
|
|
|
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2007-10-27 13:39:57 +02:00
|
|
|
/*
|
2009-11-09 09:45:50 +01:00
|
|
|
* When working with a RF2529 chip without double antenna,
|
2007-10-27 13:39:57 +02:00
|
|
|
* the antenna settings should be gathered from the NIC
|
|
|
|
* eeprom word.
|
|
|
|
*/
|
2009-12-23 00:03:25 +01:00
|
|
|
if (rt2x00_rf(rt2x00dev, RF2529) &&
|
2011-04-18 15:27:06 +02:00
|
|
|
!test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
|
2008-12-20 10:57:47 +01:00
|
|
|
rt2x00dev->default_ant.rx =
|
|
|
|
ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
|
|
|
|
rt2x00dev->default_ant.tx =
|
|
|
|
ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
|
2007-10-27 13:39:57 +02:00
|
|
|
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
|
|
|
|
rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
|
|
|
|
rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Store led settings, for correct led behaviour.
|
|
|
|
* If the eeprom value is invalid,
|
|
|
|
* switch to default led mode.
|
|
|
|
*/
|
2008-09-08 19:07:15 +02:00
|
|
|
#ifdef CONFIG_RT2X00_LIB_LEDS
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
|
2008-02-03 15:53:40 +01:00
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
|
|
|
|
|
2008-06-03 20:30:01 +02:00
|
|
|
rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
|
|
|
|
rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
|
|
|
|
if (value == LED_MODE_SIGNAL_STRENGTH)
|
|
|
|
rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
|
|
|
|
LED_TYPE_QUALITY);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
|
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_GPIO_0));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_GPIO_1));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_GPIO_2));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_GPIO_3));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_GPIO_4));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_RDY_G));
|
2008-02-03 15:53:40 +01:00
|
|
|
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
|
2007-09-26 02:57:13 +02:00
|
|
|
rt2x00_get_field16(eeprom,
|
|
|
|
EEPROM_LED_POLARITY_RDY_A));
|
2008-09-08 19:07:15 +02:00
|
|
|
#endif /* CONFIG_RT2X00_LIB_LEDS */
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RF value list for RF5225 & RF5325
|
|
|
|
* Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
|
|
|
|
*/
|
|
|
|
static const struct rf_channel rf_vals_noseq[] = {
|
|
|
|
{ 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
|
|
|
|
|
|
|
|
/* 802.11 UNI / HyperLan 2 */
|
|
|
|
{ 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
|
|
|
|
{ 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
|
|
|
|
{ 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
|
|
|
|
{ 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
|
|
|
|
{ 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
|
|
|
|
{ 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
|
|
|
|
{ 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
|
|
|
|
{ 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
|
|
|
|
|
|
|
|
/* 802.11 HyperLan 2 */
|
|
|
|
{ 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
|
|
|
|
{ 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
|
|
|
|
{ 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
|
|
|
|
{ 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
|
|
|
|
{ 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
|
|
|
|
{ 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
|
|
|
|
{ 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
|
|
|
|
{ 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
|
|
|
|
{ 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
|
|
|
|
{ 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
|
|
|
|
|
|
|
|
/* 802.11 UNII */
|
|
|
|
{ 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
|
|
|
|
{ 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
|
|
|
|
{ 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
|
|
|
|
{ 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
|
|
|
|
{ 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
|
|
|
|
{ 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
|
|
|
|
|
|
|
|
/* MMAC(Japan)J52 ch 34,38,42,46 */
|
|
|
|
{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
|
|
|
|
{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
|
|
|
|
{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
|
|
|
|
{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RF value list for RF5225 & RF5325
|
|
|
|
* Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
|
|
|
|
*/
|
|
|
|
static const struct rf_channel rf_vals_seq[] = {
|
|
|
|
{ 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
|
|
|
|
{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
|
|
|
|
{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
|
|
|
|
|
|
|
|
/* 802.11 UNI / HyperLan 2 */
|
|
|
|
{ 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
|
|
|
|
{ 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
|
|
|
|
{ 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
|
|
|
|
{ 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
|
|
|
|
{ 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
|
|
|
|
{ 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
|
|
|
|
{ 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
|
|
|
|
{ 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
|
|
|
|
|
|
|
|
/* 802.11 HyperLan 2 */
|
|
|
|
{ 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
|
|
|
|
{ 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
|
|
|
|
{ 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
|
|
|
|
{ 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
|
|
|
|
{ 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
|
|
|
|
{ 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
|
|
|
|
{ 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
|
|
|
|
{ 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
|
|
|
|
{ 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
|
|
|
|
{ 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
|
|
|
|
|
|
|
|
/* 802.11 UNII */
|
|
|
|
{ 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
|
|
|
|
{ 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
|
|
|
|
{ 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
|
|
|
|
{ 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
|
|
|
|
{ 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
|
|
|
|
{ 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
|
|
|
|
|
|
|
|
/* MMAC(Japan)J52 ch 34,38,42,46 */
|
|
|
|
{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
|
|
|
|
{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
|
|
|
|
{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
|
|
|
|
{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
|
|
|
|
};
|
|
|
|
|
2008-08-04 16:38:47 +02:00
|
|
|
static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
struct hw_mode_spec *spec = &rt2x00dev->spec;
|
2008-08-04 16:38:47 +02:00
|
|
|
struct channel_info *info;
|
|
|
|
char *tx_power;
|
2007-09-26 02:57:13 +02:00
|
|
|
unsigned int i;
|
|
|
|
|
2009-12-14 20:33:55 +01:00
|
|
|
/*
|
|
|
|
* Disable powersaving as default.
|
|
|
|
*/
|
|
|
|
rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Initialize all hw fields.
|
|
|
|
*/
|
|
|
|
rt2x00dev->hw->flags =
|
2008-05-08 19:15:40 +02:00
|
|
|
IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
|
2009-01-07 18:28:20 +01:00
|
|
|
IEEE80211_HW_SIGNAL_DBM |
|
|
|
|
IEEE80211_HW_SUPPORTS_PS |
|
|
|
|
IEEE80211_HW_PS_NULLFUNC_STACK;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-06-16 19:55:43 +02:00
|
|
|
SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
|
2007-09-26 02:57:13 +02:00
|
|
|
SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
|
|
|
|
rt2x00_eeprom_addr(rt2x00dev,
|
|
|
|
EEPROM_MAC_ADDR_0));
|
|
|
|
|
|
|
|
/*
|
2010-06-14 22:12:54 +02:00
|
|
|
* As rt61 has a global fallback table we cannot specify
|
|
|
|
* more then one tx rate per frame but since the hw will
|
|
|
|
* try several rates (based on the fallback table) we should
|
2010-10-02 11:32:16 +02:00
|
|
|
* initialize max_report_rates to the maximum number of rates
|
2010-06-14 22:12:54 +02:00
|
|
|
* we are going to try. Otherwise mac80211 will truncate our
|
|
|
|
* reported tx rates and the rc algortihm will end up with
|
|
|
|
* incorrect data.
|
|
|
|
*/
|
2010-10-02 11:32:16 +02:00
|
|
|
rt2x00dev->hw->max_rates = 1;
|
|
|
|
rt2x00dev->hw->max_report_rates = 7;
|
2010-06-14 22:12:54 +02:00
|
|
|
rt2x00dev->hw->max_rate_tries = 1;
|
|
|
|
|
|
|
|
/*
|
2007-09-26 02:57:13 +02:00
|
|
|
* Initialize hw_mode information.
|
|
|
|
*/
|
2008-02-17 17:35:05 +01:00
|
|
|
spec->supported_bands = SUPPORT_BAND_2GHZ;
|
|
|
|
spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2011-04-18 15:27:06 +02:00
|
|
|
if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
|
2007-09-26 02:57:13 +02:00
|
|
|
spec->num_channels = 14;
|
|
|
|
spec->channels = rf_vals_noseq;
|
|
|
|
} else {
|
|
|
|
spec->num_channels = 14;
|
|
|
|
spec->channels = rf_vals_seq;
|
|
|
|
}
|
|
|
|
|
2009-12-23 00:03:25 +01:00
|
|
|
if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
|
2008-02-17 17:35:05 +01:00
|
|
|
spec->supported_bands |= SUPPORT_BAND_5GHZ;
|
2007-09-26 02:57:13 +02:00
|
|
|
spec->num_channels = ARRAY_SIZE(rf_vals_seq);
|
2008-08-04 16:38:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create channel information array
|
|
|
|
*/
|
2010-08-11 09:02:48 +02:00
|
|
|
info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
|
2008-08-04 16:38:47 +02:00
|
|
|
if (!info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
spec->channels_info = info;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-08-04 16:38:47 +02:00
|
|
|
tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
|
2010-08-23 19:56:07 +02:00
|
|
|
for (i = 0; i < 14; i++) {
|
|
|
|
info[i].max_power = MAX_TXPOWER;
|
|
|
|
info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2008-08-04 16:38:47 +02:00
|
|
|
if (spec->num_channels > 14) {
|
|
|
|
tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
|
2010-08-23 19:56:07 +02:00
|
|
|
for (i = 14; i < spec->num_channels; i++) {
|
|
|
|
info[i].max_power = MAX_TXPOWER;
|
|
|
|
info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
|
|
|
|
}
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
2008-08-04 16:38:47 +02:00
|
|
|
|
|
|
|
return 0;
|
2007-09-26 02:57:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
int retval;
|
2012-08-31 19:22:11 +02:00
|
|
|
u32 reg;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2009-08-02 20:30:02 +02:00
|
|
|
/*
|
|
|
|
* Disable power saving.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Allocate eeprom data.
|
|
|
|
*/
|
|
|
|
retval = rt61pci_validate_eeprom(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
retval = rt61pci_init_eeprom(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
2012-08-31 19:22:11 +02:00
|
|
|
/*
|
|
|
|
* Enable rfkill polling by setting GPIO direction of the
|
|
|
|
* rfkill switch GPIO pin correctly.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
|
2012-08-31 19:22:13 +02:00
|
|
|
rt2x00_set_field32(®, MAC_CSR13_DIR5, 1);
|
2012-08-31 19:22:11 +02:00
|
|
|
rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
|
|
|
* Initialize hw specifications.
|
|
|
|
*/
|
2008-08-04 16:38:47 +02:00
|
|
|
retval = rt61pci_probe_hw_mode(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
2007-09-26 02:57:13 +02:00
|
|
|
|
2009-08-08 23:55:55 +02:00
|
|
|
/*
|
|
|
|
* This device has multiple filters for control frames,
|
|
|
|
* but has no a separate filter for PS Poll frames.
|
|
|
|
*/
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
|
2009-08-08 23:55:55 +02:00
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
/*
|
2008-06-16 19:56:31 +02:00
|
|
|
* This device requires firmware and DMA mapped skbs.
|
2007-09-26 02:57:13 +02:00
|
|
|
*/
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
|
|
|
|
__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
|
2008-08-06 17:27:31 +02:00
|
|
|
if (!modparam_nohwcrypt)
|
2011-04-18 15:27:06 +02:00
|
|
|
__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
|
|
|
|
__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
|
2007-09-26 02:57:13 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the rssi offset.
|
|
|
|
*/
|
|
|
|
rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IEEE80211 stack callback functions.
|
|
|
|
*/
|
2011-10-02 10:15:52 +02:00
|
|
|
static int rt61pci_conf_tx(struct ieee80211_hw *hw,
|
|
|
|
struct ieee80211_vif *vif, u16 queue_idx,
|
2008-08-29 21:05:45 +02:00
|
|
|
const struct ieee80211_tx_queue_params *params)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
struct data_queue *queue;
|
|
|
|
struct rt2x00_field32 field;
|
|
|
|
int retval;
|
|
|
|
u32 reg;
|
2009-01-17 20:42:58 +01:00
|
|
|
u32 offset;
|
2008-08-29 21:05:45 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* First pass the configuration through rt2x00lib, that will
|
|
|
|
* update the queue settings and validate the input. After that
|
|
|
|
* we are free to update the registers based on the value
|
|
|
|
* in the queue parameter.
|
|
|
|
*/
|
2011-10-02 10:15:52 +02:00
|
|
|
retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
|
2008-08-29 21:05:45 +02:00
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
2009-01-17 20:42:58 +01:00
|
|
|
/*
|
|
|
|
* We only need to perform additional register initialization
|
2009-11-09 09:45:50 +01:00
|
|
|
* for WMM queues.
|
2009-01-17 20:42:58 +01:00
|
|
|
*/
|
|
|
|
if (queue_idx >= 4)
|
|
|
|
return 0;
|
|
|
|
|
2011-03-03 19:38:55 +01:00
|
|
|
queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
|
2008-08-29 21:05:45 +02:00
|
|
|
|
|
|
|
/* Update WMM TXOP register */
|
2009-01-17 20:42:58 +01:00
|
|
|
offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
|
|
|
|
field.bit_offset = (queue_idx & 1) * 16;
|
|
|
|
field.bit_mask = 0xffff << field.bit_offset;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, offset, ®);
|
|
|
|
rt2x00_set_field32(®, field, queue->txop);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, offset, reg);
|
2008-08-29 21:05:45 +02:00
|
|
|
|
|
|
|
/* Update WMM registers */
|
|
|
|
field.bit_offset = queue_idx * 4;
|
|
|
|
field.bit_mask = 0xf << field.bit_offset;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, field, queue->aifs);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, field, queue->cw_min);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
|
|
|
|
rt2x00_set_field32(®, field, queue->cw_max);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-21 13:06:11 +02:00
|
|
|
static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
2007-09-26 02:57:13 +02:00
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
u64 tsf;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
|
|
|
|
tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
|
|
|
|
tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
|
|
|
|
|
|
|
|
return tsf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct ieee80211_ops rt61pci_mac80211_ops = {
|
|
|
|
.tx = rt2x00mac_tx,
|
[PATCH] mac80211: revamp interface and filter configuration
Drivers are currently supposed to keep track of monitor
interfaces if they allow so-called "hard" monitor, and
they are also supposed to keep track of multicast etc.
This patch changes that, replaces the set_multicast_list()
callback with a new configure_filter() callback that takes
filter flags (FIF_*) instead of interface flags (IFF_*).
For a driver, this means it should open the filter as much
as necessary to get all frames requested by the filter flags.
Accordingly, the filter flags are named "positively", e.g.
FIF_ALLMULTI.
Multicast filtering is a bit special in that drivers that
have no multicast address filters need to allow multicast
frames through when either the FIF_ALLMULTI flag is set or
when the mc_count value is positive.
At the same time, drivers are no longer notified about
monitor interfaces at all, this means they now need to
implement the start() and stop() callbacks and the new
change_filter_flags() callback. Also, the start()/stop()
ordering changed, start() is now called *before* any
add_interface() as it really should be, and stop() after
any remove_interface().
The patch also changes the behaviour of setting the bssid
to multicast for scanning when IEEE80211_HW_NO_PROBE_FILTERING
is set; the IEEE80211_HW_NO_PROBE_FILTERING flag is removed
and the filter flag FIF_BCN_PRBRESP_PROMISC introduced.
This is a lot more efficient for hardware like b43 that
supports it and other hardware can still set the BSSID
to all-ones.
Driver modifications by Johannes Berg (b43 & iwlwifi), Michael Wu
(rtl8187, adm8211, and p54), Larry Finger (b43legacy), and
Ivo van Doorn (rt2x00).
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-09-17 07:29:23 +02:00
|
|
|
.start = rt2x00mac_start,
|
|
|
|
.stop = rt2x00mac_stop,
|
2007-09-26 02:57:13 +02:00
|
|
|
.add_interface = rt2x00mac_add_interface,
|
|
|
|
.remove_interface = rt2x00mac_remove_interface,
|
|
|
|
.config = rt2x00mac_config,
|
2008-03-25 14:13:18 +01:00
|
|
|
.configure_filter = rt2x00mac_configure_filter,
|
2008-08-04 16:38:02 +02:00
|
|
|
.set_key = rt2x00mac_set_key,
|
2010-07-11 12:24:47 +02:00
|
|
|
.sw_scan_start = rt2x00mac_sw_scan_start,
|
|
|
|
.sw_scan_complete = rt2x00mac_sw_scan_complete,
|
2007-09-26 02:57:13 +02:00
|
|
|
.get_stats = rt2x00mac_get_stats,
|
2007-12-28 14:32:58 +01:00
|
|
|
.bss_info_changed = rt2x00mac_bss_info_changed,
|
2008-08-29 21:05:45 +02:00
|
|
|
.conf_tx = rt61pci_conf_tx,
|
2007-09-26 02:57:13 +02:00
|
|
|
.get_tsf = rt61pci_get_tsf,
|
2009-07-01 15:17:35 +02:00
|
|
|
.rfkill_poll = rt2x00mac_rfkill_poll,
|
2010-11-04 20:40:11 +01:00
|
|
|
.flush = rt2x00mac_flush,
|
2011-04-18 15:35:12 +02:00
|
|
|
.set_antenna = rt2x00mac_set_antenna,
|
|
|
|
.get_antenna = rt2x00mac_get_antenna,
|
2011-04-18 15:34:41 +02:00
|
|
|
.get_ringparam = rt2x00mac_get_ringparam,
|
2011-07-06 23:00:21 +02:00
|
|
|
.tx_frames_pending = rt2x00mac_tx_frames_pending,
|
2007-09-26 02:57:13 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
|
|
|
|
.irq_handler = rt61pci_interrupt,
|
2011-01-30 13:19:08 +01:00
|
|
|
.txstatus_tasklet = rt61pci_txstatus_tasklet,
|
|
|
|
.tbtt_tasklet = rt61pci_tbtt_tasklet,
|
|
|
|
.rxdone_tasklet = rt61pci_rxdone_tasklet,
|
|
|
|
.autowake_tasklet = rt61pci_autowake_tasklet,
|
2007-09-26 02:57:13 +02:00
|
|
|
.probe_hw = rt61pci_probe_hw,
|
|
|
|
.get_firmware_name = rt61pci_get_firmware_name,
|
2009-01-28 00:33:47 +01:00
|
|
|
.check_firmware = rt61pci_check_firmware,
|
2007-09-26 02:57:13 +02:00
|
|
|
.load_firmware = rt61pci_load_firmware,
|
|
|
|
.initialize = rt2x00pci_initialize,
|
|
|
|
.uninitialize = rt2x00pci_uninitialize,
|
2008-11-08 15:25:33 +01:00
|
|
|
.get_entry_state = rt61pci_get_entry_state,
|
|
|
|
.clear_entry = rt61pci_clear_entry,
|
2007-09-26 02:57:13 +02:00
|
|
|
.set_device_state = rt61pci_set_device_state,
|
|
|
|
.rfkill_poll = rt61pci_rfkill_poll,
|
|
|
|
.link_stats = rt61pci_link_stats,
|
|
|
|
.reset_tuner = rt61pci_reset_tuner,
|
|
|
|
.link_tuner = rt61pci_link_tuner,
|
2010-12-13 12:34:54 +01:00
|
|
|
.start_queue = rt61pci_start_queue,
|
|
|
|
.kick_queue = rt61pci_kick_queue,
|
|
|
|
.stop_queue = rt61pci_stop_queue,
|
2011-04-18 15:31:02 +02:00
|
|
|
.flush_queue = rt2x00pci_flush_queue,
|
2007-09-26 02:57:13 +02:00
|
|
|
.write_tx_desc = rt61pci_write_tx_desc,
|
2008-07-09 15:12:44 +02:00
|
|
|
.write_beacon = rt61pci_write_beacon,
|
2011-01-30 13:16:03 +01:00
|
|
|
.clear_beacon = rt61pci_clear_beacon,
|
2007-09-26 02:57:13 +02:00
|
|
|
.fill_rxdone = rt61pci_fill_rxdone,
|
2008-08-04 16:38:02 +02:00
|
|
|
.config_shared_key = rt61pci_config_shared_key,
|
|
|
|
.config_pairwise_key = rt61pci_config_pairwise_key,
|
2008-03-25 14:13:18 +01:00
|
|
|
.config_filter = rt61pci_config_filter,
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 15:49:59 +01:00
|
|
|
.config_intf = rt61pci_config_intf,
|
2008-03-09 22:46:18 +01:00
|
|
|
.config_erp = rt61pci_config_erp,
|
2008-10-29 17:17:57 +01:00
|
|
|
.config_ant = rt61pci_config_ant,
|
2007-09-26 02:57:13 +02:00
|
|
|
.config = rt61pci_config,
|
|
|
|
};
|
|
|
|
|
2008-02-05 22:42:23 +01:00
|
|
|
static const struct data_queue_desc rt61pci_queue_rx = {
|
2010-11-04 20:37:22 +01:00
|
|
|
.entry_num = 32,
|
2008-02-05 22:42:23 +01:00
|
|
|
.data_size = DATA_FRAME_SIZE,
|
|
|
|
.desc_size = RXD_DESC_SIZE,
|
2008-05-10 13:46:03 +02:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 22:42:23 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct data_queue_desc rt61pci_queue_tx = {
|
2010-11-04 20:37:22 +01:00
|
|
|
.entry_num = 32,
|
2008-02-05 22:42:23 +01:00
|
|
|
.data_size = DATA_FRAME_SIZE,
|
|
|
|
.desc_size = TXD_DESC_SIZE,
|
2008-05-10 13:46:03 +02:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 22:42:23 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct data_queue_desc rt61pci_queue_bcn = {
|
2010-11-04 20:37:22 +01:00
|
|
|
.entry_num = 4,
|
2008-05-05 17:23:31 +02:00
|
|
|
.data_size = 0, /* No DMA required for beacons */
|
2008-02-05 22:42:23 +01:00
|
|
|
.desc_size = TXINFO_SIZE,
|
2008-05-10 13:46:03 +02:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 22:42:23 +01:00
|
|
|
};
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
static const struct rt2x00_ops rt61pci_ops = {
|
2009-11-23 22:44:51 +01:00
|
|
|
.name = KBUILD_MODNAME,
|
|
|
|
.max_ap_intf = 4,
|
|
|
|
.eeprom_size = EEPROM_SIZE,
|
|
|
|
.rf_size = RF_SIZE,
|
|
|
|
.tx_queues = NUM_TX_QUEUES,
|
2009-11-23 22:44:52 +01:00
|
|
|
.extra_tx_headroom = 0,
|
2009-11-23 22:44:51 +01:00
|
|
|
.rx = &rt61pci_queue_rx,
|
|
|
|
.tx = &rt61pci_queue_tx,
|
|
|
|
.bcn = &rt61pci_queue_bcn,
|
|
|
|
.lib = &rt61pci_rt2x00_ops,
|
|
|
|
.hw = &rt61pci_mac80211_ops,
|
2007-09-26 02:57:13 +02:00
|
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
2009-11-23 22:44:51 +01:00
|
|
|
.debugfs = &rt61pci_rt2x00debug,
|
2007-09-26 02:57:13 +02:00
|
|
|
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RT61pci module information.
|
|
|
|
*/
|
2010-01-07 12:58:11 +01:00
|
|
|
static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
|
2007-09-26 02:57:13 +02:00
|
|
|
/* RT2561s */
|
2011-04-18 15:32:13 +02:00
|
|
|
{ PCI_DEVICE(0x1814, 0x0301) },
|
2007-09-26 02:57:13 +02:00
|
|
|
/* RT2561 v2 */
|
2011-04-18 15:32:13 +02:00
|
|
|
{ PCI_DEVICE(0x1814, 0x0302) },
|
2007-09-26 02:57:13 +02:00
|
|
|
/* RT2661 */
|
2011-04-18 15:32:13 +02:00
|
|
|
{ PCI_DEVICE(0x1814, 0x0401) },
|
2007-09-26 02:57:13 +02:00
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_AUTHOR(DRV_PROJECT);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
|
|
|
|
MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
|
|
|
|
"PCI & PCMCIA chipset based cards");
|
|
|
|
MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
|
|
|
|
MODULE_FIRMWARE(FIRMWARE_RT2561);
|
|
|
|
MODULE_FIRMWARE(FIRMWARE_RT2561s);
|
|
|
|
MODULE_FIRMWARE(FIRMWARE_RT2661);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
2011-04-18 15:32:13 +02:00
|
|
|
static int rt61pci_probe(struct pci_dev *pci_dev,
|
|
|
|
const struct pci_device_id *id)
|
|
|
|
{
|
|
|
|
return rt2x00pci_probe(pci_dev, &rt61pci_ops);
|
|
|
|
}
|
|
|
|
|
2007-09-26 02:57:13 +02:00
|
|
|
static struct pci_driver rt61pci_driver = {
|
2007-11-27 21:47:34 +01:00
|
|
|
.name = KBUILD_MODNAME,
|
2007-09-26 02:57:13 +02:00
|
|
|
.id_table = rt61pci_device_table,
|
2011-04-18 15:32:13 +02:00
|
|
|
.probe = rt61pci_probe,
|
2012-12-03 15:56:39 +01:00
|
|
|
.remove = rt2x00pci_remove,
|
2007-09-26 02:57:13 +02:00
|
|
|
.suspend = rt2x00pci_suspend,
|
|
|
|
.resume = rt2x00pci_resume,
|
|
|
|
};
|
|
|
|
|
2012-04-14 04:38:36 +02:00
|
|
|
module_pci_driver(rt61pci_driver);
|