ntb: fix SKX NTB config space size register offsets
The offsets for the SZ registers are wrong. Updated. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reported-by: Sandeep Mann <sandeep@purestorage.com> Tested-by: Zachary Ross <zacharyx.ross@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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@ -152,10 +152,10 @@
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#define XEON_SPAD_COUNT 16
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/* Intel Skylake Xeon hardware */
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#define SKX_IMBAR1SZ_OFFSET 0x00d1
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#define SKX_IMBAR2SZ_OFFSET 0x00d5
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#define SKX_EMBAR1SZ_OFFSET 0x00d3
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#define SKX_EMBAR2SZ_OFFSET 0x00d6
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#define SKX_IMBAR1SZ_OFFSET 0x00d0
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#define SKX_IMBAR2SZ_OFFSET 0x00d1
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#define SKX_EMBAR1SZ_OFFSET 0x00d2
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#define SKX_EMBAR2SZ_OFFSET 0x00d3
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#define SKX_DEVCTRL_OFFSET 0x0098
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#define SKX_DEVSTS_OFFSET 0x009a
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#define SKX_UNCERRSTS_OFFSET 0x014c
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