Merge branch 'u300-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/cleanup
From Linus Walleij <linus.walleij@linaro.org> This patch set does a number of cleanups and a minor improvement to U300, paving the way for single zImage and device tree: - Deprecate ancient platforms to make the following patches easier to make... - Move out one header to platform data and one to the mach-u300 proper to depopulate <mach/*> - Consolidate core machine files - Convert to sparse IRQs * 'u300-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: u300: convert to sparse IRQs ARM: u300: move DMA channel header into mach-u300 ARM: u300: delete remnant clkdev.h file ARM: u300: merge u300.c into core.c and rid headers pinctrl/coh901: move header to platform data dir pinctrl/coh901: retire ancient GPIO block versions ARM: u300: retire ancient platforms Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
63487589bf
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@ -926,6 +926,7 @@ config ARCH_U300
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select COMMON_CLK
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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select SPARSE_IRQ
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help
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Support for ST-Ericsson U300 series mobile platforms.
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@ -1,6 +1,6 @@
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if ARCH_U300
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menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
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menu "ST-Ericsson AB U300/U335 Platform"
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comment "ST-Ericsson Mobile Platform Products"
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@ -10,46 +10,7 @@ config MACH_U300
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select PINCTRL_U300
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select PINCTRL_COH901
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comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
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choice
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prompt "U300/U330/U335/U365 system type"
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default MACH_U300_BS2X
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---help---
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You need to select the target system, i.e. the
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U300/U330/U335/U365 board that you want to compile your kernel
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for.
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config MACH_U300_BS2X
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bool "S26/S26/B25/B26 Test Products"
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depends on MACH_U300
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help
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Select this if you're developing on the
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S26/S25 test products. (Also works on
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B26/B25 big boards.)
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config MACH_U300_BS330
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bool "S330/B330 Test Products"
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depends on MACH_U300
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help
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Select this if you're developing on the
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S330/B330 test products.
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config MACH_U300_BS335
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bool "S335/B335 Test Products"
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depends on MACH_U300
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help
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Select this if you're developing on the
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S335/B335 test products.
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config MACH_U300_BS365
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bool "S365/B365 Test Products"
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depends on MACH_U300
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help
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Select this if you're developing on the
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S365/B365 test products.
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endchoice
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comment "ST-Ericsson U300/U335 Feature Selections"
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config U300_DEBUG
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bool "Debug support for U300"
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@ -7,7 +7,6 @@ obj-m :=
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obj-n :=
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obj- :=
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obj-$(CONFIG_ARCH_U300) += u300.o
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obj-$(CONFIG_SPI_PL022) += spi.o
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obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o
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obj-$(CONFIG_I2C_STU300) += i2c.o
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@ -3,7 +3,7 @@
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* arch/arm/mach-u300/core.c
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*
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*
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* Copyright (C) 2007-2010 ST-Ericsson SA
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* Copyright (C) 2007-2012 ST-Ericsson SA
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* License terms: GNU General Public License (GPL) version 2
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* Core platform support, IRQ handling and device definitions.
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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@ -31,23 +31,26 @@
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_data/clk-u300.h>
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#include <linux/platform_data/pinctrl-coh901.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/coh901318.h>
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#include <mach/hardware.h>
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#include <mach/syscon.h>
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#include <mach/dma_channels.h>
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#include <mach/gpio-u300.h>
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#include <mach/irqs.h>
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#include "timer.h"
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#include "spi.h"
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#include "i2c.h"
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#include "u300-gpio.h"
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#include "dma_channels.h"
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/*
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* Static I/O mappings that are needed for booting the U300 platforms. The
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@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
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},
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};
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void __init u300_map_io(void)
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static void __init u300_map_io(void)
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{
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iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
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/* We enable a real big DMA buffer if need be. */
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@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
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{ IRQ_U300_UART0 }, &uart0_plat_data);
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/* The U335 have an additional UART1 on the APP CPU */
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#ifdef CONFIG_MACH_U300_BS335
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static struct amba_pl011_data uart1_plat_data = {
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#ifdef CONFIG_COH901318
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.dma_filter = coh901318_filter_id,
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@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = {
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/* Fast device at 0x7000 offset */
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static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
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{ IRQ_U300_UART1 }, &uart1_plat_data);
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#endif
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/* AHB device at 0x4000 offset */
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static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
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@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
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*/
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static struct amba_device *amba_devs[] __initdata = {
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&uart0_device,
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#ifdef CONFIG_MACH_U300_BS335
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&uart1_device,
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#endif
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&pl022_device,
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&pl172_device,
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&mmcsd_device,
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@ -188,7 +187,6 @@ static struct resource gpio_resources[] = {
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.end = IRQ_U300_GPIO_PORT2,
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.flags = IORESOURCE_IRQ,
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},
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#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
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{
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.name = "gpio3",
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.start = IRQ_U300_GPIO_PORT3,
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@ -201,8 +199,6 @@ static struct resource gpio_resources[] = {
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.end = IRQ_U300_GPIO_PORT4,
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.flags = IORESOURCE_IRQ,
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},
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#endif
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#ifdef CONFIG_MACH_U300_BS335
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{
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.name = "gpio5",
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.start = IRQ_U300_GPIO_PORT5,
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@ -215,7 +211,6 @@ static struct resource gpio_resources[] = {
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.end = IRQ_U300_GPIO_PORT6,
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.flags = IORESOURCE_IRQ,
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},
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#endif /* CONFIG_MACH_U300_BS335 */
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};
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static struct resource keypad_resources[] = {
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@ -323,7 +318,6 @@ static struct resource dma_resource[] = {
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}
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};
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#ifdef CONFIG_MACH_U300_BS335
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/* points out all dma slave channels.
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* Syntax is [A1, B1, A2, B2, .... ,-1,-1]
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* Select all channels from A to B, end of list is marked with -1,-1
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@ -336,14 +330,6 @@ static int dma_slave_channels[] = {
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static int dma_memcpy_channels[] = {
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U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
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#else /* CONFIG_MACH_U300_BS335 */
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static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
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static int dma_memcpy_channels[] = {
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U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
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#endif
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/** register dma for memory access
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*
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* active 1 means dma intends to access memory
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@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.param.ctrl_lli = flags_memcpy_lli,
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.param.ctrl_lli_last = flags_memcpy_lli_last,
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},
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#ifdef CONFIG_MACH_U300_BS335
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{
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.number = U300_DMA_UART1_TX,
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.name = "UART1 TX",
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@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.name = "UART1 RX",
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.priority_high = 0,
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}
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#else
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{
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.number = U300_DMA_GENERAL_PURPOSE_9,
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.name = "GENERAL 09",
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.priority_high = 0,
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.param.config = flags_memcpy_config,
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.param.ctrl_lli_chained = flags_memcpy_lli_chained,
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.param.ctrl_lli = flags_memcpy_lli,
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.param.ctrl_lli_last = flags_memcpy_lli_last,
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},
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{
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.number = U300_DMA_GENERAL_PURPOSE_10,
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.name = "GENERAL 10",
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.priority_high = 0,
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.param.config = flags_memcpy_config,
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.param.ctrl_lli_chained = flags_memcpy_lli_chained,
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.param.ctrl_lli = flags_memcpy_lli,
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.param.ctrl_lli_last = flags_memcpy_lli_last,
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}
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#endif
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};
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@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = {
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* GPIO block, with different number of ports.
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*/
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static struct u300_gpio_platform u300_gpio_plat = {
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#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
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.variant = U300_GPIO_COH901335,
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.ports = 3,
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#endif
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#ifdef CONFIG_MACH_U300_BS335
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.variant = U300_GPIO_COH901571_3_BS335,
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.ports = 7,
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#endif
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#ifdef CONFIG_MACH_U300_BS365
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.variant = U300_GPIO_COH901571_3_BS365,
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.ports = 5,
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#endif
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.gpio_base = 0,
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.gpio_irq_base = IRQ_U300_GPIO_BASE,
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.pinctrl_device = &pinctrl_device,
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@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = {
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* together so some interrupts are connected to the first one and some
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* to the second one.
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*/
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void __init u300_init_irq(void)
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static void __init u300_init_irq(void)
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{
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u32 mask[2] = {0, 0};
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struct clk *clk;
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|
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@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void)
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printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
|
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"(chip ID 0x%04x)\n", chipname, val);
|
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|
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#ifdef CONFIG_MACH_U300_BS330
|
||||
if ((val & 0xFF00U) != 0xd800) {
|
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printk(KERN_ERR "Platform configured for BS330 " \
|
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"with DB3200 but %s detected, expect problems!",
|
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chipname);
|
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}
|
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#endif
|
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#ifdef CONFIG_MACH_U300_BS335
|
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if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
|
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printk(KERN_ERR "Platform configured for BS335 " \
|
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" with DB3350 but %s detected, expect problems!",
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chipname);
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}
|
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#endif
|
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#ifdef CONFIG_MACH_U300_BS365
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if ((val & 0xFF00U) != 0xe800) {
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printk(KERN_ERR "Platform configured for BS365 " \
|
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"with DB3210 but %s detected, expect problems!",
|
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chipname);
|
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}
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#endif
|
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|
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|
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}
|
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|
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/*
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|
|
@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void)
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}
|
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}
|
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void __init u300_init_devices(void)
|
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static void __init u300_init_machine(void)
|
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{
|
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int i;
|
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u16 val;
|
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|
|
@ -1852,7 +1786,7 @@ void __init u300_init_devices(void)
|
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/* Forward declare this function from the watchdog */
|
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void coh901327_watchdog_reset(void);
|
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|
||||
void u300_restart(char mode, const char *cmd)
|
||||
static void u300_restart(char mode, const char *cmd)
|
||||
{
|
||||
switch (mode) {
|
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case 's':
|
||||
|
|
@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd)
|
|||
/* Wait for system do die/reset. */
|
||||
while (1);
|
||||
}
|
||||
|
||||
MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
|
||||
/* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
|
||||
.atag_offset = 0x100,
|
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.map_io = u300_map_io,
|
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.nr_irqs = NR_IRQS_U300,
|
||||
.init_irq = u300_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &u300_timer,
|
||||
.init_machine = u300_init_machine,
|
||||
.restart = u300_restart,
|
||||
MACHINE_END
|
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|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* arch/arm/mach-u300/include/mach/dma_channels.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* Copyright (C) 2007-2012 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Map file for the U300 dma driver.
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
|
|
@ -50,19 +50,10 @@
|
|||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
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#define U300_DMA_GENERAL_PURPOSE_7 36
|
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#define U300_DMA_GENERAL_PURPOSE_8 37
|
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#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_DMA_UART1_TX 38
|
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#define U300_DMA_UART1_RX 39
|
||||
#else
|
||||
#define U300_DMA_GENERAL_PURPOSE_9 38
|
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#define U300_DMA_GENERAL_PURPOSE_10 39
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#else
|
||||
#define U300_DMA_DEVICE_CHANNELS 30
|
||||
#endif
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* arch/arm/mach-u300/i2c.c
|
||||
*
|
||||
* Copyright (C) 2009 ST-Ericsson AB
|
||||
* Copyright (C) 2009-2012 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*
|
||||
* Register board i2c devices
|
||||
|
|
@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
|
|||
};
|
||||
|
||||
static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
{
|
||||
.type = "fwcam",
|
||||
.addr = 0x10,
|
||||
|
|
@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
|
|||
.type = "fwcam",
|
||||
.addr = 0x5d,
|
||||
},
|
||||
#else
|
||||
{ },
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init u300_i2c_register_board_devices(void)
|
||||
|
|
|
|||
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef __MACH_CLKDEV_H
|
||||
#define __MACH_CLKDEV_H
|
||||
|
||||
int __clk_get(struct clk *clk);
|
||||
void __clk_put(struct clk *clk);
|
||||
|
||||
#endif
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* arch/arm/mach-u300/include/mach/irqs.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2006-2009 ST-Ericsson AB
|
||||
* Copyright (C) 2006-2012 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* IRQ channel definitions for the U300 platforms.
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
|
|
@ -31,10 +31,6 @@
|
|||
#define IRQ_U300_XGAM_GAMCON 14
|
||||
#define IRQ_U300_XGAM_CDI 15
|
||||
#define IRQ_U300_XGAM_CDICON 16
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
/* MMIACC not used on the DB3210 or DB3350 chips */
|
||||
#define IRQ_U300_XGAM_MMIACC 17
|
||||
#endif
|
||||
#define IRQ_U300_XGAM_PDI 18
|
||||
#define IRQ_U300_XGAM_PDICON 19
|
||||
#define IRQ_U300_XGAM_GAMEACC 20
|
||||
|
|
@ -55,8 +51,6 @@
|
|||
#define IRQ_U300_GPIO_PORT1 34
|
||||
#define IRQ_U300_GPIO_PORT2 35
|
||||
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
|
||||
defined(CONFIG_MACH_U300_BS335)
|
||||
/* These are for DB3150, DB3200 and DB3350 */
|
||||
#define IRQ_U300_WDOG 36
|
||||
#define IRQ_U300_EVHIST 37
|
||||
|
|
@ -68,15 +62,8 @@
|
|||
#define IRQ_U300_RTC 43
|
||||
#define IRQ_U300_NFIF 44
|
||||
#define IRQ_U300_NFIF2 45
|
||||
#endif
|
||||
|
||||
/* DB3150 and DB3200 have only 45 IRQs */
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
#define U300_VIC_IRQS_END 46
|
||||
#endif
|
||||
|
||||
/* The DB3350-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define IRQ_U300_ISP_F0 46
|
||||
#define IRQ_U300_ISP_F1 47
|
||||
#define IRQ_U300_ISP_F2 48
|
||||
|
|
@ -89,25 +76,6 @@
|
|||
#define IRQ_U300_GPIO_PORT5 55
|
||||
#define IRQ_U300_GPIO_PORT6 56
|
||||
#define U300_VIC_IRQS_END 57
|
||||
#endif
|
||||
|
||||
/* The DB3210-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS365
|
||||
#define IRQ_U300_GPIO_PORT3 36
|
||||
#define IRQ_U300_GPIO_PORT4 37
|
||||
#define IRQ_U300_WDOG 38
|
||||
#define IRQ_U300_EVHIST 39
|
||||
#define IRQ_U300_MSPRO 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 41
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 42
|
||||
#define IRQ_U300_I2C0 43
|
||||
#define IRQ_U300_I2C1 44
|
||||
#define IRQ_U300_RTC 45
|
||||
#define IRQ_U300_NFIF 46
|
||||
#define IRQ_U300_NFIF2 47
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 48
|
||||
#define U300_VIC_IRQS_END 49
|
||||
#endif
|
||||
|
||||
/* Maximum 8*7 GPIO lines */
|
||||
#ifdef CONFIG_PINCTRL_COH901
|
||||
|
|
@ -117,6 +85,6 @@
|
|||
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
|
||||
#define NR_IRQS_U300 (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* arch/arm/mach-u300/include/mach/platform.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2006-2009 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Basic platform init and mapping functions.
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
void u300_map_io(void);
|
||||
void u300_init_irq(void);
|
||||
void u300_init_devices(void);
|
||||
void u300_restart(char, const char *);
|
||||
extern struct sys_timer u300_timer;
|
||||
|
||||
#endif
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* arch/arm/mach-u300/include/mach/syscon.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2008 ST-Ericsson AB
|
||||
* Copyright (C) 2008-2012 ST-Ericsson AB
|
||||
*
|
||||
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
|
||||
*/
|
||||
|
|
@ -36,9 +36,7 @@
|
|||
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
|
||||
/* Reset lines for SLOW devices 16bit (R/W) */
|
||||
#define U300_SYSCON_RSR (0x0014)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
|
||||
#endif
|
||||
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
|
||||
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
|
||||
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
|
||||
|
|
@ -50,9 +48,7 @@
|
|||
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
|
||||
/* Reset lines for FAST devices 16bit (R/W) */
|
||||
#define U300_SYSCON_RFR (0x0018)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
|
||||
#endif
|
||||
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
|
||||
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
|
||||
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
|
||||
|
|
@ -62,10 +58,8 @@
|
|||
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
|
||||
/* Reset lines for the rest of the peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_RRR (0x001c)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
|
||||
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
|
||||
#endif
|
||||
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
|
||||
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
|
||||
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
|
||||
|
|
@ -79,9 +73,7 @@
|
|||
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
|
||||
/* Clock enable for SLOW peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_CESR (0x0020)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
|
||||
#endif
|
||||
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
|
||||
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
|
||||
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
|
||||
|
|
@ -92,24 +84,20 @@
|
|||
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
|
||||
/* Clock enable for FAST peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_CEFR (0x0024)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
|
||||
#endif
|
||||
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
|
||||
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
|
||||
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
|
||||
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
|
||||
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
|
||||
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
|
||||
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
|
||||
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
|
||||
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
|
||||
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
|
||||
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
|
||||
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
|
||||
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
|
||||
/* Clock enable for the rest of the peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_CERR (0x0028)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
|
||||
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
|
||||
#endif
|
||||
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
|
||||
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
|
||||
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
|
||||
|
|
@ -124,9 +112,7 @@
|
|||
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
|
||||
/* Single block clock enable 16bit (-/W) */
|
||||
#define U300_SYSCON_SBCER (0x002c)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
|
||||
#endif
|
||||
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
|
||||
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
|
||||
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
|
||||
|
|
@ -135,9 +121,7 @@
|
|||
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
|
||||
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
|
||||
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
|
||||
#endif
|
||||
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
|
||||
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
|
||||
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
|
||||
|
|
@ -147,10 +131,8 @@
|
|||
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
|
||||
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
|
||||
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
|
||||
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
|
||||
#endif
|
||||
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
|
||||
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
|
||||
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
|
||||
|
|
@ -168,9 +150,7 @@
|
|||
/* Same values as above for SBCER */
|
||||
/* Clock force SLOW peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_CFSR (0x003c)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
|
||||
#endif
|
||||
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
|
||||
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
|
||||
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
|
||||
|
|
@ -184,10 +164,8 @@
|
|||
/* Values not defined. Define if you want to use them. */
|
||||
/* Clock force the rest of the peripherals 16bit (R/W) */
|
||||
#define U300_SYSCON_CFRR (0x44)
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
|
||||
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
|
||||
#endif
|
||||
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
|
||||
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
|
||||
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
#define PLAT_NAND_CLE (1 << 16)
|
||||
#define PLAT_NAND_ALE (1 << 17)
|
||||
|
||||
|
||||
/* AHB Peripherals */
|
||||
#define U300_AHB_PER_PHYS_BASE 0xa0000000
|
||||
#define U300_AHB_PER_VIRT_BASE 0xff010000
|
||||
|
|
@ -46,11 +45,7 @@
|
|||
#define U300_BOOTROM_VIRT_BASE 0xffff0000
|
||||
|
||||
/* SEMI config base */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
|
||||
#else
|
||||
#define U300_SEMI_CONFIG_BASE 0x30000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AHB peripherals
|
||||
|
|
@ -99,10 +94,8 @@
|
|||
/* SPI controller */
|
||||
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
/* Fast UART1 on U335 only */
|
||||
#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SLOW peripherals
|
||||
|
|
@ -151,10 +144,8 @@
|
|||
* REST peripherals
|
||||
*/
|
||||
|
||||
/* ISP (image signal processor) is only available in U335 */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
/* ISP (image signal processor) */
|
||||
#define U300_ISP_BASE (0xA0008000)
|
||||
#endif
|
||||
|
||||
/* DMA Controller base */
|
||||
#define U300_DMAC_BASE (0xC0020000)
|
||||
|
|
@ -166,17 +157,9 @@
|
|||
#define U300_APEX_BASE (0xc0030000)
|
||||
|
||||
/* Video Encoder Base */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define U300_VIDEOENC_BASE (0xc0080000)
|
||||
#else
|
||||
#define U300_VIDEOENC_BASE (0xc0040000)
|
||||
#endif
|
||||
|
||||
/* XGAM Base */
|
||||
#define U300_XGAM_BASE (0xd0000000)
|
||||
|
||||
/*
|
||||
* Virtual accessor macros for static devices
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
#include <linux/amba/pl022.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include <mach/dma_channels.h>
|
||||
#include "dma_channels.h"
|
||||
|
||||
/*
|
||||
* The following is for the actual devices on the SSP/SPI bus
|
||||
|
|
|
|||
|
|
@ -17,14 +17,17 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/* Generic stuff */
|
||||
#include <asm/sched_clock.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "timer.h"
|
||||
|
||||
/*
|
||||
* APP side special timer registers
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
extern struct sys_timer u300_timer;
|
||||
|
|
@ -1,50 +1,11 @@
|
|||
/*
|
||||
* Individual pin assignments for the B26/S26. Notice that the
|
||||
* actual usage of these pins depends on the PAD MUX settings, that
|
||||
* is why the same number can potentially appear several times.
|
||||
* In the reference design each pin is only used for one purpose.
|
||||
* These were determined by inspecting the B26/S26 schematic:
|
||||
* 2/1911-ROA 128 1603
|
||||
*/
|
||||
#ifdef CONFIG_MACH_U300_BS2X
|
||||
#define U300_GPIO_PIN_UART_RX 0
|
||||
#define U300_GPIO_PIN_UART_TX 1
|
||||
#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
|
||||
#define U300_GPIO_PIN_CAM_SLEEP 4
|
||||
#define U300_GPIO_PIN_CAM_REG_EN 5
|
||||
#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
|
||||
|
||||
#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
|
||||
#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
|
||||
#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
|
||||
#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
|
||||
#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
|
||||
#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
|
||||
#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
|
||||
#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
|
||||
|
||||
#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Individual pin assignments for the B330/S330 and B365/S365.
|
||||
* Individual pin assignments for the B335/S335.
|
||||
* Notice that the actual usage of these pins depends on the
|
||||
* PAD MUX settings, that is why the same number can potentially
|
||||
* appear several times. In the reference design each pin is only
|
||||
* used for one purpose. These were determined by inspecting the
|
||||
* S365 schematic.
|
||||
*/
|
||||
#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
|
||||
defined(CONFIG_MACH_U300_BS335)
|
||||
#define U300_GPIO_PIN_UART_RX 0
|
||||
#define U300_GPIO_PIN_UART_TX 1
|
||||
#define U300_GPIO_PIN_UART_CTS 2
|
||||
|
|
@ -90,8 +51,6 @@
|
|||
#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
|
||||
#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
|
||||
|
|
@ -109,6 +68,3 @@
|
|||
#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
|
||||
#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,57 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* arch/arm/mach-u300/u300.c
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2006-2009 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Platform machine definition.
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
static void __init u300_init_machine(void)
|
||||
{
|
||||
u300_init_devices();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS2X
|
||||
#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS330
|
||||
#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_U300_BS365
|
||||
#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
|
||||
#endif
|
||||
|
||||
MACHINE_START(U300, MACH_U300_STRING)
|
||||
/* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = u300_map_io,
|
||||
.init_irq = u300_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &u300_timer,
|
||||
.init_machine = u300_init_machine,
|
||||
.restart = u300_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -1,11 +1,8 @@
|
|||
/*
|
||||
* U300 GPIO module.
|
||||
*
|
||||
* Copyright (C) 2007-2011 ST-Ericsson AB
|
||||
* Copyright (C) 2007-2012 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* This can driver either of the two basic GPIO cores
|
||||
* available in the U300 platforms:
|
||||
* COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
|
||||
* COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
|
||||
* Author: Linus Walleij <linus.walleij@linaro.org>
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
|
||||
|
|
@ -24,19 +21,22 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <mach/gpio-u300.h>
|
||||
#include <linux/platform_data/pinctrl-coh901.h>
|
||||
#include "pinctrl-coh901.h"
|
||||
|
||||
#define U300_GPIO_PORT_STRIDE (0x30)
|
||||
/*
|
||||
* Register definitions for COH 901 335 variant
|
||||
* Control Register 32bit (R/W)
|
||||
* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
|
||||
* gives the number of GPIO pins.
|
||||
* bit 8-2 (mask 0x000001FC) contains the core version ID.
|
||||
*/
|
||||
#define U300_335_PORT_STRIDE (0x1C)
|
||||
/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
|
||||
#define U300_335_PXPDIR (0x00)
|
||||
#define U300_335_PXPDOR (0x00)
|
||||
/* Port X Pin Config Register 32bit (R/W) */
|
||||
#define U300_335_PXPCR (0x04)
|
||||
/* This register layout is the same in both blocks */
|
||||
#define U300_GPIO_CR (0x00)
|
||||
#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
|
||||
#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
|
||||
#define U300_GPIO_PXPDIR (0x04)
|
||||
#define U300_GPIO_PXPDOR (0x08)
|
||||
#define U300_GPIO_PXPCR (0x0C)
|
||||
#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
|
||||
#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
|
||||
#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
|
||||
|
|
@ -44,53 +44,17 @@
|
|||
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
|
||||
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
|
||||
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
|
||||
/* Port X Interrupt Event Register 32bit (R/W) */
|
||||
#define U300_335_PXIEV (0x08)
|
||||
/* Port X Interrupt Enable Register 32bit (R/W) */
|
||||
#define U300_335_PXIEN (0x0C)
|
||||
/* Port X Interrupt Force Register 32bit (R/W) */
|
||||
#define U300_335_PXIFR (0x10)
|
||||
/* Port X Interrupt Config Register 32bit (R/W) */
|
||||
#define U300_335_PXICR (0x14)
|
||||
/* This register layout is the same in both blocks */
|
||||
#define U300_GPIO_PXPER (0x10)
|
||||
#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
|
||||
#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
|
||||
#define U300_GPIO_PXIEV (0x14)
|
||||
#define U300_GPIO_PXIEN (0x18)
|
||||
#define U300_GPIO_PXIFR (0x1C)
|
||||
#define U300_GPIO_PXICR (0x20)
|
||||
#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
|
||||
#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
|
||||
#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
|
||||
#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
|
||||
/* Port X Pull-up Enable Register 32bit (R/W) */
|
||||
#define U300_335_PXPER (0x18)
|
||||
/* This register layout is the same in both blocks */
|
||||
#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
|
||||
#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
|
||||
/* Control Register 32bit (R/W) */
|
||||
#define U300_335_CR (0x54)
|
||||
#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
|
||||
|
||||
/*
|
||||
* Register definitions for COH 901 571 / 3 variant
|
||||
*/
|
||||
#define U300_571_PORT_STRIDE (0x30)
|
||||
/*
|
||||
* Control Register 32bit (R/W)
|
||||
* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
|
||||
* gives the number of GPIO pins.
|
||||
* bit 8-2 (mask 0x000001FC) contains the core version ID.
|
||||
*/
|
||||
#define U300_571_CR (0x00)
|
||||
#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
|
||||
#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
|
||||
/*
|
||||
* These registers have the same layout and function as the corresponding
|
||||
* COH 901 335 registers, just at different offset.
|
||||
*/
|
||||
#define U300_571_PXPDIR (0x04)
|
||||
#define U300_571_PXPDOR (0x08)
|
||||
#define U300_571_PXPCR (0x0C)
|
||||
#define U300_571_PXPER (0x10)
|
||||
#define U300_571_PXIEV (0x14)
|
||||
#define U300_571_PXIEN (0x18)
|
||||
#define U300_571_PXIFR (0x1C)
|
||||
#define U300_571_PXICR (0x20)
|
||||
|
||||
/* 8 bits per port, no version has more than 7 ports */
|
||||
#define U300_GPIO_PINS_PER_PORT 8
|
||||
|
|
@ -149,8 +113,6 @@ struct u300_gpio_confdata {
|
|||
|
||||
/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
|
||||
#define BS335_GPIO_NUM_PORTS 7
|
||||
/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
|
||||
#define BS365_GPIO_NUM_PORTS 5
|
||||
|
||||
#define U300_FLOATING_INPUT { \
|
||||
.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
|
||||
|
|
@ -172,7 +134,6 @@ struct u300_gpio_confdata {
|
|||
.outval = 1, \
|
||||
}
|
||||
|
||||
|
||||
/* Initial configuration */
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
|
|
@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
|||
}
|
||||
};
|
||||
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
/* Port 0, pins 0-7 */
|
||||
{
|
||||
U300_FLOATING_INPUT,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_FLOATING_INPUT,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_FLOATING_INPUT,
|
||||
},
|
||||
/* Port 1, pins 0-7 */
|
||||
{
|
||||
U300_OUTPUT_LOW,
|
||||
U300_FLOATING_INPUT,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_FLOATING_INPUT,
|
||||
U300_FLOATING_INPUT,
|
||||
U300_OUTPUT_HIGH,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
},
|
||||
/* Port 2, pins 0-7 */
|
||||
{
|
||||
U300_FLOATING_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
},
|
||||
/* Port 3, pins 0-7 */
|
||||
{
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
},
|
||||
/* Port 4, pins 0-7 */
|
||||
{
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
U300_PULL_UP_INPUT,
|
||||
/* These 4 pins doesn't exist on DB3210 */
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
U300_OUTPUT_LOW,
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* to_u300_gpio() - get the pointer to u300_gpio
|
||||
* @chip: the gpio chip member of the structure u300_gpio
|
||||
|
|
@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
|
|||
const struct u300_gpio_confdata *conf;
|
||||
int offset = (i*8) + j;
|
||||
|
||||
if (plat->variant == U300_GPIO_COH901571_3_BS335)
|
||||
conf = &bs335_gpio_config[i][j];
|
||||
else if (plat->variant == U300_GPIO_COH901571_3_BS365)
|
||||
conf = &bs365_gpio_config[i][j];
|
||||
else
|
||||
break;
|
||||
|
||||
conf = &bs335_gpio_config[i][j];
|
||||
u300_gpio_init_pin(gpio, offset, conf);
|
||||
}
|
||||
}
|
||||
|
|
@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
|
|||
goto err_no_ioremap;
|
||||
}
|
||||
|
||||
if (plat->variant == U300_GPIO_COH901335) {
|
||||
dev_info(gpio->dev,
|
||||
"initializing GPIO Controller COH 901 335\n");
|
||||
gpio->stride = U300_335_PORT_STRIDE;
|
||||
gpio->pcr = U300_335_PXPCR;
|
||||
gpio->dor = U300_335_PXPDOR;
|
||||
gpio->dir = U300_335_PXPDIR;
|
||||
gpio->per = U300_335_PXPER;
|
||||
gpio->icr = U300_335_PXICR;
|
||||
gpio->ien = U300_335_PXIEN;
|
||||
gpio->iev = U300_335_PXIEV;
|
||||
ifr = U300_335_PXIFR;
|
||||
dev_info(gpio->dev,
|
||||
"initializing GPIO Controller COH 901 571/3\n");
|
||||
gpio->stride = U300_GPIO_PORT_STRIDE;
|
||||
gpio->pcr = U300_GPIO_PXPCR;
|
||||
gpio->dor = U300_GPIO_PXPDOR;
|
||||
gpio->dir = U300_GPIO_PXPDIR;
|
||||
gpio->per = U300_GPIO_PXPER;
|
||||
gpio->icr = U300_GPIO_PXICR;
|
||||
gpio->ien = U300_GPIO_PXIEN;
|
||||
gpio->iev = U300_GPIO_PXIEV;
|
||||
ifr = U300_GPIO_PXIFR;
|
||||
|
||||
/* Turn on the GPIO block */
|
||||
writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
|
||||
gpio->base + U300_335_CR);
|
||||
} else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
|
||||
plat->variant == U300_GPIO_COH901571_3_BS365) {
|
||||
dev_info(gpio->dev,
|
||||
"initializing GPIO Controller COH 901 571/3\n");
|
||||
gpio->stride = U300_571_PORT_STRIDE;
|
||||
gpio->pcr = U300_571_PXPCR;
|
||||
gpio->dor = U300_571_PXPDOR;
|
||||
gpio->dir = U300_571_PXPDIR;
|
||||
gpio->per = U300_571_PXPER;
|
||||
gpio->icr = U300_571_PXICR;
|
||||
gpio->ien = U300_571_PXIEN;
|
||||
gpio->iev = U300_571_PXIEV;
|
||||
ifr = U300_571_PXIFR;
|
||||
|
||||
val = readl(gpio->base + U300_571_CR);
|
||||
dev_info(gpio->dev, "COH901571/3 block version: %d, " \
|
||||
"number of cores: %d totalling %d pins\n",
|
||||
((val & 0x000001FC) >> 2),
|
||||
((val & 0x0000FE00) >> 9),
|
||||
((val & 0x0000FE00) >> 9) * 8);
|
||||
writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
|
||||
gpio->base + U300_571_CR);
|
||||
u300_gpio_init_coh901571(gpio, plat);
|
||||
} else {
|
||||
dev_err(gpio->dev, "unknown block variant\n");
|
||||
err = -ENODEV;
|
||||
goto err_unknown_variant;
|
||||
}
|
||||
val = readl(gpio->base + U300_GPIO_CR);
|
||||
dev_info(gpio->dev, "COH901571/3 block version: %d, " \
|
||||
"number of cores: %d totalling %d pins\n",
|
||||
((val & 0x000001FC) >> 2),
|
||||
((val & 0x0000FE00) >> 9),
|
||||
((val & 0x0000FE00) >> 9) * 8);
|
||||
writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
|
||||
gpio->base + U300_GPIO_CR);
|
||||
u300_gpio_init_coh901571(gpio, plat);
|
||||
|
||||
/* Add each port with its IRQ separately */
|
||||
INIT_LIST_HEAD(&gpio->port_list);
|
||||
|
|
@ -906,7 +778,6 @@ err_no_pinctrl:
|
|||
err_no_chip:
|
||||
err_no_port:
|
||||
u300_gpio_free_ports(gpio);
|
||||
err_unknown_variant:
|
||||
iounmap(gpio->base);
|
||||
err_no_ioremap:
|
||||
release_mem_region(gpio->memres->start, resource_size(gpio->memres));
|
||||
|
|
@ -923,16 +794,11 @@ err_no_clk:
|
|||
|
||||
static int __exit u300_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
|
||||
struct u300_gpio *gpio = platform_get_drvdata(pdev);
|
||||
int err;
|
||||
|
||||
/* Turn off the GPIO block */
|
||||
if (plat->variant == U300_GPIO_COH901335)
|
||||
writel(0x00000000U, gpio->base + U300_335_CR);
|
||||
if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
|
||||
plat->variant == U300_GPIO_COH901571_3_BS365)
|
||||
writel(0x00000000U, gpio->base + U300_571_CR);
|
||||
writel(0x00000000U, gpio->base + U300_GPIO_CR);
|
||||
|
||||
err = gpiochip_remove(&gpio->chip);
|
||||
if (err < 0) {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2007-2011 ST-Ericsson AB
|
||||
* Copyright (C) 2007-2012 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* GPIO block resgister definitions and inline macros for
|
||||
* U300 GPIO COH 901 335 or COH 901 571/3
|
||||
|
|
@ -9,25 +9,14 @@
|
|||
#ifndef __MACH_U300_GPIO_U300_H
|
||||
#define __MACH_U300_GPIO_U300_H
|
||||
|
||||
/**
|
||||
* enum u300_gpio_variant - the type of U300 GPIO employed
|
||||
*/
|
||||
enum u300_gpio_variant {
|
||||
U300_GPIO_COH901335,
|
||||
U300_GPIO_COH901571_3_BS335,
|
||||
U300_GPIO_COH901571_3_BS365,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct u300_gpio_platform - U300 GPIO platform data
|
||||
* @variant: IP block variant
|
||||
* @ports: number of GPIO block ports
|
||||
* @gpio_base: first GPIO number for this block (use a free range)
|
||||
* @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
|
||||
* @pinctrl_device: pin control device to spawn as child
|
||||
*/
|
||||
struct u300_gpio_platform {
|
||||
enum u300_gpio_variant variant;
|
||||
u8 ports;
|
||||
int gpio_base;
|
||||
int gpio_irq_base;
|
||||
Loading…
Reference in New Issue