ath9k_hw: move LowPower array writes to ar9003_hw_configpcipowersave()
The LowPower array writes disables the PLL when ASPM is enabled. The host driver makes quite a few calls to ath9k_hw_configpcipowersave() and these same calls also need to ensure the PLL is off when they issue it. Cc: Aeolus Yang <aeolus.yang@atheros.com> Cc: Madhan Jaganathan <madhan.jaganathan@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -298,6 +298,20 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
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else
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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}
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/*
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* Configire PCIE after Ini init. SERDES values now come from ini file
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* This enables PCIe low power mode.
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*/
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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unsigned int i;
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for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
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REG_WRITE(ah,
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INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
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INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
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}
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}
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}
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/* Sets up the AR9003 hardware familiy callbacks */
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@ -570,20 +570,6 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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ath9k_hw_init_mode_regs(ah);
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/*
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* Configire PCIE after Ini init. SERDES values now come from ini file
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* This enables PCIe low power mode.
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*/
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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unsigned int i;
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for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
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REG_WRITE(ah,
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INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
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INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
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}
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}
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/*
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* Read back AR_WA into a permanent copy and set bits 14 and 17.
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* We need to do this to avoid RMW of this register. We cannot
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