Fixes for ARM and aarch64.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.13 (GNU/Linux) iQIcBAABAgAGBQJSEoS0AAoJEBvWZb6bTYbyE/8P/izUr1XtKBqtVuqVBMewEkeB SBgvJ2w681f4d+1waVAEPqWVGKHDvSOQC54sG6Y3fWHKijKGLiQhLaY3Y1WaLlO1 B+duREwCwHaApjrpYoKhkyGQVpgyIfHBVe8d2TM9Q2bRuYNZEEcOtfdXk+Qfr6WR 2kN+67ivJzAXvjs0uuRyJtXXq9cemcOnngsAfBlJz+j6UbiEdQ3l569D3wQU1jS2 lUxxCEdtBDKDXkJUbTYvtJNYR48caqVXhYBTjpmY04207iSHmacUytOXO3rRA3OL fFhm/QeKVZND0XrJDUOMFzosWdUVdP5Qd5PtYoV/gEydNJMMpPs+dFKv+RXzrWlm 2S2PWbFlkFT8yM+xwh6uKnLQ1aj614dkK2vKlp9GwDuwWiaod71C8ouTJvanNHGt pWgktFlfD+npSc3QDeXG5QB78pTSeyJfZBeVvA+U/etX+vjdfFWZ3bHMScrAE4DX xsdvtfamo0m9v2yZsnKzRWtCQq9No5FRb/c31w7yUzSXNBtyNR0Vft9gmiLo4HYa FQ0wC2UPyaKbfYtX0orpWnN3u4vaylGw2HuzK+2Mwi2HL+AMI6Piu//nrTbqb/i+ 1a6OARWvv9BQdbcuzBqznUdcllbmRl94kA5zXPvAz0dOBPQFU4X/t6dkxxH+8JFj mA/c2PHEyOtuFDOoqZxE =RlHG -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm fixes from Paolo Bonzini: "Fixes for ARM and aarch64. This pull request is coming a bit later than I would have preferred, because I and Gleb happened to have holidays around the same weeks of August... sorry about that" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: ARM: Squash len warning arm64: KVM: use 'int' instead of 'u32' for variable 'target' in kvm_host.h. arm64: KVM: add missing dsb before invalidating Stage-2 TLBs arm64: KVM: perform save/restore of PAR_EL1 arm64: KVM: fix 2-level page tables unmapping ARM: KVM: Fix unaligned unmap_range leak ARM: KVM: Fix 64-bit coprocessor handling
This commit is contained in:
Linus Torvalds
commit
69bbe136a9
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@ -146,7 +146,11 @@ static bool pm_fake(struct kvm_vcpu *vcpu,
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#define access_pmintenclr pm_fake
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/* Architected CP15 registers.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2
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* CRn denotes the primary register number, but is copied to the CRm in the
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* user space API for 64-bit register access in line with the terminology used
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* in the ARM ARM.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
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* registers preceding 32-bit ones.
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*/
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static const struct coproc_reg cp15_regs[] = {
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/* CSSELR: swapped by interrupt.S. */
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@ -154,8 +158,8 @@ static const struct coproc_reg cp15_regs[] = {
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NULL, reset_unknown, c0_CSSELR },
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/* TTBR0/TTBR1: swapped by interrupt.S. */
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{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
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{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
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{ CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
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{ CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
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/* TTBCR: swapped by interrupt.S. */
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{ CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
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@ -182,7 +186,7 @@ static const struct coproc_reg cp15_regs[] = {
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NULL, reset_unknown, c6_IFAR },
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/* PAR swapped by interrupt.S */
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{ CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
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{ CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
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/*
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* DC{C,I,CI}SW operations:
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@ -399,12 +403,13 @@ static bool index_to_params(u64 id, struct coproc_params *params)
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| KVM_REG_ARM_OPC1_MASK))
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return false;
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params->is_64bit = true;
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params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
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/* CRm to CRn: see cp15_to_index for details */
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params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
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>> KVM_REG_ARM_CRM_SHIFT);
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params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
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>> KVM_REG_ARM_OPC1_SHIFT);
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params->Op2 = 0;
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params->CRn = 0;
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params->CRm = 0;
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return true;
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default:
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return false;
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@ -898,7 +903,14 @@ static u64 cp15_to_index(const struct coproc_reg *reg)
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if (reg->is_64) {
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val |= KVM_REG_SIZE_U64;
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val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
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val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
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/*
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* CRn always denotes the primary coproc. reg. nr. for the
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* in-kernel representation, but the user space API uses the
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* CRm for the encoding, because it is modelled after the
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* MRRC/MCRR instructions: see the ARM ARM rev. c page
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* B3-1445
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*/
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val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
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} else {
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val |= KVM_REG_SIZE_U32;
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val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
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@ -135,6 +135,8 @@ static inline int cmp_reg(const struct coproc_reg *i1,
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return -1;
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if (i1->CRn != i2->CRn)
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return i1->CRn - i2->CRn;
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if (i1->is_64 != i2->is_64)
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return i2->is_64 - i1->is_64;
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if (i1->CRm != i2->CRm)
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return i1->CRm - i2->CRm;
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if (i1->Op1 != i2->Op1)
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@ -145,6 +147,7 @@ static inline int cmp_reg(const struct coproc_reg *i1,
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#define CRn(_x) .CRn = _x
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#define CRm(_x) .CRm = _x
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#define CRm64(_x) .CRn = _x, .CRm = 0
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#define Op1(_x) .Op1 = _x
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#define Op2(_x) .Op2 = _x
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#define is64 .is_64 = true
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@ -114,7 +114,11 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu,
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/*
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* A15-specific CP15 registers.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2
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* CRn denotes the primary register number, but is copied to the CRm in the
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* user space API for 64-bit register access in line with the terminology used
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* in the ARM ARM.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
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* registers preceding 32-bit ones.
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*/
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static const struct coproc_reg a15_regs[] = {
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/* MPIDR: we use VMPIDR for guest access. */
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@ -63,7 +63,8 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
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static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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struct kvm_exit_mmio *mmio)
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{
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unsigned long rt, len;
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unsigned long rt;
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int len;
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bool is_write, sign_extend;
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if (kvm_vcpu_dabt_isextabt(vcpu)) {
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@ -85,6 +85,12 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
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return p;
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}
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static bool page_empty(void *ptr)
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{
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struct page *ptr_page = virt_to_page(ptr);
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return page_count(ptr_page) == 1;
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}
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static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
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{
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pmd_t *pmd_table = pmd_offset(pud, 0);
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@ -103,12 +109,6 @@ static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
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put_page(virt_to_page(pmd));
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}
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static bool pmd_empty(pmd_t *pmd)
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{
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struct page *pmd_page = virt_to_page(pmd);
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return page_count(pmd_page) == 1;
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}
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static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
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{
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if (pte_present(*pte)) {
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@ -118,12 +118,6 @@ static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
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}
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}
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static bool pte_empty(pte_t *pte)
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{
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struct page *pte_page = virt_to_page(pte);
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return page_count(pte_page) == 1;
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}
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static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
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unsigned long long start, u64 size)
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{
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@ -132,37 +126,37 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
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pmd_t *pmd;
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pte_t *pte;
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unsigned long long addr = start, end = start + size;
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u64 range;
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u64 next;
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while (addr < end) {
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pgd = pgdp + pgd_index(addr);
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pud = pud_offset(pgd, addr);
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if (pud_none(*pud)) {
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addr += PUD_SIZE;
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addr = pud_addr_end(addr, end);
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continue;
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}
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pmd = pmd_offset(pud, addr);
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if (pmd_none(*pmd)) {
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addr += PMD_SIZE;
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addr = pmd_addr_end(addr, end);
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continue;
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}
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pte = pte_offset_kernel(pmd, addr);
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clear_pte_entry(kvm, pte, addr);
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range = PAGE_SIZE;
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next = addr + PAGE_SIZE;
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/* If we emptied the pte, walk back up the ladder */
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if (pte_empty(pte)) {
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if (page_empty(pte)) {
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clear_pmd_entry(kvm, pmd, addr);
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range = PMD_SIZE;
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if (pmd_empty(pmd)) {
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next = pmd_addr_end(addr, end);
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if (page_empty(pmd) && !page_empty(pud)) {
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clear_pud_entry(kvm, pud, addr);
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range = PUD_SIZE;
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next = pud_addr_end(addr, end);
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}
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}
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addr += range;
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addr = next;
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}
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}
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@ -42,14 +42,15 @@
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#define TPIDR_EL1 18 /* Thread ID, Privileged */
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#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
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#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
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#define PAR_EL1 21 /* Physical Address Register */
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/* 32bit specific registers. Keep them at the end of the range */
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#define DACR32_EL2 21 /* Domain Access Control Register */
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#define IFSR32_EL2 22 /* Instruction Fault Status Register */
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#define FPEXC32_EL2 23 /* Floating-Point Exception Control Register */
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#define DBGVCR32_EL2 24 /* Debug Vector Catch Register */
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#define TEECR32_EL1 25 /* ThumbEE Configuration Register */
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#define TEEHBR32_EL1 26 /* ThumbEE Handler Base Register */
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#define NR_SYS_REGS 27
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#define DACR32_EL2 22 /* Domain Access Control Register */
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#define IFSR32_EL2 23 /* Instruction Fault Status Register */
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#define FPEXC32_EL2 24 /* Floating-Point Exception Control Register */
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#define DBGVCR32_EL2 25 /* Debug Vector Catch Register */
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#define TEECR32_EL1 26 /* ThumbEE Configuration Register */
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#define TEEHBR32_EL1 27 /* ThumbEE Handler Base Register */
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#define NR_SYS_REGS 28
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/* 32bit mapping */
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#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
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@ -69,6 +70,8 @@
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#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
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#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
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#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
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#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
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#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
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#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
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#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
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#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
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@ -129,7 +129,7 @@ struct kvm_vcpu_arch {
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struct kvm_mmu_memory_cache mmu_page_cache;
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/* Target CPU and feature flags */
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u32 target;
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int target;
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
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/* Detect first run of a vcpu */
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@ -214,6 +214,7 @@ __kvm_hyp_code_start:
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mrs x21, tpidr_el1
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mrs x22, amair_el1
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mrs x23, cntkctl_el1
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mrs x24, par_el1
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stp x4, x5, [x3]
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stp x6, x7, [x3, #16]
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@ -225,6 +226,7 @@ __kvm_hyp_code_start:
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stp x18, x19, [x3, #112]
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stp x20, x21, [x3, #128]
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stp x22, x23, [x3, #144]
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str x24, [x3, #160]
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.endm
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.macro restore_sysregs
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@ -243,6 +245,7 @@ __kvm_hyp_code_start:
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ldp x18, x19, [x3, #112]
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ldp x20, x21, [x3, #128]
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ldp x22, x23, [x3, #144]
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ldr x24, [x3, #160]
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msr vmpidr_el2, x4
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msr csselr_el1, x5
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@ -264,6 +267,7 @@ __kvm_hyp_code_start:
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msr tpidr_el1, x21
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msr amair_el1, x22
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msr cntkctl_el1, x23
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msr par_el1, x24
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.endm
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.macro skip_32bit_state tmp, target
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@ -600,6 +604,8 @@ END(__kvm_vcpu_run)
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// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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ENTRY(__kvm_tlb_flush_vmid_ipa)
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dsb ishst
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kern_hyp_va x0
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ldr x2, [x0, #KVM_VTTBR]
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msr vttbr_el2, x2
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@ -621,6 +627,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
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ENDPROC(__kvm_tlb_flush_vmid_ipa)
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ENTRY(__kvm_flush_vm_context)
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dsb ishst
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tlbi alle1is
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ic ialluis
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dsb sy
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@ -753,6 +760,10 @@ el1_trap:
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*/
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tbnz x1, #7, 1f // S1PTW is set
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/* Preserve PAR_EL1 */
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mrs x3, par_el1
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push x3, xzr
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/*
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* Permission fault, HPFAR_EL2 is invalid.
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* Resolve the IPA the hard way using the guest VA.
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@ -766,6 +777,8 @@ el1_trap:
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/* Read result */
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mrs x3, par_el1
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pop x0, xzr // Restore PAR_EL1 from the stack
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msr par_el1, x0
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tbnz x3, #0, 3f // Bail out if we failed the translation
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ubfx x3, x3, #12, #36 // Extract IPA
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lsl x3, x3, #4 // and present it like HPFAR
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@ -211,6 +211,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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/* FAR_EL1 */
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{ Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
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NULL, reset_unknown, FAR_EL1 },
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/* PAR_EL1 */
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{ Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
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NULL, reset_unknown, PAR_EL1 },
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/* PMINTENSET_EL1 */
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{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
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