OMAPDSS: DSI: add new clock calculation code
Add new way to iterate over DSI PLL and HSDIV clock divisors. dsi_pll_calc() and dss_hsdiv_calc() provide a generic way to go over all the divisors, within given clock range. The functions will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -1280,6 +1280,75 @@ static int dsi_pll_power(struct platform_device *dsidev,
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return 0;
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}
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unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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return clk_get_rate(dsi->sys_clk);
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}
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bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
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unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int regm, regm_start, regm_stop;
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unsigned long out_max;
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unsigned long out;
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out_min = out_min ? out_min : 1;
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out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
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regm_stop = min(pll / out_min, dsi->regm_dispc_max);
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for (regm = regm_start; regm <= regm_stop; ++regm) {
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out = pll / regm;
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if (func(regm, out, data))
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return true;
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}
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return false;
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}
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bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dsi_pll_calc_func func, void *data)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int regn, regn_start, regn_stop;
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int regm, regm_start, regm_stop;
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unsigned long fint, pll;
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const unsigned long pll_hw_max = 1800000000;
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unsigned long fint_hw_min, fint_hw_max;
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fint_hw_min = dsi->fint_min;
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fint_hw_max = dsi->fint_max;
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regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
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regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
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pll_max = pll_max ? pll_max : ULONG_MAX;
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for (regn = regn_start; regn <= regn_stop; ++regn) {
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fint = clkin / regn;
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regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
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1ul);
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regm_stop = min3(pll_max / fint / 2,
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pll_hw_max / fint / 2,
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dsi->regm_max);
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for (regm = regm_start; regm <= regm_stop; ++regm) {
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pll = 2 * regm * fint;
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if (func(regn, regm, fint, pll, data))
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return true;
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}
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}
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return false;
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}
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/* calculate clock rates using dividers in cinfo */
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static int dsi_calc_clock_rates(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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@ -295,6 +295,18 @@ void dsi_dump_clocks(struct seq_file *s);
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void dsi_irq_handler(void);
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u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
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unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
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typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
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unsigned long pll, void *data);
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typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
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void *data);
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bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
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unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
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bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dsi_pll_calc_func func, void *data);
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unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo);
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