amd64_edac: Cleanup DCT Select Low/High code
Shorten macro names, remove family name from macros, fix macro arguments, shorten debug strings. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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cb32850744
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@ -1148,11 +1148,11 @@ static u64 f10_get_error_address(struct mem_ctl_info *mci,
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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if (!amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_LOW, &pvt->dct_sel_low)) {
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debugf0("F2x110 (DCTL Sel. Low): 0x%08x, High range addrs at: 0x%x\n",
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pvt->dct_sel_low, dct_sel_baseaddr(pvt));
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if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
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debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
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pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
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debugf0(" DCT mode: %s, All DCTs on: %s\n",
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debugf0(" mode: %s, All DCTs on: %s\n",
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(dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
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(dct_dram_enabled(pvt) ? "yes" : "no"));
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@ -1160,18 +1160,18 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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debugf0(" Address range split per DCT: %s\n",
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(dct_high_range_enabled(pvt) ? "yes" : "no"));
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debugf0(" DCT data interleave for ECC: %s, "
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debugf0(" data interleave for ECC: %s, "
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"DRAM cleared since last warm reset: %s\n",
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(dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
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(dct_memory_cleared(pvt) ? "yes" : "no"));
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debugf0(" DCT channel interleave: %s, "
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"DCT interleave bits selector: 0x%x\n",
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debugf0(" channel interleave: %s, "
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"interleave bits selector: 0x%x\n",
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(dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
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dct_sel_interleave_addr(pvt));
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}
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amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_HIGH, &pvt->dct_sel_hi);
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amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
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}
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/*
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@ -1181,7 +1181,7 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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static u8 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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bool hi_range_sel, u8 intlv_en)
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{
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u32 dct_sel_high = (pvt->dct_sel_low >> 1) & 1;
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u32 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
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if (dct_ganging_enabled(pvt))
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return 0;
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@ -1955,7 +1955,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
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amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
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if (!dct_ganging_enabled(pvt) && boot_cpu_data.x86 > 0xf) {
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if (!dct_ganging_enabled(pvt)) {
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amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
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amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
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}
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@ -227,19 +227,19 @@
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#define DCHR1 0x194
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#define DDR3_MODE BIT(8)
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#define F10_DCTL_SEL_LOW 0x110
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#define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0))
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#define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2))
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#define DCT_SEL_LO 0x110
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#define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
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#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_low & BIT(4)))
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
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#define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5))
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#define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8))
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#define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10))
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#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
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#define dct_dram_enabled(pvt) ((pvt)->dct_sel_lo & BIT(8))
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#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
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#define F10_DCTL_SEL_HIGH 0x114
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#define DCT_SEL_HI 0x114
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/*
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* Function 3 - Misc Control
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@ -419,8 +419,8 @@ struct amd64_pvt {
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u64 top_mem; /* top of memory below 4GB */
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u64 top_mem2; /* top of memory above 4GB */
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u32 dct_sel_low; /* DRAM Controller Select Low Reg */
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u32 dct_sel_hi; /* DRAM Controller Select High Reg */
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u32 dct_sel_lo; /* DRAM Controller Select Low */
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u32 dct_sel_hi; /* DRAM Controller Select High */
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u32 online_spare; /* On-Line spare Reg */
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/* x4 or x8 syndromes in use */
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