mvebu fixes for 4.1 (part 3)
Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlVo2BIACgkQCwYYjhRyO9Vf4ACZAUuChGNGu5zOwme4AHCuimp6 TnYAn2n7DjGJ+0aOHCY6qAsVGCUdnda9 =FvVk -----END PGP SIGNATURE----- Merge tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu into fixes Merge "mvebu fixes for 4.1 (part 3)" from Gregory CLEMENT: Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) * tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu: Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window" bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms. ARM: mvebu: armada-xp-linksys-mamba: Disable internal RTC
This commit is contained in:
Arnd Bergmann
commit
8f1ab524b1
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@ -95,6 +95,11 @@
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internal-regs {
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rtc@10300 {
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/* No crystal connected to the internal RTC */
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status = "disabled";
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};
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/* J10: VCC, NC, RX, NC, TX, GND */
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serial@12000 {
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status = "okay";
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@ -58,7 +58,6 @@
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#include <linux/debugfs.h>
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#include <linux/log2.h>
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#include <linux/syscore_ops.h>
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#include <linux/memblock.h>
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/*
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* DDR target is the same on all platforms.
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@ -70,6 +69,7 @@
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*/
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#define WIN_CTRL_OFF 0x0000
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#define WIN_CTRL_ENABLE BIT(0)
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/* Only on HW I/O coherency capable platforms */
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#define WIN_CTRL_SYNCBARRIER BIT(1)
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#define WIN_CTRL_TGT_MASK 0xf0
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#define WIN_CTRL_TGT_SHIFT 4
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@ -102,9 +102,7 @@
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/* Relative to mbusbridge_base */
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#define MBUS_BRIDGE_CTRL_OFF 0x0
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#define MBUS_BRIDGE_SIZE_MASK 0xffff0000
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#define MBUS_BRIDGE_BASE_OFF 0x4
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#define MBUS_BRIDGE_BASE_MASK 0xffff0000
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/* Maximum number of windows, for all known platforms */
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#define MBUS_WINS_MAX 20
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@ -323,8 +321,9 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
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ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
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(attr << WIN_CTRL_ATTR_SHIFT) |
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(target << WIN_CTRL_TGT_SHIFT) |
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WIN_CTRL_SYNCBARRIER |
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WIN_CTRL_ENABLE;
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if (mbus->hw_io_coherency)
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ctrl |= WIN_CTRL_SYNCBARRIER;
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writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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@ -577,106 +576,36 @@ static unsigned int armada_xp_mbus_win_remap_offset(int win)
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return MVEBU_MBUS_NO_REMAP;
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}
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/*
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* Use the memblock information to find the MBus bridge hole in the
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* physical address space.
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*/
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static void __init
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mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
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{
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struct memblock_region *r;
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uint64_t s = 0;
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for_each_memblock(memory, r) {
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/*
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* This part of the memory is above 4 GB, so we don't
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* care for the MBus bridge hole.
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*/
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if (r->base >= 0x100000000)
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continue;
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/*
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* The MBus bridge hole is at the end of the RAM under
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* the 4 GB limit.
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*/
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if (r->base + r->size > s)
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s = r->base + r->size;
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}
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*start = s;
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*end = 0x100000000;
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}
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static void __init
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mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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int i;
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int cs;
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uint64_t mbus_bridge_base, mbus_bridge_end;
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mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
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for (i = 0, cs = 0; i < 4; i++) {
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u64 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u64 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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u64 end;
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struct mbus_dram_window *w;
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/* Ignore entries that are not enabled */
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if (!(size & DDR_SIZE_ENABLED))
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continue;
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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/*
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* Ignore entries whose base address is above 2^32,
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* since devices cannot DMA to such high addresses
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* We only take care of entries for which the chip
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* select is enabled, and that don't have high base
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* address bits set (devices can only access the first
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* 32 bits of the memory).
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*/
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if (base & DDR_BASE_CS_HIGH_MASK)
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continue;
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if ((size & DDR_SIZE_ENABLED) &&
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!(base & DDR_BASE_CS_HIGH_MASK)) {
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struct mbus_dram_window *w;
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base = base & DDR_BASE_CS_LOW_MASK;
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size = (size | ~DDR_SIZE_MASK) + 1;
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end = base + size;
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/*
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* Adjust base/size of the current CS to make sure it
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* doesn't overlap with the MBus bridge hole. This is
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* particularly important for devices that do DMA from
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* DRAM to a SRAM mapped in a MBus window, such as the
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* CESA cryptographic engine.
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*/
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/*
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* The CS is fully enclosed inside the MBus bridge
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* area, so ignore it.
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*/
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if (base >= mbus_bridge_base && end <= mbus_bridge_end)
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continue;
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/*
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* Beginning of CS overlaps with end of MBus, raise CS
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* base address, and shrink its size.
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*/
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if (base >= mbus_bridge_base && end > mbus_bridge_end) {
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size -= mbus_bridge_end - base;
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base = mbus_bridge_end;
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w = &mvebu_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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if (mbus->hw_io_coherency)
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w->mbus_attr |= ATTR_HW_COHERENCY;
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w->base = base & DDR_BASE_CS_LOW_MASK;
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w->size = (size | ~DDR_SIZE_MASK) + 1;
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}
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/*
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* End of CS overlaps with beginning of MBus, shrink
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* CS size.
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*/
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if (base < mbus_bridge_base && end > mbus_bridge_base)
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size -= end - mbus_bridge_base;
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w = &mvebu_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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if (mbus->hw_io_coherency)
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w->mbus_attr |= ATTR_HW_COHERENCY;
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w->base = base;
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w->size = size;
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}
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mvebu_mbus_dram_info.num_cs = cs;
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}
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