Merge branch 'fixes-part-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into omap/fixes
This commit is contained in:
commit
c2fda22207
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@ -852,6 +852,7 @@ config ARCH_OMAP
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select HAVE_CLK
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_HAS_CPUFREQ
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select CLKSRC_MMIO
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select GENERIC_CLOCKEVENTS
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select HAVE_SCHED_CLOCK
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select ARCH_HAS_HOLES_MEMORYMODEL
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@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
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* On 1510, 1610 and 1710, McBSP1 and McBSP3
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* are DSP public peripherals.
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*/
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if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
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if (id == 0 || id == 2) {
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if (dsp_use++ == 0) {
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api_clk = clk_get(NULL, "api_ck");
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dsp_clk = clk_get(NULL, "dsp_ck");
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@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
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static void omap1_mcbsp_free(unsigned int id)
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{
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if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
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if (id == 0 || id == 2) {
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if (--dsp_use == 0) {
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if (!IS_ERR(api_clk)) {
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clk_disable(api_clk);
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@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
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# hwmod data
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
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# EMU peripherals
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@ -269,4 +279,4 @@ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
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disp-$(CONFIG_OMAP2_DSS) := display.o
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obj-y += $(disp-m) $(disp-y)
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obj-y += common-board-devices.o
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obj-y += common-board-devices.o twl-common.o
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@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
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omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
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}
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static int sdp3430_batt_table[] = {
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/* 0 C*/
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30800, 29500, 28300, 27100,
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26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
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17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
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11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
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8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
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5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
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4040, 3910, 3790, 3670, 3550
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};
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static struct twl4030_bci_platform_data sdp3430_bci_data = {
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.battery_tmp_tbl = sdp3430_batt_table,
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.tblsize = ARRAY_SIZE(sdp3430_batt_table),
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};
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static struct omap2_hsmmc_info mmc[] = {
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{
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.mmc = 1,
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@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
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.setup = sdp3430_twl_gpio_setup,
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};
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static struct twl4030_usb_data sdp3430_usb_data = {
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.usb_mode = T2_USB_MODE_ULPI,
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};
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static struct twl4030_madc_platform_data sdp3430_madc_data = {
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.irq_line = 1,
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};
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/* regulator consumer mappings */
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/* ads7846 on SPI */
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@ -307,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
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REGULATOR_SUPPLY("vcc", "spi1.0"),
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};
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static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
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REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
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};
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/* VPLL2 for digital video outputs */
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static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
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REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
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REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
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};
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static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
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REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
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};
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@ -433,54 +399,10 @@ static struct regulator_init_data sdp3430_vsim = {
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.consumer_supplies = sdp3430_vsim_supplies,
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};
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/* VDAC for DSS driving S-Video */
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static struct regulator_init_data sdp3430_vdac = {
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.constraints = {
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.min_uV = 1800000,
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.max_uV = 1800000,
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.apply_uV = true,
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.valid_modes_mask = REGULATOR_MODE_NORMAL
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| REGULATOR_MODE_STANDBY,
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.valid_ops_mask = REGULATOR_CHANGE_MODE
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| REGULATOR_CHANGE_STATUS,
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},
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.num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
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.consumer_supplies = sdp3430_vdda_dac_supplies,
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};
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static struct regulator_init_data sdp3430_vpll2 = {
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.constraints = {
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.name = "VDVI",
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.min_uV = 1800000,
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.max_uV = 1800000,
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.apply_uV = true,
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.valid_modes_mask = REGULATOR_MODE_NORMAL
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| REGULATOR_MODE_STANDBY,
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.valid_ops_mask = REGULATOR_CHANGE_MODE
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| REGULATOR_CHANGE_STATUS,
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},
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.num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
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.consumer_supplies = sdp3430_vpll2_supplies,
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};
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static struct twl4030_codec_audio_data sdp3430_audio;
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static struct twl4030_codec_data sdp3430_codec = {
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.audio_mclk = 26000000,
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.audio = &sdp3430_audio,
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};
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static struct twl4030_platform_data sdp3430_twldata = {
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.irq_base = TWL4030_IRQ_BASE,
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.irq_end = TWL4030_IRQ_END,
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/* platform_data for children goes here */
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.bci = &sdp3430_bci_data,
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.gpio = &sdp3430_gpio_data,
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.madc = &sdp3430_madc_data,
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.keypad = &sdp3430_kp_data,
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.usb = &sdp3430_usb_data,
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.codec = &sdp3430_codec,
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.vaux1 = &sdp3430_vaux1,
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.vaux2 = &sdp3430_vaux2,
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@ -489,14 +411,21 @@ static struct twl4030_platform_data sdp3430_twldata = {
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.vmmc1 = &sdp3430_vmmc1,
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.vmmc2 = &sdp3430_vmmc2,
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.vsim = &sdp3430_vsim,
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.vdac = &sdp3430_vdac,
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.vpll2 = &sdp3430_vpll2,
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};
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static int __init omap3430_i2c_init(void)
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{
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/* i2c1 for PMIC only */
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omap3_pmic_get_config(&sdp3430_twldata,
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TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
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TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
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TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
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sdp3430_twldata.vdac->constraints.apply_uV = true;
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sdp3430_twldata.vpll2->constraints.apply_uV = true;
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sdp3430_twldata.vpll2->constraints.name = "VDVI";
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omap3_pmic_init("twl4030", &sdp3430_twldata);
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/* i2c2 on camera connector (for sensor control) and optional isp1301 */
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omap_register_i2c_bus(2, 400, NULL, 0);
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/* i2c3 on display connector (for DVI, tfp410) */
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@ -302,14 +302,6 @@ static struct omap_musb_board_data musb_board_data = {
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.power = 100,
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};
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static struct twl4030_usb_data omap4_usbphy_data = {
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.phy_init = omap4430_phy_init,
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.phy_exit = omap4430_phy_exit,
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.phy_power = omap4430_phy_power,
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.phy_set_clock = omap4430_phy_set_clk,
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.phy_suspend = omap4430_phy_suspend,
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};
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static struct omap2_hsmmc_info mmc[] = {
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{
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.mmc = 2,
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@ -332,10 +324,6 @@ static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
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REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
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};
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static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
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REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
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};
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static int omap4_twl6030_hsmmc_late_init(struct device *dev)
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{
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int ret = 0;
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@ -394,61 +382,6 @@ static struct regulator_init_data sdp4430_vaux1 = {
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.consumer_supplies = sdp4430_vaux_supply,
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};
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static struct regulator_init_data sdp4430_vaux2 = {
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.constraints = {
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.min_uV = 1200000,
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.max_uV = 2800000,
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.apply_uV = true,
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.valid_modes_mask = REGULATOR_MODE_NORMAL
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| REGULATOR_MODE_STANDBY,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
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| REGULATOR_CHANGE_MODE
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| REGULATOR_CHANGE_STATUS,
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},
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};
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|
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static struct regulator_init_data sdp4430_vaux3 = {
|
||||
.constraints = {
|
||||
.min_uV = 1000000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
/* VMMC1 for MMC1 card */
|
||||
static struct regulator_init_data sdp4430_vmmc = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = sdp4430_vmmc_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vpp = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 2500000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vusim = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
|
@ -462,74 +395,10 @@ static struct regulator_init_data sdp4430_vusim = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vana = {
|
||||
.constraints = {
|
||||
.min_uV = 2100000,
|
||||
.max_uV = 2100000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vcxio = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_vusb = {
|
||||
.constraints = {
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data sdp4430_clk32kg = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data sdp4430_twldata = {
|
||||
.irq_base = TWL6030_IRQ_BASE,
|
||||
.irq_end = TWL6030_IRQ_END,
|
||||
|
||||
/* Regulators */
|
||||
.vmmc = &sdp4430_vmmc,
|
||||
.vpp = &sdp4430_vpp,
|
||||
.vusim = &sdp4430_vusim,
|
||||
.vana = &sdp4430_vana,
|
||||
.vcxio = &sdp4430_vcxio,
|
||||
.vdac = &sdp4430_vdac,
|
||||
.vusb = &sdp4430_vusb,
|
||||
.vaux1 = &sdp4430_vaux1,
|
||||
.vaux2 = &sdp4430_vaux2,
|
||||
.vaux3 = &sdp4430_vaux3,
|
||||
.clk32kg = &sdp4430_clk32kg,
|
||||
.usb = &omap4_usbphy_data
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
|
||||
|
@ -547,6 +416,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
|
|||
};
|
||||
static int __init omap4_i2c_init(void)
|
||||
{
|
||||
omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
|
||||
TWL_COMMON_REGULATOR_VDAC |
|
||||
TWL_COMMON_REGULATOR_VAUX2 |
|
||||
TWL_COMMON_REGULATOR_VAUX3 |
|
||||
TWL_COMMON_REGULATOR_VMMC |
|
||||
TWL_COMMON_REGULATOR_VPP |
|
||||
TWL_COMMON_REGULATOR_VANA |
|
||||
TWL_COMMON_REGULATOR_VCXIO |
|
||||
TWL_COMMON_REGULATOR_VUSB |
|
||||
TWL_COMMON_REGULATOR_CLK32KG);
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
|
||||
|
|
|
@ -339,10 +339,6 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
|
|||
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply cm_t35_vdac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
|
||||
REGULATOR_SUPPLY("vdvi", "omapdss"),
|
||||
};
|
||||
|
@ -377,39 +373,6 @@ static struct regulator_init_data cm_t35_vsim = {
|
|||
.consumer_supplies = cm_t35_vsim_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data cm_t35_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vdac_supply),
|
||||
.consumer_supplies = cm_t35_vdac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data cm_t35_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vdvi_supply),
|
||||
.consumer_supplies = cm_t35_vdvi_supply,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data cm_t35_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static uint32_t cm_t35_keymap[] = {
|
||||
KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
|
||||
KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
|
||||
|
@ -488,21 +451,23 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
|
|||
};
|
||||
|
||||
static struct twl4030_platform_data cm_t35_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.keypad = &cm_t35_kp_data,
|
||||
.usb = &cm_t35_usb_data,
|
||||
.gpio = &cm_t35_gpio_data,
|
||||
.vmmc1 = &cm_t35_vmmc1,
|
||||
.vsim = &cm_t35_vsim,
|
||||
.vdac = &cm_t35_vdac,
|
||||
.vpll2 = &cm_t35_vpll2,
|
||||
};
|
||||
|
||||
static void __init cm_t35_init_i2c(void)
|
||||
{
|
||||
omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
cm_t35_twldata.vpll2->constraints.name = "VDVI";
|
||||
cm_t35_twldata.vpll2->num_consumer_supplies =
|
||||
ARRAY_SIZE(cm_t35_vdvi_supply);
|
||||
cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
|
||||
|
||||
omap3_pmic_init("tps65930", &cm_t35_twldata);
|
||||
}
|
||||
|
||||
|
|
|
@ -186,10 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
|
|||
.default_device = &devkit8000_lcd_device,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply devkit8000_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static uint32_t board_keymap[] = {
|
||||
KEY(0, 0, KEY_1),
|
||||
KEY(1, 0, KEY_2),
|
||||
|
@ -289,20 +285,6 @@ static struct regulator_init_data devkit8000_vmmc1 = {
|
|||
.consumer_supplies = devkit8000_vmmc1_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data devkit8000_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(devkit8000_vdda_dac_supply),
|
||||
.consumer_supplies = devkit8000_vdda_dac_supply,
|
||||
};
|
||||
|
||||
/* VPLL1 for digital video outputs */
|
||||
static struct regulator_init_data devkit8000_vpll1 = {
|
||||
.constraints = {
|
||||
|
@ -332,27 +314,10 @@ static struct regulator_init_data devkit8000_vio = {
|
|||
.consumer_supplies = devkit8000_vio_supply,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data devkit8000_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data devkit8000_audio_data;
|
||||
|
||||
static struct twl4030_codec_data devkit8000_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &devkit8000_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data devkit8000_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.usb = &devkit8000_usb_data,
|
||||
.gpio = &devkit8000_gpio_data,
|
||||
.codec = &devkit8000_codec_data,
|
||||
.vmmc1 = &devkit8000_vmmc1,
|
||||
.vdac = &devkit8000_vdac,
|
||||
.vpll1 = &devkit8000_vpll1,
|
||||
.vio = &devkit8000_vio,
|
||||
.keypad = &devkit8000_kp_data,
|
||||
|
@ -360,6 +325,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
|
|||
|
||||
static int __init devkit8000_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&devkit8000_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC);
|
||||
omap3_pmic_init("tps65930", &devkit8000_twldata);
|
||||
/* Bus 3 is attached to the DVI port where devices like the pico DLP
|
||||
* projector don't work reliably with 400kHz */
|
||||
|
|
|
@ -72,5 +72,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
|
|||
.init_early = omap_generic_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.timer = &omap3_timer,
|
||||
.timer = &omap2_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -443,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
|
|||
.setup = igep_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data igep_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static int igep2_enable_dvi(struct omap_dss_device *dssdev)
|
||||
{
|
||||
gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
|
||||
|
@ -483,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
|
|||
.default_device = &igep2_dvi_device,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data igep2_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies),
|
||||
.consumer_supplies = igep2_vpll2_supplies,
|
||||
};
|
||||
|
||||
static void __init igep2_display_init(void)
|
||||
{
|
||||
int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
|
||||
|
@ -522,13 +498,6 @@ static void __init igep_init_early(void)
|
|||
m65kxxxxam_sdrc_params);
|
||||
}
|
||||
|
||||
static struct twl4030_codec_audio_data igep2_audio_data;
|
||||
|
||||
static struct twl4030_codec_data igep2_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &igep2_audio_data,
|
||||
};
|
||||
|
||||
static int igep2_keymap[] = {
|
||||
KEY(0, 0, KEY_LEFT),
|
||||
KEY(0, 1, KEY_RIGHT),
|
||||
|
@ -561,11 +530,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
|
|||
};
|
||||
|
||||
static struct twl4030_platform_data igep_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.usb = &igep_usb_data,
|
||||
.gpio = &igep_twl4030_gpio_pdata,
|
||||
.vmmc1 = &igep_vmmc1,
|
||||
.vio = &igep_vio,
|
||||
|
@ -581,6 +546,8 @@ static void __init igep_i2c_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
|
||||
|
||||
if (machine_is_igep0020()) {
|
||||
/*
|
||||
* Bus 3 is attached to the DVI port where devices like the
|
||||
|
@ -591,9 +558,12 @@ static void __init igep_i2c_init(void)
|
|||
if (ret)
|
||||
pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
|
||||
|
||||
igep_twldata.codec = &igep2_codec_data;
|
||||
igep_twldata.keypad = &igep2_keypad_pdata;
|
||||
igep_twldata.vpll2 = &igep2_vpll2;
|
||||
/* Get common pmic data */
|
||||
omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VPLL2);
|
||||
igep_twldata.vpll2->constraints.apply_uV = true;
|
||||
igep_twldata.vpll2->constraints.name = "VDVI";
|
||||
}
|
||||
|
||||
omap3_pmic_init("twl4030", &igep_twldata);
|
||||
|
|
|
@ -199,20 +199,12 @@ static void __init omap_ldp_init_early(void)
|
|||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct twl4030_usb_data ldp_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_gpio_platform_data ldp_gpio_data = {
|
||||
.gpio_base = OMAP_MAX_GPIO_LINES,
|
||||
.irq_base = TWL4030_GPIO_IRQ_BASE,
|
||||
.irq_end = TWL4030_GPIO_IRQ_END,
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data ldp_madc_data = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
|
||||
};
|
||||
|
@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
|
|||
};
|
||||
|
||||
static struct twl4030_platform_data ldp_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.madc = &ldp_madc_data,
|
||||
.usb = &ldp_usb_data,
|
||||
.vmmc1 = &ldp_vmmc1,
|
||||
.vaux1 = &ldp_vaux1,
|
||||
.gpio = &ldp_gpio_data,
|
||||
|
@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
|
|||
|
||||
static int __init omap_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&ldp_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
|
||||
omap3_pmic_init("twl4030", &ldp_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
|
|
|
@ -209,15 +209,6 @@ static struct omap_dss_board_info beagle_dss_data = {
|
|||
.default_device = &beagle_dvi_device,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply beagle_vdac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static void __init beagle_display_init(void)
|
||||
{
|
||||
int r;
|
||||
|
@ -351,58 +342,11 @@ static struct regulator_init_data beagle_vsim = {
|
|||
.consumer_supplies = beagle_vsim_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data beagle_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(beagle_vdac_supply),
|
||||
.consumer_supplies = beagle_vdac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data beagle_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies),
|
||||
.consumer_supplies = beagle_vdvi_supplies,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data beagle_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data beagle_audio_data;
|
||||
|
||||
static struct twl4030_codec_data beagle_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &beagle_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data beagle_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.usb = &beagle_usb_data,
|
||||
.gpio = &beagle_gpio_data,
|
||||
.codec = &beagle_codec_data,
|
||||
.vmmc1 = &beagle_vmmc1,
|
||||
.vsim = &beagle_vsim,
|
||||
.vdac = &beagle_vdac,
|
||||
.vpll2 = &beagle_vpll2,
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
|
||||
|
@ -413,6 +357,12 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
|
|||
|
||||
static int __init omap3_beagle_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&beagle_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
beagle_twldata.vpll2->constraints.name = "VDVI";
|
||||
|
||||
omap3_pmic_init("twl4030", &beagle_twldata);
|
||||
/* Bus 3 is attached to the DVI port where devices like the pico DLP
|
||||
* projector don't work reliably with 400kHz */
|
||||
|
|
|
@ -396,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
|
|||
.setup = omap3evm_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap3evm_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static uint32_t board_keymap[] = {
|
||||
KEY(0, 0, KEY_LEFT),
|
||||
KEY(0, 1, KEY_DOWN),
|
||||
|
@ -434,56 +430,6 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
|
|||
.rep = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data omap3evm_madc_data = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data omap3evm_audio_data;
|
||||
|
||||
static struct twl4030_codec_data omap3evm_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &omap3evm_audio_data,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video */
|
||||
static struct regulator_init_data omap3_evm_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_evm_vdda_dac_supply),
|
||||
.consumer_supplies = omap3_evm_vdda_dac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap3_evm_vpll2 = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
|
||||
.consumer_supplies = omap3_evm_vpll2_supplies,
|
||||
};
|
||||
|
||||
/* ads7846 on SPI */
|
||||
static struct regulator_consumer_supply omap3evm_vio_supply[] = {
|
||||
REGULATOR_SUPPLY("vcc", "spi1.0"),
|
||||
|
@ -547,17 +493,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
|
|||
#endif
|
||||
|
||||
static struct twl4030_platform_data omap3evm_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.keypad = &omap3evm_kp_data,
|
||||
.madc = &omap3evm_madc_data,
|
||||
.usb = &omap3evm_usb_data,
|
||||
.gpio = &omap3evm_gpio_data,
|
||||
.codec = &omap3evm_codec_data,
|
||||
.vdac = &omap3_evm_vdac,
|
||||
.vpll2 = &omap3_evm_vpll2,
|
||||
.vio = &omap3evm_vio,
|
||||
.vmmc1 = &omap3evm_vmmc1,
|
||||
.vsim = &omap3evm_vsim,
|
||||
|
@ -565,6 +503,14 @@ static struct twl4030_platform_data omap3evm_twldata = {
|
|||
|
||||
static int __init omap3_evm_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&omap3evm_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
|
||||
TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
omap3evm_twldata.vdac->constraints.apply_uV = true;
|
||||
omap3evm_twldata.vpll2->constraints.apply_uV = true;
|
||||
|
||||
omap3_pmic_init("twl4030", &omap3evm_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
|
|
|
@ -332,10 +332,6 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
|
|||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply pandora_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply pandora_vdds_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
|
@ -391,36 +387,6 @@ static struct regulator_init_data pandora_vmmc2 = {
|
|||
.consumer_supplies = pandora_vmmc2_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video */
|
||||
static struct regulator_init_data pandora_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(pandora_vdda_dac_supply),
|
||||
.consumer_supplies = pandora_vdda_dac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data pandora_vpll2 = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
|
||||
.consumer_supplies = pandora_vdds_supplies,
|
||||
};
|
||||
|
||||
/* VAUX1 for LCD */
|
||||
static struct regulator_init_data pandora_vaux1 = {
|
||||
.constraints = {
|
||||
|
@ -508,29 +474,12 @@ static struct platform_device pandora_vwlan_device = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap3pandora_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data omap3pandora_audio_data;
|
||||
|
||||
static struct twl4030_codec_data omap3pandora_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &omap3pandora_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_bci_platform_data pandora_bci_data;
|
||||
|
||||
static struct twl4030_platform_data omap3pandora_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
.gpio = &omap3pandora_gpio_data,
|
||||
.usb = &omap3pandora_usb_data,
|
||||
.codec = &omap3pandora_codec_data,
|
||||
.vmmc1 = &pandora_vmmc1,
|
||||
.vmmc2 = &pandora_vmmc2,
|
||||
.vdac = &pandora_vdac,
|
||||
.vpll2 = &pandora_vpll2,
|
||||
.vaux1 = &pandora_vaux1,
|
||||
.vaux2 = &pandora_vaux2,
|
||||
.vaux4 = &pandora_vaux4,
|
||||
|
@ -548,6 +497,17 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
|
|||
|
||||
static int __init omap3pandora_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&omap3pandora_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
omap3pandora_twldata.vdac->constraints.apply_uV = true;
|
||||
|
||||
omap3pandora_twldata.vpll2->constraints.apply_uV = true;
|
||||
omap3pandora_twldata.vpll2->num_consumer_supplies =
|
||||
ARRAY_SIZE(pandora_vdds_supplies);
|
||||
omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
|
||||
|
||||
omap3_pmic_init("tps65950", &omap3pandora_twldata);
|
||||
/* i2c2 pins are not connected */
|
||||
omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
|
||||
|
|
|
@ -349,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
|
|||
.setup = omap3stalker_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap3stalker_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static uint32_t board_keymap[] = {
|
||||
KEY(0, 0, KEY_LEFT),
|
||||
KEY(0, 1, KEY_DOWN),
|
||||
|
@ -387,69 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
|
|||
.rep = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data omap3stalker_madc_data = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data omap3stalker_audio_data;
|
||||
|
||||
static struct twl4030_codec_data omap3stalker_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &omap3stalker_audio_data,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video */
|
||||
static struct regulator_init_data omap3_stalker_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vdda_dac_supply),
|
||||
.consumer_supplies = omap3_stalker_vdda_dac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap3_stalker_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
|
||||
.consumer_supplies = omap3_stalker_vpll2_supplies,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data omap3stalker_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.keypad = &omap3stalker_kp_data,
|
||||
.madc = &omap3stalker_madc_data,
|
||||
.usb = &omap3stalker_usb_data,
|
||||
.gpio = &omap3stalker_gpio_data,
|
||||
.codec = &omap3stalker_codec_data,
|
||||
.vdac = &omap3_stalker_vdac,
|
||||
.vpll2 = &omap3_stalker_vpll2,
|
||||
.vmmc1 = &omap3stalker_vmmc1,
|
||||
.vsim = &omap3stalker_vsim,
|
||||
};
|
||||
|
@ -470,6 +407,15 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
|
|||
|
||||
static int __init omap3_stalker_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&omap3stalker_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
|
||||
TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
omap3stalker_twldata.vdac->constraints.apply_uV = true;
|
||||
omap3stalker_twldata.vpll2->constraints.apply_uV = true;
|
||||
omap3stalker_twldata.vpll2->constraints.name = "VDVI";
|
||||
|
||||
omap3_pmic_init("twl4030", &omap3stalker_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
|
||||
|
|
|
@ -206,58 +206,11 @@ static struct regulator_init_data touchbook_vsim = {
|
|||
.consumer_supplies = touchbook_vsim_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data touchbook_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(touchbook_vdac_supply),
|
||||
.consumer_supplies = touchbook_vdac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data touchbook_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(touchbook_vdvi_supply),
|
||||
.consumer_supplies = touchbook_vdvi_supply,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data touchbook_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data touchbook_audio_data;
|
||||
|
||||
static struct twl4030_codec_data touchbook_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &touchbook_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data touchbook_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.usb = &touchbook_usb_data,
|
||||
.gpio = &touchbook_gpio_data,
|
||||
.codec = &touchbook_codec_data,
|
||||
.vmmc1 = &touchbook_vmmc1,
|
||||
.vsim = &touchbook_vsim,
|
||||
.vdac = &touchbook_vdac,
|
||||
.vpll2 = &touchbook_vpll2,
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
|
||||
|
@ -269,8 +222,20 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
|
|||
static int __init omap3_touchbook_i2c_init(void)
|
||||
{
|
||||
/* Standard TouchBook bus */
|
||||
omap3_pmic_init("twl4030", &touchbook_twldata);
|
||||
omap3_pmic_get_config(&touchbook_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
touchbook_twldata.vdac->num_consumer_supplies =
|
||||
ARRAY_SIZE(touchbook_vdac_supply);
|
||||
touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
|
||||
|
||||
touchbook_twldata.vpll2->constraints.name = "VDVI";
|
||||
touchbook_twldata.vpll2->num_consumer_supplies =
|
||||
ARRAY_SIZE(touchbook_vdvi_supply);
|
||||
touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
|
||||
|
||||
omap3_pmic_init("twl4030", &touchbook_twldata);
|
||||
/* Additional TouchBook bus */
|
||||
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
|
||||
ARRAY_SIZE(touchBook_i2c_boardinfo));
|
||||
|
|
|
@ -154,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
|
|||
.power = 100,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap4_usbphy_data = {
|
||||
.phy_init = omap4430_phy_init,
|
||||
.phy_exit = omap4430_phy_exit,
|
||||
.phy_power = omap4430_phy_power,
|
||||
.phy_set_clock = omap4430_phy_set_clk,
|
||||
.phy_suspend = omap4430_phy_suspend,
|
||||
};
|
||||
|
||||
static struct omap2_hsmmc_info mmc[] = {
|
||||
{
|
||||
.mmc = 1,
|
||||
|
@ -181,10 +173,6 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
|
||||
};
|
||||
|
@ -269,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct regulator_init_data omap4_panda_vaux2 = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vaux3 = {
|
||||
.constraints = {
|
||||
.min_uV = 1000000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
/* VMMC1 for MMC1 card */
|
||||
static struct regulator_init_data omap4_panda_vmmc = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc_supply),
|
||||
.consumer_supplies = omap4_panda_vmmc_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vpp = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 2500000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vana = {
|
||||
.constraints = {
|
||||
.min_uV = 2100000,
|
||||
.max_uV = 2100000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vcxio = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_vusb = {
|
||||
.constraints = {
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_panda_clk32kg = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data omap4_panda_twldata = {
|
||||
.irq_base = TWL6030_IRQ_BASE,
|
||||
.irq_end = TWL6030_IRQ_END,
|
||||
|
||||
/* Regulators */
|
||||
.vmmc = &omap4_panda_vmmc,
|
||||
.vpp = &omap4_panda_vpp,
|
||||
.vana = &omap4_panda_vana,
|
||||
.vcxio = &omap4_panda_vcxio,
|
||||
.vdac = &omap4_panda_vdac,
|
||||
.vusb = &omap4_panda_vusb,
|
||||
.vaux2 = &omap4_panda_vaux2,
|
||||
.vaux3 = &omap4_panda_vaux3,
|
||||
.clk32kg = &omap4_panda_clk32kg,
|
||||
.usb = &omap4_usbphy_data,
|
||||
};
|
||||
/* Panda board uses the common PMIC configuration */
|
||||
static struct twl4030_platform_data omap4_panda_twldata;
|
||||
|
||||
/*
|
||||
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
|
||||
|
@ -404,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
|
|||
|
||||
static int __init omap4_panda_i2c_init(void)
|
||||
{
|
||||
omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
|
||||
TWL_COMMON_REGULATOR_VDAC |
|
||||
TWL_COMMON_REGULATOR_VAUX2 |
|
||||
TWL_COMMON_REGULATOR_VAUX3 |
|
||||
TWL_COMMON_REGULATOR_VMMC |
|
||||
TWL_COMMON_REGULATOR_VPP |
|
||||
TWL_COMMON_REGULATOR_VANA |
|
||||
TWL_COMMON_REGULATOR_VCXIO |
|
||||
TWL_COMMON_REGULATOR_VUSB |
|
||||
TWL_COMMON_REGULATOR_CLK32KG);
|
||||
omap4_pmic_init("twl6030", &omap4_panda_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
/*
|
||||
|
|
|
@ -265,15 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
|
|||
.default_device = &overo_dvi_device,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply overo_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct mtd_partition overo_nand_partitions[] = {
|
||||
{
|
||||
.name = "xloader",
|
||||
|
@ -433,10 +424,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
|
|||
.setup = overo_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data overo_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct regulator_init_data overo_vmmc1 = {
|
||||
.constraints = {
|
||||
.min_uV = 1850000,
|
||||
|
@ -451,55 +438,19 @@ static struct regulator_init_data overo_vmmc1 = {
|
|||
.consumer_supplies = overo_vmmc1_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data overo_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(overo_vdda_dac_supply),
|
||||
.consumer_supplies = overo_vdda_dac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data overo_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply),
|
||||
.consumer_supplies = overo_vdds_dsi_supply,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data overo_audio_data;
|
||||
|
||||
static struct twl4030_codec_data overo_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &overo_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data overo_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
.gpio = &overo_gpio_data,
|
||||
.usb = &overo_usb_data,
|
||||
.codec = &overo_codec_data,
|
||||
.vmmc1 = &overo_vmmc1,
|
||||
.vdac = &overo_vdac,
|
||||
.vpll2 = &overo_vpll2,
|
||||
};
|
||||
|
||||
static int __init overo_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&overo_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
overo_twldata.vpll2->constraints.name = "VDVI";
|
||||
|
||||
omap3_pmic_init("tps65950", &overo_twldata);
|
||||
/* i2c2 pins are used for gpio */
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
|
|
|
@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
|
|||
.pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data rm680_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data rm680_twl_data = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
.gpio = &rm680_gpio_data,
|
||||
.usb = &rm680_usb_data,
|
||||
/* add rest of the children here */
|
||||
};
|
||||
|
||||
static void __init rm680_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
|
||||
omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
|
|
|
@ -288,10 +288,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
|
|||
.rep = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data rx51_madc_data = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
/* Enable input logic and pull all lines up when eMMC is on. */
|
||||
static struct omap_board_mux rx51_mmc2_on_mux[] = {
|
||||
OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
|
||||
|
@ -398,10 +394,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
|
|||
REGULATOR_SUPPLY("vdd", "2-0063"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply rx51_vdac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data rx51_vaux1 = {
|
||||
.constraints = {
|
||||
.name = "V28",
|
||||
|
@ -518,21 +510,6 @@ static struct regulator_init_data rx51_vsim = {
|
|||
.consumer_supplies = rx51_vsim_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data rx51_vdac = {
|
||||
.constraints = {
|
||||
.name = "VDAC",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(rx51_vdac_supply),
|
||||
.consumer_supplies = rx51_vdac_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data rx51_vio = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
|
@ -603,10 +580,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
|
|||
.setup = rx51_twlgpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data rx51_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_ins sleep_on_seq[] __initdata = {
|
||||
/*
|
||||
* Turn off everything
|
||||
|
@ -778,14 +751,9 @@ struct twl4030_codec_data rx51_codec_data __initdata = {
|
|||
};
|
||||
|
||||
static struct twl4030_platform_data rx51_twldata __initdata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.gpio = &rx51_gpio_data,
|
||||
.keypad = &rx51_kp_data,
|
||||
.madc = &rx51_madc_data,
|
||||
.usb = &rx51_usb_data,
|
||||
.power = &rx51_t2scripts_data,
|
||||
.codec = &rx51_codec_data,
|
||||
|
||||
|
@ -794,7 +762,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
|
|||
.vaux4 = &rx51_vaux4,
|
||||
.vmmc1 = &rx51_vmmc1,
|
||||
.vsim = &rx51_vsim,
|
||||
.vdac = &rx51_vdac,
|
||||
.vio = &rx51_vio,
|
||||
};
|
||||
|
||||
|
@ -850,6 +817,13 @@ static int __init rx51_i2c_init(void)
|
|||
rx51_twldata.vaux3 = &rx51_vaux3_cam;
|
||||
}
|
||||
rx51_twldata.vmmc2 = &rx51_vmmc2;
|
||||
omap3_pmic_get_config(&rx51_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
|
||||
TWL_COMMON_REGULATOR_VDAC);
|
||||
|
||||
rx51_twldata.vdac->constraints.apply_uV = true;
|
||||
rx51_twldata.vdac->constraints.name = "VDAC";
|
||||
|
||||
omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
|
||||
omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
|
||||
ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
|
||||
|
|
|
@ -226,41 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
|
|||
{} /* Terminator */
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply zoom_vdda_dac_supply[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data zoom_vpll2 = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies),
|
||||
.consumer_supplies = zoom_vpll2_supplies,
|
||||
};
|
||||
|
||||
static struct regulator_init_data zoom_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(zoom_vdda_dac_supply),
|
||||
.consumer_supplies = zoom_vdda_dac_supply,
|
||||
};
|
||||
|
||||
static int zoom_twl_gpio_setup(struct device *dev,
|
||||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
|
@ -285,26 +250,6 @@ static void zoom2_set_hs_extmute(int mute)
|
|||
gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
|
||||
}
|
||||
|
||||
static int zoom_batt_table[] = {
|
||||
/* 0 C*/
|
||||
30800, 29500, 28300, 27100,
|
||||
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
|
||||
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
|
||||
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
|
||||
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
|
||||
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
|
||||
4040, 3910, 3790, 3670, 3550
|
||||
};
|
||||
|
||||
static struct twl4030_bci_platform_data zoom_bci_data = {
|
||||
.battery_tmp_tbl = zoom_batt_table,
|
||||
.tblsize = ARRAY_SIZE(zoom_batt_table),
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data zoom_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_gpio_platform_data zoom_gpio_data = {
|
||||
.gpio_base = OMAP_MAX_GPIO_LINES,
|
||||
.irq_base = TWL4030_GPIO_IRQ_BASE,
|
||||
|
@ -312,41 +257,29 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
|
|||
.setup = zoom_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data zoom_madc_data = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data zoom_audio_data;
|
||||
|
||||
static struct twl4030_codec_data zoom_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &zoom_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data zoom_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.bci = &zoom_bci_data,
|
||||
.madc = &zoom_madc_data,
|
||||
.usb = &zoom_usb_data,
|
||||
.gpio = &zoom_gpio_data,
|
||||
.keypad = &zoom_kp_twl4030_data,
|
||||
.codec = &zoom_codec_data,
|
||||
.vmmc1 = &zoom_vmmc1,
|
||||
.vmmc2 = &zoom_vmmc2,
|
||||
.vsim = &zoom_vsim,
|
||||
.vpll2 = &zoom_vpll2,
|
||||
.vdac = &zoom_vdac,
|
||||
};
|
||||
|
||||
static int __init omap_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_get_config(&zoom_twldata,
|
||||
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
|
||||
TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
|
||||
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
|
||||
|
||||
if (machine_is_omap_zoom2()) {
|
||||
zoom_audio_data.ramp_delay_value = 3; /* 161 ms */
|
||||
zoom_audio_data.hs_extmute = 1;
|
||||
zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
|
||||
struct twl4030_codec_audio_data *audio_data;
|
||||
audio_data = zoom_twldata.codec->audio;
|
||||
|
||||
audio_data->ramp_delay_value = 3; /* 161 ms */
|
||||
audio_data->hs_extmute = 1;
|
||||
audio_data->set_hs_extmute = zoom2_set_hs_extmute;
|
||||
}
|
||||
omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
|
|
|
@ -8,13 +8,6 @@
|
|||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
|
||||
|
||||
/*
|
||||
* XXX Missing values for the OMAP4 DPLL_USB
|
||||
* XXX Missing min_multiplier values for all OMAP4 DPLLs
|
||||
*/
|
||||
#define OMAP4430_MAX_DPLL_MULT 2047
|
||||
#define OMAP4430_MAX_DPLL_DIV 128
|
||||
|
||||
int omap4xxx_clk_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
|
|||
static struct clk pad_clks_ck = {
|
||||
.name = "pad_clks_ck",
|
||||
.rate = 12000000,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
||||
.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
||||
.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk pad_slimbus_core_clks_ck = {
|
||||
|
@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
|
|||
static struct clk slimbus_clk = {
|
||||
.name = "slimbus_clk",
|
||||
.rate = 12000000,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
||||
.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
|
||||
.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk sys_32k_ck = {
|
||||
|
@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
|
|||
static struct clk dpll_abe_x2_ck = {
|
||||
.name = "dpll_abe_x2_ck",
|
||||
.parent = &dpll_abe_ck,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
|
||||
.flags = CLOCK_CLKOUTX2,
|
||||
.ops = &clkops_omap4_dpllmx_ops,
|
||||
.recalc = &omap3_clkoutx2_recalc,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
|
||||
};
|
||||
|
||||
static const struct clksel_rate div31_1to31_rates[] = {
|
||||
|
@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
|
|||
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
||||
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
||||
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
.round_rate = &omap2_clksel_round_rate,
|
||||
.set_rate = &omap2_clksel_set_rate,
|
||||
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
|
||||
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk dpll_core_m7x2_ck = {
|
||||
|
@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.max_multiplier = 2047,
|
||||
.max_divider = 128,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
|
|||
static struct clk dpll_per_x2_ck = {
|
||||
.name = "dpll_per_x2_ck",
|
||||
.parent = &dpll_per_ck,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
|
||||
.flags = CLOCK_CLKOUTX2,
|
||||
.ops = &clkops_omap4_dpllmx_ops,
|
||||
.recalc = &omap3_clkoutx2_recalc,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
|
||||
};
|
||||
|
||||
static const struct clksel dpll_per_m2x2_div[] = {
|
||||
|
@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
|
|||
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
||||
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
||||
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
.round_rate = &omap2_clksel_round_rate,
|
||||
.set_rate = &omap2_clksel_set_rate,
|
||||
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
|
||||
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk dpll_per_m4x2_ck = {
|
||||
|
@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
|
|||
.set_rate = &omap2_clksel_set_rate,
|
||||
};
|
||||
|
||||
/* DPLL_UNIPRO */
|
||||
static struct dpll_data dpll_unipro_dd = {
|
||||
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
|
||||
.clk_bypass = &sys_clkin_ck,
|
||||
.clk_ref = &sys_clkin_ck,
|
||||
.control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
|
||||
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
||||
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
|
||||
.idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
|
||||
.mult_mask = OMAP4430_DPLL_MULT_MASK,
|
||||
.div1_mask = OMAP4430_DPLL_DIV_MASK,
|
||||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
||||
static struct clk dpll_unipro_ck = {
|
||||
.name = "dpll_unipro_ck",
|
||||
.parent = &sys_clkin_ck,
|
||||
.dpll_data = &dpll_unipro_dd,
|
||||
.init = &omap2_init_dpll_parent,
|
||||
.ops = &clkops_omap3_noncore_dpll_ops,
|
||||
.recalc = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
};
|
||||
|
||||
static struct clk dpll_unipro_x2_ck = {
|
||||
.name = "dpll_unipro_x2_ck",
|
||||
.parent = &dpll_unipro_ck,
|
||||
.flags = CLOCK_CLKOUTX2,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &omap3_clkoutx2_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel dpll_unipro_m2x2_div[] = {
|
||||
{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
static struct clk dpll_unipro_m2x2_ck = {
|
||||
.name = "dpll_unipro_m2x2_ck",
|
||||
.parent = &dpll_unipro_x2_ck,
|
||||
.clksel = dpll_unipro_m2x2_div,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
|
||||
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
|
||||
.ops = &clkops_omap4_dpllmx_ops,
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
.round_rate = &omap2_clksel_round_rate,
|
||||
.set_rate = &omap2_clksel_set_rate,
|
||||
};
|
||||
|
||||
static struct clk usb_hs_clk_div_ck = {
|
||||
.name = "usb_hs_clk_div_ck",
|
||||
.parent = &dpll_abe_m3x2_ck,
|
||||
|
@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
|
|||
.enable_mask = OMAP4430_DPLL_EN_MASK,
|
||||
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
|
||||
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
|
||||
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
|
||||
.max_divider = OMAP4430_MAX_DPLL_DIV,
|
||||
.sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
|
||||
.max_multiplier = 4095,
|
||||
.max_divider = 256,
|
||||
.min_divider = 1,
|
||||
};
|
||||
|
||||
|
@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
|
|||
static struct clk dpll_usb_clkdcoldo_ck = {
|
||||
.name = "dpll_usb_clkdcoldo_ck",
|
||||
.parent = &dpll_usb_ck,
|
||||
.ops = &clkops_omap4_dpllmx_ops,
|
||||
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
|
||||
.ops = &clkops_omap4_dpllmx_ops,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
|
@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
|
|||
.set_rate = &omap2_clksel_set_rate,
|
||||
};
|
||||
|
||||
static const struct clksel hsmmc6_fclk_sel[] = {
|
||||
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
||||
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
static struct clk hsmmc6_fclk = {
|
||||
.name = "hsmmc6_fclk",
|
||||
.parent = &func_64m_fclk,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel_rate div2_1to8_rates[] = {
|
||||
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
|
||||
{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
|
||||
|
@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
|
|||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static struct clk ocp_abe_iclk = {
|
||||
.name = "ocp_abe_iclk",
|
||||
.parent = &aess_fclk,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk per_abe_24m_fclk = {
|
||||
.name = "per_abe_24m_fclk",
|
||||
.parent = &dpll_abe_m2_ck,
|
||||
.ops = &clkops_null,
|
||||
.fixed_div = 4,
|
||||
.recalc = &omap_fixed_divisor_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel per_abe_nc_fclk_div[] = {
|
||||
{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
|
||||
{ .parent = NULL },
|
||||
|
@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
|
|||
.set_rate = &omap2_clksel_set_rate,
|
||||
};
|
||||
|
||||
static const struct clksel mcasp2_fclk_sel[] = {
|
||||
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
|
||||
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
static struct clk mcasp2_fclk = {
|
||||
.name = "mcasp2_fclk",
|
||||
.parent = &func_96m_fclk,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk mcasp3_fclk = {
|
||||
.name = "mcasp3_fclk",
|
||||
.parent = &func_96m_fclk,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk ocp_abe_iclk = {
|
||||
.name = "ocp_abe_iclk",
|
||||
.parent = &aess_fclk,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk per_abe_24m_fclk = {
|
||||
.name = "per_abe_24m_fclk",
|
||||
.parent = &dpll_abe_m2_ck,
|
||||
.ops = &clkops_null,
|
||||
.fixed_div = 4,
|
||||
.recalc = &omap_fixed_divisor_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel pmd_stm_clock_mux_sel[] = {
|
||||
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
|
||||
{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
|
||||
|
@ -1694,6 +1605,7 @@ static struct clk gpmc_ick = {
|
|||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
|
||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.parent = &l3_div_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
|
@ -1846,8 +1758,8 @@ static struct clk l3_instr_ick = {
|
|||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
|
||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.parent = &l3_div_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
@ -1857,8 +1769,8 @@ static struct clk l3_main_3_ick = {
|
|||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
|
||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.parent = &l3_div_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
@ -1995,10 +1907,16 @@ static struct clk mcbsp3_fck = {
|
|||
.clkdm_name = "abe_clkdm",
|
||||
};
|
||||
|
||||
static const struct clksel mcbsp4_sync_mux_sel[] = {
|
||||
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
|
||||
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
static struct clk mcbsp4_sync_mux_ck = {
|
||||
.name = "mcbsp4_sync_mux_ck",
|
||||
.parent = &func_96m_fclk,
|
||||
.clksel = mcasp2_fclk_sel,
|
||||
.clksel = mcbsp4_sync_mux_sel,
|
||||
.init = &omap2_init_clksel_parent,
|
||||
.clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
|
||||
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
|
||||
|
@ -2077,11 +1995,17 @@ static struct clk mcspi4_fck = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel hsmmc1_fclk_sel[] = {
|
||||
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
||||
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
/* Merged hsmmc1_fclk into mmc1 */
|
||||
static struct clk mmc1_fck = {
|
||||
.name = "mmc1_fck",
|
||||
.parent = &func_64m_fclk,
|
||||
.clksel = hsmmc6_fclk_sel,
|
||||
.clksel = hsmmc1_fclk_sel,
|
||||
.init = &omap2_init_clksel_parent,
|
||||
.clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
|
||||
.clksel_mask = OMAP4430_CLKSEL_MASK,
|
||||
|
@ -2096,7 +2020,7 @@ static struct clk mmc1_fck = {
|
|||
static struct clk mmc2_fck = {
|
||||
.name = "mmc2_fck",
|
||||
.parent = &func_64m_fclk,
|
||||
.clksel = hsmmc6_fclk_sel,
|
||||
.clksel = hsmmc1_fclk_sel,
|
||||
.init = &omap2_init_clksel_parent,
|
||||
.clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
|
||||
.clksel_mask = OMAP4430_CLKSEL_MASK,
|
||||
|
@ -2162,8 +2086,8 @@ static struct clk ocp_wp_noc_ick = {
|
|||
.ops = &clkops_omap2_dflt,
|
||||
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
|
||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.parent = &l3_div_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
@ -2895,6 +2819,7 @@ static struct clk auxclk2_ck = {
|
|||
.enable_reg = OMAP4_SCRM_AUXCLK2,
|
||||
.enable_bit = OMAP4_ENABLE_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk auxclk3_ck = {
|
||||
.name = "auxclk3_ck",
|
||||
.parent = &sys_clkin_ck,
|
||||
|
@ -3077,9 +3002,6 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
|
||||
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
|
||||
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
|
||||
CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
|
||||
CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
|
||||
CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
|
||||
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
|
||||
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
|
||||
|
@ -3092,17 +3014,14 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
|
||||
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
|
||||
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
|
||||
CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
|
||||
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
|
||||
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
|
||||
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
|
||||
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
|
||||
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
|
||||
CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
|
||||
CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
|
||||
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
|
||||
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
|
||||
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
|
||||
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
|
||||
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
|
||||
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
|
||||
|
@ -3114,10 +3033,10 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
|
||||
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
|
||||
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
|
||||
CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
|
||||
CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
|
||||
CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
|
||||
CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
|
||||
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
|
||||
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
|
||||
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
|
||||
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
|
||||
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
|
||||
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
|
||||
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
|
||||
|
@ -3204,7 +3123,6 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
|
||||
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
|
||||
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
|
||||
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
|
||||
CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
|
||||
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
|
||||
|
@ -3216,9 +3134,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
|
||||
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
|
||||
CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
|
||||
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
|
||||
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
|
||||
|
@ -3226,17 +3142,26 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
|
||||
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
|
||||
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
|
||||
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
|
||||
CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
|
||||
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
|
||||
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
|
||||
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
|
||||
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
|
||||
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
|
||||
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
|
||||
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
|
||||
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
|
||||
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
|
||||
|
@ -3253,6 +3178,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
|
||||
|
@ -3270,19 +3196,9 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
|
||||
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
|
||||
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
|
||||
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
|
||||
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
|
||||
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
|
||||
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
|
||||
};
|
||||
|
||||
int __init omap4xxx_clk_init(void)
|
||||
|
|
|
@ -1,11 +1,12 @@
|
|||
/*
|
||||
* OMAP4 Clock domains framework
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
* Copyright (C) 2009-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
*
|
||||
* Abhijit Pagare (abhijitpagare@ti.com)
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Paul Walmsley (paul@pwsan.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
|
@ -32,6 +33,42 @@
|
|||
|
||||
/* Static Dependencies for OMAP4 Clock Domains */
|
||||
|
||||
static struct clkdm_dep d2d_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
|
@ -116,42 +153,6 @@ static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
|
|||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
|
@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
|
|||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
|
||||
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
|
@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
|
|||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain mpuss_44xx_clkdm = {
|
||||
.name = "mpuss_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.prcm_partition = OMAP4430_CM1_PARTITION,
|
||||
.cm_inst = OMAP4430_CM1_MPU_INST,
|
||||
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
|
||||
.wkdep_srcs = mpuss_wkup_sleep_deps,
|
||||
.sleepdep_srcs = mpuss_wkup_sleep_deps,
|
||||
static struct clockdomain d2d_44xx_clkdm = {
|
||||
.name = "d2d_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.prcm_partition = OMAP4430_CM2_PARTITION,
|
||||
.cm_inst = OMAP4430_CM2_CORE_INST,
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
|
||||
.wkdep_srcs = d2d_wkup_sleep_deps,
|
||||
.sleepdep_srcs = d2d_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
|
|||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain mpu_44xx_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.prcm_partition = OMAP4430_CM1_PARTITION,
|
||||
.cm_inst = OMAP4430_CM1_MPU_INST,
|
||||
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
|
||||
.wkdep_srcs = mpu_wkup_sleep_deps,
|
||||
.sleepdep_srcs = mpu_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_2_44xx_clkdm = {
|
||||
.name = "l3_2_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
|
@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
|
|||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_d2d_44xx_clkdm = {
|
||||
.name = "l3_d2d_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.prcm_partition = OMAP4430_CM2_PARTITION,
|
||||
.cm_inst = OMAP4430_CM2_CORE_INST,
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
|
||||
.wkdep_srcs = l3_d2d_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l3_d2d_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain iss_44xx_clkdm = {
|
||||
.name = "iss_clkdm",
|
||||
.pwrdm = { .name = "cam_pwrdm" },
|
||||
|
@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
|
|||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* As clockdomains are added or removed above, this list must also be changed */
|
||||
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
||||
&l4_cefuse_44xx_clkdm,
|
||||
&l4_cfg_44xx_clkdm,
|
||||
|
@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
|||
&abe_44xx_clkdm,
|
||||
&l3_instr_44xx_clkdm,
|
||||
&l3_init_44xx_clkdm,
|
||||
&mpuss_44xx_clkdm,
|
||||
&d2d_44xx_clkdm,
|
||||
&mpu0_44xx_clkdm,
|
||||
&mpu1_44xx_clkdm,
|
||||
&l3_emif_44xx_clkdm,
|
||||
&l4_ao_44xx_clkdm,
|
||||
&ducati_44xx_clkdm,
|
||||
&mpu_44xx_clkdm,
|
||||
&l3_2_44xx_clkdm,
|
||||
&l3_1_44xx_clkdm,
|
||||
&l3_d2d_44xx_clkdm,
|
||||
&iss_44xx_clkdm,
|
||||
&l3_dss_44xx_clkdm,
|
||||
&l4_wkup_44xx_clkdm,
|
||||
&emu_sys_44xx_clkdm,
|
||||
&l3_dma_44xx_clkdm,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap44xx_clockdomains_init(void)
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* OMAP44xx CM1 instance offset macros
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley (paul@pwsan.com)
|
||||
|
@ -41,9 +41,9 @@
|
|||
#define OMAP4430_CM1_INSTR_INST 0x0f00
|
||||
|
||||
/* CM1 clockdomain register offsets (from instance start) */
|
||||
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
|
||||
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
|
||||
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
|
||||
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
|
||||
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
|
||||
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
|
||||
|
||||
/* CM1 */
|
||||
|
||||
|
@ -82,8 +82,8 @@
|
|||
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
|
||||
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
|
||||
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
|
||||
|
@ -98,8 +98,8 @@
|
|||
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
|
||||
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
|
||||
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
|
||||
|
@ -116,8 +116,8 @@
|
|||
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
|
||||
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
|
||||
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
|
||||
|
@ -134,8 +134,8 @@
|
|||
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
|
||||
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
|
||||
|
@ -154,8 +154,8 @@
|
|||
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
|
||||
|
@ -217,42 +217,6 @@
|
|||
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
|
||||
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
|
||||
|
||||
/* CM1.RESTORE_CM1 register offsets */
|
||||
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
|
||||
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
|
||||
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
|
||||
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
|
||||
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
|
||||
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
|
||||
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
|
||||
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
|
||||
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
|
||||
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
|
||||
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
|
||||
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
|
||||
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
|
||||
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
|
||||
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
|
||||
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
|
||||
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
|
||||
|
||||
/* Function prototypes */
|
||||
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
|
||||
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* OMAP44xx CM2 instance offset macros
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley (paul@pwsan.com)
|
||||
|
@ -40,9 +40,9 @@
|
|||
#define OMAP4430_CM2_CAM_INST 0x1000
|
||||
#define OMAP4430_CM2_DSS_INST 0x1100
|
||||
#define OMAP4430_CM2_GFX_INST 0x1200
|
||||
#define OMAP4430_CM2_L3INIT_INST 0x1300
|
||||
#define OMAP4430_CM2_L3INIT_INST 0x1300
|
||||
#define OMAP4430_CM2_L4PER_INST 0x1400
|
||||
#define OMAP4430_CM2_CEFUSE_INST 0x1600
|
||||
#define OMAP4430_CM2_CEFUSE_INST 0x1600
|
||||
#define OMAP4430_CM2_RESTORE_INST 0x1e00
|
||||
#define OMAP4430_CM2_INSTR_INST 0x1f00
|
||||
|
||||
|
@ -65,7 +65,6 @@
|
|||
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
|
||||
#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
|
||||
|
||||
|
||||
/* CM2 */
|
||||
|
||||
/* CM2.OCP_SOCKET_CM2 register offsets */
|
||||
|
@ -121,8 +120,8 @@
|
|||
#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
|
||||
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
|
||||
|
@ -135,8 +134,8 @@
|
|||
#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
|
||||
#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
|
||||
#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
|
||||
|
@ -151,8 +150,8 @@
|
|||
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
|
||||
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
|
||||
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
|
||||
|
||||
/* CM2.ALWAYS_ON_CM2 register offsets */
|
||||
#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
|
||||
|
@ -227,8 +226,8 @@
|
|||
#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
|
||||
#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
|
||||
#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
|
||||
#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
|
||||
#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
|
||||
#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
|
||||
#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
|
||||
#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
|
||||
#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
|
||||
#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
|
||||
|
@ -450,56 +449,6 @@
|
|||
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
|
||||
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
|
||||
|
||||
/* CM2.RESTORE_CM2 register offsets */
|
||||
#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
|
||||
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
|
||||
#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
|
||||
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
|
||||
#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
|
||||
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
|
||||
#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
|
||||
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
|
||||
#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
|
||||
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
|
||||
#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
|
||||
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
|
||||
#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
|
||||
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
|
||||
#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
|
||||
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
|
||||
#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
|
||||
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
|
||||
#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
|
||||
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
|
||||
#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
|
||||
#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
|
||||
#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
|
||||
#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
|
||||
#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
|
||||
#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
|
||||
#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
|
||||
#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
|
||||
#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
|
||||
#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
|
||||
#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
|
||||
#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
|
||||
#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
|
||||
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
|
||||
#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
|
||||
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
|
||||
#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
|
||||
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
|
||||
#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
|
||||
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
|
||||
#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
|
||||
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
|
||||
#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
|
||||
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
|
||||
#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
|
||||
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
|
||||
#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
|
||||
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
|
||||
|
||||
/* Function prototypes */
|
||||
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
|
||||
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
|
||||
|
|
|
@ -20,36 +20,15 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/ads7846.h>
|
||||
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/mcspi.h>
|
||||
#include <plat/nand.h>
|
||||
|
||||
#include "common-board-devices.h"
|
||||
|
||||
static struct i2c_board_info __initdata pmic_i2c_board_info = {
|
||||
.addr = 0x48,
|
||||
.flags = I2C_CLIENT_WAKE,
|
||||
};
|
||||
|
||||
void __init omap_pmic_init(int bus, u32 clkrate,
|
||||
const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
strncpy(pmic_i2c_board_info.type, pmic_type,
|
||||
sizeof(pmic_i2c_board_info.type));
|
||||
pmic_i2c_board_info.irq = pmic_irq;
|
||||
pmic_i2c_board_info.platform_data = pmic_data;
|
||||
|
||||
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
|
||||
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|
||||
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
|
||||
|
|
|
@ -1,33 +1,11 @@
|
|||
#ifndef __OMAP_COMMON_BOARD_DEVICES__
|
||||
#define __OMAP_COMMON_BOARD_DEVICES__
|
||||
|
||||
#include "twl-common.h"
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
|
||||
struct twl4030_platform_data;
|
||||
struct mtd_partition;
|
||||
|
||||
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data);
|
||||
|
||||
static inline void omap2_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
|
||||
}
|
||||
|
||||
static inline void omap3_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
|
||||
}
|
||||
|
||||
static inline void omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
|
||||
omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
|
||||
}
|
||||
|
||||
struct ads7846_platform_data;
|
||||
|
||||
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
|
||||
|
|
|
@ -21,9 +21,19 @@
|
|||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
/* In register I2C_CON, Bit 15 is the I2C enable bit */
|
||||
#define I2C_EN BIT(15)
|
||||
#define OMAP2_I2C_CON_OFFSET 0x24
|
||||
#define OMAP4_I2C_CON_OFFSET 0xA4
|
||||
|
||||
/* Maximum microseconds to wait for OMAP module to softreset */
|
||||
#define MAX_MODULE_SOFTRESET_WAIT 10000
|
||||
|
||||
void __init omap2_i2c_mux_pins(int bus_id)
|
||||
{
|
||||
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
|
||||
|
@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
|
|||
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
|
||||
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_i2c_reset - reset the omap i2c module.
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* The i2c moudle in omap2, omap3 had a special sequence to reset. The
|
||||
* sequence is:
|
||||
* - Disable the I2C.
|
||||
* - Write to SOFTRESET bit.
|
||||
* - Enable the I2C.
|
||||
* - Poll on the RESETDONE bit.
|
||||
* The sequence is implemented in below function. This is called for 2420,
|
||||
* 2430 and omap3.
|
||||
*/
|
||||
int omap_i2c_reset(struct omap_hwmod *oh)
|
||||
{
|
||||
u32 v;
|
||||
u16 i2c_con;
|
||||
int c = 0;
|
||||
|
||||
if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
|
||||
i2c_con = OMAP4_I2C_CON_OFFSET;
|
||||
} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
|
||||
i2c_con = OMAP2_I2C_CON_OFFSET;
|
||||
} else {
|
||||
WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
|
||||
oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Disable I2C */
|
||||
v = omap_hwmod_read(oh, i2c_con);
|
||||
v &= ~I2C_EN;
|
||||
omap_hwmod_write(v, oh, i2c_con);
|
||||
|
||||
/* Write to the SOFTRESET bit */
|
||||
omap_hwmod_softreset(oh);
|
||||
|
||||
/* Enable I2C */
|
||||
v = omap_hwmod_read(oh, i2c_con);
|
||||
v |= I2C_EN;
|
||||
omap_hwmod_write(v, oh, i2c_con);
|
||||
|
||||
/* Poll on RESETDONE bit */
|
||||
omap_test_timeout((omap_hwmod_read(oh,
|
||||
oh->class->sysc->syss_offs)
|
||||
& SYSS_RESETDONE_MASK),
|
||||
MAX_MODULE_SOFTRESET_WAIT, c);
|
||||
|
||||
if (c == MAX_MODULE_SOFTRESET_WAIT)
|
||||
pr_warning("%s: %s: softreset failed (waited %d usec)\n",
|
||||
__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
|
||||
else
|
||||
pr_debug("%s: %s: softreset in %d usec\n", __func__,
|
||||
oh->name, c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* omap_hwmod implementation for OMAP2/3/4
|
||||
*
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
* Copyright (C) 2011 Texas Instruments, Inc.
|
||||
*
|
||||
* Paul Walmsley, Benoît Cousson, Kevin Hilman
|
||||
*
|
||||
|
@ -387,11 +388,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
|
|||
*/
|
||||
static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
|
||||
{
|
||||
u32 wakeup_mask;
|
||||
|
||||
if (!oh->class->sysc ||
|
||||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
|
||||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
|
||||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
|
||||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
|
||||
return -EINVAL;
|
||||
|
||||
if (!oh->class->sysc->sysc_fields) {
|
||||
|
@ -399,12 +399,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
|
||||
|
||||
*v |= wakeup_mask;
|
||||
if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
|
||||
*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
|
||||
|
||||
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
|
||||
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
|
||||
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
|
||||
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
|
||||
|
||||
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
|
||||
|
||||
|
@ -422,11 +423,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
|
|||
*/
|
||||
static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
|
||||
{
|
||||
u32 wakeup_mask;
|
||||
|
||||
if (!oh->class->sysc ||
|
||||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
|
||||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
|
||||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
|
||||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
|
||||
return -EINVAL;
|
||||
|
||||
if (!oh->class->sysc->sysc_fields) {
|
||||
|
@ -434,12 +434,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
|
||||
|
||||
*v &= ~wakeup_mask;
|
||||
if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
|
||||
*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
|
||||
|
||||
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
|
||||
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
|
||||
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
|
||||
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
|
||||
|
||||
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
|
||||
|
||||
|
@ -677,6 +678,75 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
|
||||
* @oh: struct omap_hwmod *oh
|
||||
*
|
||||
* Count and return the number of MPU IRQs associated with the hwmod
|
||||
* @oh. Used to allocate struct resource data. Returns 0 if @oh is
|
||||
* NULL.
|
||||
*/
|
||||
static int _count_mpu_irqs(struct omap_hwmod *oh)
|
||||
{
|
||||
struct omap_hwmod_irq_info *ohii;
|
||||
int i = 0;
|
||||
|
||||
if (!oh || !oh->mpu_irqs)
|
||||
return 0;
|
||||
|
||||
do {
|
||||
ohii = &oh->mpu_irqs[i++];
|
||||
} while (ohii->irq != -1);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/**
|
||||
* _count_sdma_reqs - count the number of SDMA request lines associated with @oh
|
||||
* @oh: struct omap_hwmod *oh
|
||||
*
|
||||
* Count and return the number of SDMA request lines associated with
|
||||
* the hwmod @oh. Used to allocate struct resource data. Returns 0
|
||||
* if @oh is NULL.
|
||||
*/
|
||||
static int _count_sdma_reqs(struct omap_hwmod *oh)
|
||||
{
|
||||
struct omap_hwmod_dma_info *ohdi;
|
||||
int i = 0;
|
||||
|
||||
if (!oh || !oh->sdma_reqs)
|
||||
return 0;
|
||||
|
||||
do {
|
||||
ohdi = &oh->sdma_reqs[i++];
|
||||
} while (ohdi->dma_req != -1);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/**
|
||||
* _count_ocp_if_addr_spaces - count the number of address space entries for @oh
|
||||
* @oh: struct omap_hwmod *oh
|
||||
*
|
||||
* Count and return the number of address space ranges associated with
|
||||
* the hwmod @oh. Used to allocate struct resource data. Returns 0
|
||||
* if @oh is NULL.
|
||||
*/
|
||||
static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
|
||||
{
|
||||
struct omap_hwmod_addr_space *mem;
|
||||
int i = 0;
|
||||
|
||||
if (!os || !os->addr)
|
||||
return 0;
|
||||
|
||||
do {
|
||||
mem = &os->addr[i++];
|
||||
} while (mem->pa_start != mem->pa_end);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/**
|
||||
* _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
|
||||
* @oh: struct omap_hwmod *
|
||||
|
@ -722,8 +792,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
|
|||
{
|
||||
struct omap_hwmod_ocp_if *os;
|
||||
struct omap_hwmod_addr_space *mem;
|
||||
int i;
|
||||
int found = 0;
|
||||
int i = 0, found = 0;
|
||||
void __iomem *va_start;
|
||||
|
||||
if (!oh || oh->slaves_cnt == 0)
|
||||
|
@ -731,12 +800,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
|
|||
|
||||
os = oh->slaves[index];
|
||||
|
||||
for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
|
||||
if (mem->flags & ADDR_TYPE_RT) {
|
||||
if (!os->addr)
|
||||
return NULL;
|
||||
|
||||
do {
|
||||
mem = &os->addr[i++];
|
||||
if (mem->flags & ADDR_TYPE_RT)
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} while (!found && mem->pa_start != mem->pa_end);
|
||||
|
||||
if (found) {
|
||||
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
|
||||
|
@ -781,8 +852,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
|
|||
}
|
||||
|
||||
if (sf & SYSC_HAS_MIDLEMODE) {
|
||||
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
|
||||
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
|
||||
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
|
||||
idlemode = HWMOD_IDLEMODE_NO;
|
||||
} else {
|
||||
if (sf & SYSC_HAS_ENAWAKEUP)
|
||||
_enable_wakeup(oh, &v);
|
||||
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
|
||||
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
|
||||
else
|
||||
idlemode = HWMOD_IDLEMODE_SMART;
|
||||
}
|
||||
_set_master_standbymode(oh, idlemode, &v);
|
||||
}
|
||||
|
||||
|
@ -840,8 +919,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
|
|||
}
|
||||
|
||||
if (sf & SYSC_HAS_MIDLEMODE) {
|
||||
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
|
||||
HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
|
||||
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
|
||||
idlemode = HWMOD_IDLEMODE_FORCE;
|
||||
} else {
|
||||
if (sf & SYSC_HAS_ENAWAKEUP)
|
||||
_enable_wakeup(oh, &v);
|
||||
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
|
||||
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
|
||||
else
|
||||
idlemode = HWMOD_IDLEMODE_SMART;
|
||||
}
|
||||
_set_master_standbymode(oh, idlemode, &v);
|
||||
}
|
||||
|
||||
|
@ -928,6 +1015,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
|
|||
|
||||
if (!ret)
|
||||
oh->_state = _HWMOD_STATE_CLKS_INITED;
|
||||
else
|
||||
pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -1224,6 +1313,8 @@ static int _enable(struct omap_hwmod *oh)
|
|||
{
|
||||
int r;
|
||||
|
||||
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
|
||||
|
||||
if (oh->_state != _HWMOD_STATE_INITIALIZED &&
|
||||
oh->_state != _HWMOD_STATE_IDLE &&
|
||||
oh->_state != _HWMOD_STATE_DISABLED) {
|
||||
|
@ -1232,17 +1323,6 @@ static int _enable(struct omap_hwmod *oh)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
|
||||
|
||||
/*
|
||||
* If an IP contains only one HW reset line, then de-assert it in order
|
||||
* to allow to enable the clocks. Otherwise the PRCM will return
|
||||
* Intransition status, and the init will failed.
|
||||
*/
|
||||
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
|
||||
oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
|
||||
_deassert_hardreset(oh, oh->rst_lines[0].name);
|
||||
|
||||
/* Mux pins for device runtime if populated */
|
||||
if (oh->mux && (!oh->mux->enabled ||
|
||||
((oh->_state == _HWMOD_STATE_IDLE) &&
|
||||
|
@ -1252,20 +1332,31 @@ static int _enable(struct omap_hwmod *oh)
|
|||
_add_initiator_dep(oh, mpu_oh);
|
||||
_enable_clocks(oh);
|
||||
|
||||
r = _wait_target_ready(oh);
|
||||
if (!r) {
|
||||
oh->_state = _HWMOD_STATE_ENABLED;
|
||||
/*
|
||||
* If an IP contains only one HW reset line, then de-assert it in order
|
||||
* to allow the module state transition. Otherwise the PRCM will return
|
||||
* Intransition status, and the init will failed.
|
||||
*/
|
||||
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
|
||||
oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
|
||||
_deassert_hardreset(oh, oh->rst_lines[0].name);
|
||||
|
||||
/* Access the sysconfig only if the target is ready */
|
||||
if (oh->class->sysc) {
|
||||
if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
|
||||
_update_sysc_cache(oh);
|
||||
_enable_sysc(oh);
|
||||
}
|
||||
} else {
|
||||
_disable_clocks(oh);
|
||||
r = _wait_target_ready(oh);
|
||||
if (r) {
|
||||
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
|
||||
oh->name, r);
|
||||
_disable_clocks(oh);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
oh->_state = _HWMOD_STATE_ENABLED;
|
||||
|
||||
/* Access the sysconfig only if the target is ready */
|
||||
if (oh->class->sysc) {
|
||||
if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
|
||||
_update_sysc_cache(oh);
|
||||
_enable_sysc(oh);
|
||||
}
|
||||
|
||||
return r;
|
||||
|
@ -1281,14 +1372,14 @@ static int _enable(struct omap_hwmod *oh)
|
|||
*/
|
||||
static int _idle(struct omap_hwmod *oh)
|
||||
{
|
||||
pr_debug("omap_hwmod: %s: idling\n", oh->name);
|
||||
|
||||
if (oh->_state != _HWMOD_STATE_ENABLED) {
|
||||
WARN(1, "omap_hwmod: %s: idle state can only be entered from "
|
||||
"enabled state\n", oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_debug("omap_hwmod: %s: idling\n", oh->name);
|
||||
|
||||
if (oh->class->sysc)
|
||||
_idle_sysc(oh);
|
||||
_del_initiator_dep(oh, mpu_oh);
|
||||
|
@ -1374,15 +1465,11 @@ static int _shutdown(struct omap_hwmod *oh)
|
|||
}
|
||||
}
|
||||
|
||||
if (oh->class->sysc)
|
||||
if (oh->class->sysc) {
|
||||
if (oh->_state == _HWMOD_STATE_IDLE)
|
||||
_enable(oh);
|
||||
_shutdown_sysc(oh);
|
||||
|
||||
/*
|
||||
* If an IP contains only one HW reset line, then assert it
|
||||
* before disabling the clocks and shutting down the IP.
|
||||
*/
|
||||
if (oh->rst_lines_cnt == 1)
|
||||
_assert_hardreset(oh, oh->rst_lines[0].name);
|
||||
}
|
||||
|
||||
/* clocks and deps are already disabled in idle */
|
||||
if (oh->_state == _HWMOD_STATE_ENABLED) {
|
||||
|
@ -1392,6 +1479,13 @@ static int _shutdown(struct omap_hwmod *oh)
|
|||
}
|
||||
/* XXX Should this code also force-disable the optional clocks? */
|
||||
|
||||
/*
|
||||
* If an IP contains only one HW reset line, then assert it
|
||||
* after disabling the clocks and before shutting down the IP.
|
||||
*/
|
||||
if (oh->rst_lines_cnt == 1)
|
||||
_assert_hardreset(oh, oh->rst_lines[0].name);
|
||||
|
||||
/* Mux pins to safe mode or use populated off mode values */
|
||||
if (oh->mux)
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
|
||||
|
@ -1561,6 +1655,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
|
|||
__raw_writel(v, oh->_mpu_rt_va + reg_offs);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* This is a public function exposed to drivers. Some drivers may need to do
|
||||
* some settings before and after resetting the device. Those drivers after
|
||||
* doing the necessary settings could use this function to start a reset by
|
||||
* setting the SYSCONFIG.SOFTRESET bit.
|
||||
*/
|
||||
int omap_hwmod_softreset(struct omap_hwmod *oh)
|
||||
{
|
||||
u32 v;
|
||||
int ret;
|
||||
|
||||
if (!oh || !(oh->_sysc_cache))
|
||||
return -EINVAL;
|
||||
|
||||
v = oh->_sysc_cache;
|
||||
ret = _set_softreset(oh, &v);
|
||||
if (ret)
|
||||
goto error;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
|
||||
* @oh: struct omap_hwmod *
|
||||
|
@ -1685,9 +1806,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
|
|||
return 0;
|
||||
|
||||
oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
|
||||
if (!oh->_mpu_rt_va)
|
||||
pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
|
||||
__func__, oh->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1939,10 +2057,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
|
|||
{
|
||||
int ret, i;
|
||||
|
||||
ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
|
||||
ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
|
||||
|
||||
for (i = 0; i < oh->slaves_cnt; i++)
|
||||
ret += oh->slaves[i]->addr_cnt;
|
||||
ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -1959,12 +2077,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
|
|||
*/
|
||||
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
|
||||
{
|
||||
int i, j;
|
||||
int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
|
||||
int r = 0;
|
||||
|
||||
/* For each IRQ, DMA, memory area, fill in array.*/
|
||||
|
||||
for (i = 0; i < oh->mpu_irqs_cnt; i++) {
|
||||
mpu_irqs_cnt = _count_mpu_irqs(oh);
|
||||
for (i = 0; i < mpu_irqs_cnt; i++) {
|
||||
(res + r)->name = (oh->mpu_irqs + i)->name;
|
||||
(res + r)->start = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->end = (oh->mpu_irqs + i)->irq;
|
||||
|
@ -1972,7 +2091,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
|
|||
r++;
|
||||
}
|
||||
|
||||
for (i = 0; i < oh->sdma_reqs_cnt; i++) {
|
||||
sdma_reqs_cnt = _count_sdma_reqs(oh);
|
||||
for (i = 0; i < sdma_reqs_cnt; i++) {
|
||||
(res + r)->name = (oh->sdma_reqs + i)->name;
|
||||
(res + r)->start = (oh->sdma_reqs + i)->dma_req;
|
||||
(res + r)->end = (oh->sdma_reqs + i)->dma_req;
|
||||
|
@ -1982,10 +2102,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
|
|||
|
||||
for (i = 0; i < oh->slaves_cnt; i++) {
|
||||
struct omap_hwmod_ocp_if *os;
|
||||
int addr_cnt;
|
||||
|
||||
os = oh->slaves[i];
|
||||
addr_cnt = _count_ocp_if_addr_spaces(os);
|
||||
|
||||
for (j = 0; j < os->addr_cnt; j++) {
|
||||
for (j = 0; j < addr_cnt; j++) {
|
||||
(res + r)->name = (os->addr + j)->name;
|
||||
(res + r)->start = (os->addr + j)->pa_start;
|
||||
(res + r)->end = (os->addr + j)->pa_end;
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
|
||||
*
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* XXX handle crossbar/shared link difference for L3?
|
||||
* XXX these should be marked initdata for multi-OMAP kernels
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809c000,
|
||||
.pa_end = 0x4809c1ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b4000,
|
||||
.pa_end = 0x480b41ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48070000,
|
||||
.pa_end = 0x48070000 + SZ_128 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48072000,
|
||||
.pa_end = 0x48072000 + SZ_128 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050000,
|
||||
.pa_end = 0x48050000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050400,
|
||||
.pa_end = 0x48050400 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050800,
|
||||
.pa_end = 0x48050800 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050C00,
|
||||
.pa_end = 0x48050C00 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48086000,
|
||||
.pa_end = 0x48086000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48088000,
|
||||
.pa_end = 0x48088000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4808a000,
|
||||
.pa_end = 0x4808a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48098000,
|
||||
.pa_end = 0x48098000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809a000,
|
||||
.pa_end = 0x4809a000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b8000,
|
||||
.pa_end = 0x480b8000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x48056000 + SZ_4K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48094000,
|
||||
.pa_end = 0x48094000 + SZ_512 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48074000,
|
||||
.pa_end = 0x480740ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
|
@ -0,0 +1,322 @@
|
|||
/*
|
||||
* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
|
||||
*
|
||||
* Copyright (C) 2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/dma.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
/* UART */
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
|
||||
.rev_offs = 0x50,
|
||||
.sysc_offs = 0x54,
|
||||
.syss_offs = 0x58,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_uart_class = {
|
||||
.name = "uart",
|
||||
.sysc = &omap2_uart_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dss' class
|
||||
* display sub-system
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_dss_hwmod_class = {
|
||||
.name = "dss",
|
||||
.sysc = &omap2_dss_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dispc' class
|
||||
* display controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_dispc_hwmod_class = {
|
||||
.name = "dispc",
|
||||
.sysc = &omap2_dispc_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'rfbi' class
|
||||
* remote frame buffer interface
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
|
||||
.name = "rfbi",
|
||||
.sysc = &omap2_rfbi_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'venc' class
|
||||
* video encoder
|
||||
*/
|
||||
|
||||
struct omap_hwmod_class omap2_venc_hwmod_class = {
|
||||
.name = "venc",
|
||||
};
|
||||
|
||||
|
||||
/* Common DMA request line data */
|
||||
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
|
||||
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
|
||||
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
|
||||
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
|
||||
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
|
||||
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
|
||||
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
|
||||
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
|
||||
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
|
||||
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
|
||||
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
|
||||
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
|
||||
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
|
||||
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
|
||||
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
|
||||
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
|
||||
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
|
||||
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
|
||||
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
|
||||
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = 32 },
|
||||
{ .name = "tx", .dma_req = 31 },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = 34 },
|
||||
{ .name = "tx", .dma_req = 33 },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
|
||||
{ .name = "rx", .dma_req = 18 },
|
||||
{ .name = "tx", .dma_req = 17 },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
|
||||
/* Other IP block data */
|
||||
|
||||
|
||||
/*
|
||||
* omap_hwmod class data
|
||||
*/
|
||||
|
||||
struct omap_hwmod_class l3_hwmod_class = {
|
||||
.name = "l3"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class l4_hwmod_class = {
|
||||
.name = "l4"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class mpu_hwmod_class = {
|
||||
.name = "mpu"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class iva_hwmod_class = {
|
||||
.name = "iva"
|
||||
};
|
||||
|
||||
/* Common MPU IRQ line data */
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
|
||||
{ .irq = 37, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
|
||||
{ .irq = 38, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
|
||||
{ .irq = 39, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
|
||||
{ .irq = 40, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
|
||||
{ .irq = 41, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
|
||||
{ .irq = 42, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
|
||||
{ .irq = 43, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
|
||||
{ .irq = 44, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
|
||||
{ .irq = 45, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART3_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
|
||||
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
|
||||
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
|
||||
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
|
||||
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
|
||||
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
|
||||
{ .irq = 65 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
|
||||
{ .irq = 66 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
|
||||
*
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* XXX handle crossbar/shared link difference for L3?
|
||||
* XXX these should be marked initdata for multi-OMAP kernels
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART1_BASE,
|
||||
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART2_BASE,
|
||||
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART3_BASE,
|
||||
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4802a000,
|
||||
.pa_end = 0x4802a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48078000,
|
||||
.pa_end = 0x48078000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807a000,
|
||||
.pa_end = 0x4807a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807c000,
|
||||
.pa_end = 0x4807c000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807e000,
|
||||
.pa_end = 0x4807e000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48080000,
|
||||
.pa_end = 0x48080000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48082000,
|
||||
.pa_end = 0x48082000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48084000,
|
||||
.pa_end = 0x48084000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48076000,
|
||||
.pa_end = 0x480760ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
|
||||
*
|
||||
* Copyright (C) 2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dmtimer.h>
|
||||
#include <plat/mcspi.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "wd_timer.h"
|
||||
|
||||
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
|
||||
{ .irq = 48, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
|
||||
{ .name = "dispc", .dma_req = 5 },
|
||||
{ .dma_req = -1 }
|
||||
};
|
||||
/* OMAP2xxx Timer Common */
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
|
||||
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
|
||||
.name = "timer",
|
||||
.sysc = &omap2xxx_timer_sysc,
|
||||
.rev = OMAP_TIMER_IP_VERSION_1,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'wd_timer' class
|
||||
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
|
||||
* overflow condition
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
|
||||
.name = "wd_timer",
|
||||
.sysc = &omap2xxx_wd_timer_sysc,
|
||||
.pre_shutdown = &omap2_wd_timer_disable
|
||||
};
|
||||
|
||||
/*
|
||||
* 'gpio' class
|
||||
* general purpose io module
|
||||
*/
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
||||
SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
|
||||
.name = "gpio",
|
||||
.sysc = &omap2xxx_gpio_sysc,
|
||||
.rev = 0,
|
||||
};
|
||||
|
||||
/* system dma */
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x002c,
|
||||
.syss_offs = 0x0028,
|
||||
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
|
||||
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
|
||||
.name = "dma",
|
||||
.sysc = &omap2xxx_dma_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mailbox' class
|
||||
* mailbox module allowing communication between the on-chip processors
|
||||
* using a queued mailbox-interrupt mechanism.
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
|
||||
.rev_offs = 0x000,
|
||||
.sysc_offs = 0x010,
|
||||
.syss_offs = 0x014,
|
||||
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
|
||||
.name = "mailbox",
|
||||
.sysc = &omap2xxx_mailbox_sysc,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mcspi' class
|
||||
* multichannel serial port interface (mcspi) / master/slave synchronous serial
|
||||
* bus
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class omap2xxx_mcspi_class = {
|
||||
.name = "mcspi",
|
||||
.sysc = &omap2xxx_mcspi_sysc,
|
||||
.rev = OMAP2_MCSPI_REV,
|
||||
};
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
|
|||
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* omap_hwmod class data
|
||||
*/
|
||||
|
||||
struct omap_hwmod_class l3_hwmod_class = {
|
||||
.name = "l3"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class l4_hwmod_class = {
|
||||
.name = "l4"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class mpu_hwmod_class = {
|
||||
.name = "mpu"
|
||||
};
|
||||
|
||||
struct omap_hwmod_class iva_hwmod_class = {
|
||||
.name = "iva"
|
||||
};
|
||||
|
|
|
@ -1,10 +1,10 @@
|
|||
/*
|
||||
* omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
|
||||
*
|
||||
* Copyright (C) 2010 Nokia Corporation
|
||||
* Copyright (C) 2010-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2010-2011 Texas Instruments, Inc.
|
||||
* Benoît Cousson
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
|
@ -16,10 +16,99 @@
|
|||
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
/* Common address space across OMAP2xxx */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
|
||||
|
||||
/* Common address space across OMAP2xxx/3xxx */
|
||||
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
|
||||
|
||||
/* Common IP block data across OMAP2xxx */
|
||||
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
|
||||
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
|
||||
|
||||
/* Common IP block data */
|
||||
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
|
||||
extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
|
||||
|
||||
/* Common IP block data on OMAP2430/OMAP3 */
|
||||
extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
|
||||
|
||||
/* Common IP block data across OMAP2/3 */
|
||||
extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
|
||||
|
||||
/* OMAP hwmod classes - forward declarations */
|
||||
extern struct omap_hwmod_class l3_hwmod_class;
|
||||
extern struct omap_hwmod_class l4_hwmod_class;
|
||||
extern struct omap_hwmod_class mpu_hwmod_class;
|
||||
extern struct omap_hwmod_class iva_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2_uart_class;
|
||||
extern struct omap_hwmod_class omap2_dss_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2_venc_hwmod_class;
|
||||
|
||||
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
|
||||
extern struct omap_hwmod_class omap2xxx_mcspi_class;
|
||||
|
||||
#endif
|
||||
|
|
|
@ -106,7 +106,7 @@ static void omap2_init_processor_devices(void)
|
|||
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
||||
{
|
||||
u32 cur_state;
|
||||
int sleep_switch = 0;
|
||||
int sleep_switch = -1;
|
||||
int ret = 0;
|
||||
|
||||
if (pwrdm == NULL || IS_ERR(pwrdm))
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* OMAP4 Power domains framework
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
*
|
||||
* Abhijit Pagare (abhijitpagare@ti.com)
|
||||
|
@ -41,19 +41,19 @@ static struct powerdomain core_44xx_pwrdm = {
|
|||
.banks = 5,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF, /* core_nret_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* core_ocmram */
|
||||
[1] = PWRSTS_RET, /* core_ocmram */
|
||||
[2] = PWRSTS_RET, /* core_other_bank */
|
||||
[3] = PWRSTS_OFF_RET, /* ducati_l2ram */
|
||||
[4] = PWRSTS_OFF_RET, /* ducati_unicache */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* core_nret_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* core_ocmram */
|
||||
[1] = PWRSTS_ON, /* core_ocmram */
|
||||
[2] = PWRSTS_ON, /* core_other_bank */
|
||||
[3] = PWRSTS_ON, /* ducati_l2ram */
|
||||
[4] = PWRSTS_ON, /* ducati_unicache */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* gfx_44xx_pwrdm: 3D accelerator power domain */
|
||||
|
@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
|
|||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gfx_mem */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* abe_44xx_pwrdm: Audio back end power domain */
|
||||
|
@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
|
|||
[0] = PWRSTS_ON, /* aessmem */
|
||||
[1] = PWRSTS_ON, /* periphmem */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* dss_44xx_pwrdm: Display subsystem power domain */
|
||||
|
@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
|
|||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dss_mem */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* tesla_44xx_pwrdm: Tesla processor power domain */
|
||||
|
@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
|
|||
[1] = PWRSTS_ON, /* tesla_l1 */
|
||||
[2] = PWRSTS_ON, /* tesla_l2 */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* wkup_44xx_pwrdm: Wake-up power domain */
|
||||
|
@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
|
|||
.prcm_offs = OMAP4430_PRM_MPU_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
|
@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
|
|||
[2] = PWRSTS_ON, /* tcm1_mem */
|
||||
[3] = PWRSTS_ON, /* tcm2_mem */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* cam_44xx_pwrdm: Camera subsystem power domain */
|
||||
|
@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
|
|||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* cam_mem */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
|
||||
|
@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
|
|||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* l3init_bank1 */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/* l4per_44xx_pwrdm: Target peripherals power domain */
|
||||
|
@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
|
|||
[0] = PWRSTS_ON, /* nonretained_bank */
|
||||
[1] = PWRSTS_ON, /* retained_bank */
|
||||
},
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
|
|||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
|
||||
|
||||
/* PRCM_MPU instances */
|
||||
|
||||
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
|
||||
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
|
||||
#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
|
||||
|
@ -52,46 +51,46 @@
|
|||
*/
|
||||
|
||||
/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
|
||||
#define OMAP4_REVISION_PRCM_OFFSET 0x0000
|
||||
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
|
||||
#define OMAP4_REVISION_PRCM_OFFSET 0x0000
|
||||
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
|
||||
|
||||
/* PRCM_MPU.DEVICE_PRM register offsets */
|
||||
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
|
||||
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
|
||||
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
|
||||
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
|
||||
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
|
||||
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
|
||||
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
|
||||
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
|
||||
|
||||
/* PRCM_MPU.CPU0 register offsets */
|
||||
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
|
||||
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
|
||||
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
|
||||
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
|
||||
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
|
||||
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
|
||||
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
|
||||
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
|
||||
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
|
||||
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
|
||||
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
|
||||
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
|
||||
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
|
||||
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
|
||||
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
|
||||
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
|
||||
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
|
||||
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
|
||||
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
|
||||
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
|
||||
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
|
||||
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
|
||||
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
|
||||
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
|
||||
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
|
||||
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
|
||||
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
|
||||
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
|
||||
|
||||
/* PRCM_MPU.CPU1 register offsets */
|
||||
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
|
||||
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
|
||||
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
|
||||
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
|
||||
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
|
||||
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
|
||||
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
|
||||
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
|
||||
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
|
||||
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
|
||||
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
|
||||
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
|
||||
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
|
||||
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
|
||||
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
|
||||
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
|
||||
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
|
||||
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
|
||||
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
|
||||
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
|
||||
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
|
||||
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
|
||||
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
|
||||
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
|
||||
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
|
||||
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
|
||||
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
|
||||
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
|
||||
|
||||
/* Function prototypes */
|
||||
# ifndef __ASSEMBLER__
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#define OMAP4430_PRM_BASE 0x4a306000
|
||||
|
||||
#define OMAP44XX_PRM_REGADDR(inst, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
|
||||
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
|
||||
|
||||
|
||||
/* PRM instances */
|
||||
|
@ -46,30 +46,18 @@
|
|||
#define OMAP4430_PRM_CAM_INST 0x1000
|
||||
#define OMAP4430_PRM_DSS_INST 0x1100
|
||||
#define OMAP4430_PRM_GFX_INST 0x1200
|
||||
#define OMAP4430_PRM_L3INIT_INST 0x1300
|
||||
#define OMAP4430_PRM_L3INIT_INST 0x1300
|
||||
#define OMAP4430_PRM_L4PER_INST 0x1400
|
||||
#define OMAP4430_PRM_CEFUSE_INST 0x1600
|
||||
#define OMAP4430_PRM_CEFUSE_INST 0x1600
|
||||
#define OMAP4430_PRM_WKUP_INST 0x1700
|
||||
#define OMAP4430_PRM_WKUP_CM_INST 0x1800
|
||||
#define OMAP4430_PRM_EMU_INST 0x1900
|
||||
#define OMAP4430_PRM_EMU_CM_INST 0x1a00
|
||||
#define OMAP4430_PRM_DEVICE_INST 0x1b00
|
||||
#define OMAP4430_PRM_EMU_CM_INST 0x1a00
|
||||
#define OMAP4430_PRM_DEVICE_INST 0x1b00
|
||||
#define OMAP4430_PRM_INSTR_INST 0x1f00
|
||||
|
||||
/* PRM clockdomain register offsets (from instance start) */
|
||||
#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
|
||||
#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
|
||||
|
||||
/* OMAP4 specific register offsets */
|
||||
|
@ -247,8 +235,8 @@
|
|||
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
|
||||
#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
|
||||
#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
|
||||
#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
|
||||
#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
|
||||
#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
|
||||
#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
|
||||
#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
|
||||
#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
|
||||
#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
|
||||
|
@ -713,8 +701,8 @@
|
|||
#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
|
||||
#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
|
||||
#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
|
||||
#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
|
||||
#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
|
||||
#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
|
||||
#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
|
||||
#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
|
||||
#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
|
||||
#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
|
||||
|
@ -751,8 +739,8 @@
|
|||
#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
|
||||
#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
|
||||
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
|
||||
#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
|
||||
#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
|
||||
#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
|
||||
#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
|
||||
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
|
||||
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
|
||||
|
||||
|
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* twl-common.c
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments, Inc..
|
||||
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "twl-common.h"
|
||||
|
||||
static struct i2c_board_info __initdata pmic_i2c_board_info = {
|
||||
.addr = 0x48,
|
||||
.flags = I2C_CLIENT_WAKE,
|
||||
};
|
||||
|
||||
void __init omap_pmic_init(int bus, u32 clkrate,
|
||||
const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
strncpy(pmic_i2c_board_info.type, pmic_type,
|
||||
sizeof(pmic_i2c_board_info.type));
|
||||
pmic_i2c_board_info.irq = pmic_irq;
|
||||
pmic_i2c_board_info.platform_data = pmic_data;
|
||||
|
||||
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
|
||||
}
|
||||
|
||||
static struct twl4030_usb_data omap4_usb_pdata = {
|
||||
.phy_init = omap4430_phy_init,
|
||||
.phy_exit = omap4430_phy_exit,
|
||||
.phy_power = omap4430_phy_power,
|
||||
.phy_set_clock = omap4430_phy_set_clk,
|
||||
.phy_suspend = omap4430_phy_suspend,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap3_usb_pdata = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static int omap3_batt_table[] = {
|
||||
/* 0 C */
|
||||
30800, 29500, 28300, 27100,
|
||||
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
|
||||
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
|
||||
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
|
||||
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
|
||||
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
|
||||
4040, 3910, 3790, 3670, 3550
|
||||
};
|
||||
|
||||
static struct twl4030_bci_platform_data omap3_bci_pdata = {
|
||||
.battery_tmp_tbl = omap3_batt_table,
|
||||
.tblsize = ARRAY_SIZE(omap3_batt_table),
|
||||
};
|
||||
|
||||
static struct twl4030_madc_platform_data omap3_madc_pdata = {
|
||||
.irq_line = 1,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data omap3_audio;
|
||||
|
||||
static struct twl4030_codec_data omap3_codec_pdata = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &omap3_audio,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap3_vdac_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
|
||||
.consumer_supplies = omap3_vdda_dac_supplies,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
|
||||
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap3_vpll2_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
|
||||
.consumer_supplies = omap3_vpll2_supplies,
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vdac_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vaux2_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vaux3_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1000000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply omap4_vmmc_supply[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
|
||||
};
|
||||
|
||||
/* VMMC1 for MMC1 card */
|
||||
static struct regulator_init_data omap4_vmmc_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
|
||||
.consumer_supplies = omap4_vmmc_supply,
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vpp_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 2500000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vana_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 2100000,
|
||||
.max_uV = 2100000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vcxio_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_vusb_idata = {
|
||||
.constraints = {
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = true,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data omap4_clk32kg_idata = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
};
|
||||
|
||||
void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
|
||||
u32 pdata_flags, u32 regulators_flags)
|
||||
{
|
||||
if (!pmic_data->irq_base)
|
||||
pmic_data->irq_base = TWL6030_IRQ_BASE;
|
||||
if (!pmic_data->irq_end)
|
||||
pmic_data->irq_end = TWL6030_IRQ_END;
|
||||
|
||||
/* Common platform data configurations */
|
||||
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
|
||||
pmic_data->usb = &omap4_usb_pdata;
|
||||
|
||||
/* Common regulator configurations */
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
|
||||
pmic_data->vdac = &omap4_vdac_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
|
||||
pmic_data->vaux2 = &omap4_vaux2_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
|
||||
pmic_data->vaux3 = &omap4_vaux3_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
|
||||
pmic_data->vmmc = &omap4_vmmc_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
|
||||
pmic_data->vpp = &omap4_vpp_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
|
||||
pmic_data->vana = &omap4_vana_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
|
||||
pmic_data->vcxio = &omap4_vcxio_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
|
||||
pmic_data->vusb = &omap4_vusb_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
|
||||
!pmic_data->clk32kg)
|
||||
pmic_data->clk32kg = &omap4_clk32kg_idata;
|
||||
}
|
||||
|
||||
void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
|
||||
u32 pdata_flags, u32 regulators_flags)
|
||||
{
|
||||
if (!pmic_data->irq_base)
|
||||
pmic_data->irq_base = TWL4030_IRQ_BASE;
|
||||
if (!pmic_data->irq_end)
|
||||
pmic_data->irq_end = TWL4030_IRQ_END;
|
||||
|
||||
/* Common platform data configurations */
|
||||
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
|
||||
pmic_data->usb = &omap3_usb_pdata;
|
||||
|
||||
if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
|
||||
pmic_data->bci = &omap3_bci_pdata;
|
||||
|
||||
if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
|
||||
pmic_data->madc = &omap3_madc_pdata;
|
||||
|
||||
if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->codec)
|
||||
pmic_data->codec = &omap3_codec_pdata;
|
||||
|
||||
/* Common regulator configurations */
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
|
||||
pmic_data->vdac = &omap3_vdac_idata;
|
||||
|
||||
if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
|
||||
pmic_data->vpll2 = &omap3_vpll2_idata;
|
||||
}
|
|
@ -0,0 +1,59 @@
|
|||
#ifndef __OMAP_PMIC_COMMON__
|
||||
#define __OMAP_PMIC_COMMON__
|
||||
|
||||
#define TWL_COMMON_PDATA_USB (1 << 0)
|
||||
#define TWL_COMMON_PDATA_BCI (1 << 1)
|
||||
#define TWL_COMMON_PDATA_MADC (1 << 2)
|
||||
#define TWL_COMMON_PDATA_AUDIO (1 << 3)
|
||||
|
||||
/* Common LDO regulators for TWL4030/TWL6030 */
|
||||
#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
|
||||
#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
|
||||
#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
|
||||
#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
|
||||
|
||||
/* TWL6030 LDO regulators */
|
||||
#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
|
||||
#define TWL_COMMON_REGULATOR_VPP (1 << 5)
|
||||
#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
|
||||
#define TWL_COMMON_REGULATOR_VANA (1 << 7)
|
||||
#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
|
||||
#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
|
||||
#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
|
||||
|
||||
/* TWL4030 LDO regulators */
|
||||
#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
|
||||
#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
|
||||
|
||||
|
||||
struct twl4030_platform_data;
|
||||
|
||||
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data);
|
||||
|
||||
static inline void omap2_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
|
||||
}
|
||||
|
||||
static inline void omap3_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
|
||||
}
|
||||
|
||||
static inline void omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
|
||||
omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
|
||||
}
|
||||
|
||||
void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
|
||||
u32 pdata_flags, u32 regulators_flags);
|
||||
|
||||
void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
|
||||
u32 pdata_flags, u32 regulators_flags);
|
||||
|
||||
#endif /* __OMAP_PMIC_COMMON__ */
|
|
@ -211,9 +211,6 @@ choice
|
|||
depends on ARCH_OMAP
|
||||
default OMAP_PM_NOOP
|
||||
|
||||
config OMAP_PM_NONE
|
||||
bool "No PM layer"
|
||||
|
||||
config OMAP_PM_NOOP
|
||||
bool "No-op/debug PM layer"
|
||||
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
|
@ -26,87 +27,16 @@
|
|||
|
||||
#include <plat/clock.h>
|
||||
|
||||
|
||||
/*
|
||||
* 32KHz clocksource ... always available, on pretty most chips except
|
||||
* OMAP 730 and 1510. Other timers could be used as clocksources, with
|
||||
* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
|
||||
* but systems won't necessarily want to spend resources that way.
|
||||
*/
|
||||
static void __iomem *timer_32k_base;
|
||||
|
||||
#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
|
||||
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
/*
|
||||
* offset_32k holds the init time counter value. It is then subtracted
|
||||
* from every counter read to achieve a counter that counts time from the
|
||||
* kernel boot (needed for sched_clock()).
|
||||
*/
|
||||
static u32 offset_32k __read_mostly;
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap16xx_32k_read NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap2420_32k_read NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap2430_32k_read NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static cycle_t notrace omap34xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap34xx_32k_read NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
static cycle_t notrace omap44xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap44xx_32k_read NULL
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Kernel assumes that sched_clock can be called early but may not have
|
||||
* things ready yet.
|
||||
*/
|
||||
static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_32k = {
|
||||
.name = "32k_counter",
|
||||
.rating = 250,
|
||||
.read = omap_32k_read_dummy,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
/*
|
||||
* Returns current time from boot in nsecs. It's OK for this to wrap
|
||||
* around for now, as it's just a relative time stamp.
|
||||
|
@ -122,7 +52,7 @@ static DEFINE_CLOCK_DATA(cd);
|
|||
|
||||
static inline unsigned long long notrace _omap_32k_sched_clock(void)
|
||||
{
|
||||
u32 cyc = clocksource_32k.read(&clocksource_32k);
|
||||
u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
|
||||
return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
|
||||
}
|
||||
|
||||
|
@ -140,7 +70,7 @@ unsigned long long notrace omap_32k_sched_clock(void)
|
|||
|
||||
static void notrace omap_update_sched_clock(void)
|
||||
{
|
||||
u32 cyc = clocksource_32k.read(&clocksource_32k);
|
||||
u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
|
||||
update_sched_clock(&cd, cyc, (u32)~0);
|
||||
}
|
||||
|
||||
|
@ -153,6 +83,7 @@ static void notrace omap_update_sched_clock(void)
|
|||
*/
|
||||
static struct timespec persistent_ts;
|
||||
static cycles_t cycles, last_cycles;
|
||||
static unsigned int persistent_mult, persistent_shift;
|
||||
void read_persistent_clock(struct timespec *ts)
|
||||
{
|
||||
unsigned long long nsecs;
|
||||
|
@ -160,11 +91,10 @@ void read_persistent_clock(struct timespec *ts)
|
|||
struct timespec *tsp = &persistent_ts;
|
||||
|
||||
last_cycles = cycles;
|
||||
cycles = clocksource_32k.read(&clocksource_32k);
|
||||
cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
|
||||
delta = cycles - last_cycles;
|
||||
|
||||
nsecs = clocksource_cyc2ns(delta,
|
||||
clocksource_32k.mult, clocksource_32k.shift);
|
||||
nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
|
||||
|
||||
timespec_add_ns(tsp, nsecs);
|
||||
*ts = *tsp;
|
||||
|
@ -176,29 +106,46 @@ int __init omap_init_clocksource_32k(void)
|
|||
"%s: can't register clocksource!\n";
|
||||
|
||||
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
|
||||
u32 pbase;
|
||||
unsigned long size = SZ_4K;
|
||||
void __iomem *base;
|
||||
struct clk *sync_32k_ick;
|
||||
|
||||
if (cpu_is_omap16xx())
|
||||
clocksource_32k.read = omap16xx_32k_read;
|
||||
else if (cpu_is_omap2420())
|
||||
clocksource_32k.read = omap2420_32k_read;
|
||||
if (cpu_is_omap16xx()) {
|
||||
pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
|
||||
size = SZ_1K;
|
||||
} else if (cpu_is_omap2420())
|
||||
pbase = OMAP2420_32KSYNCT_BASE + 0x10;
|
||||
else if (cpu_is_omap2430())
|
||||
clocksource_32k.read = omap2430_32k_read;
|
||||
pbase = OMAP2430_32KSYNCT_BASE + 0x10;
|
||||
else if (cpu_is_omap34xx())
|
||||
clocksource_32k.read = omap34xx_32k_read;
|
||||
pbase = OMAP3430_32KSYNCT_BASE + 0x10;
|
||||
else if (cpu_is_omap44xx())
|
||||
clocksource_32k.read = omap44xx_32k_read;
|
||||
pbase = OMAP4430_32KSYNCT_BASE + 0x10;
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
/* For this to work we must have a static mapping in io.c for this area */
|
||||
base = ioremap(pbase, size);
|
||||
if (!base)
|
||||
return -ENODEV;
|
||||
|
||||
sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
|
||||
if (!IS_ERR(sync_32k_ick))
|
||||
clk_enable(sync_32k_ick);
|
||||
|
||||
offset_32k = clocksource_32k.read(&clocksource_32k);
|
||||
timer_32k_base = base;
|
||||
|
||||
if (clocksource_register_hz(&clocksource_32k, 32768))
|
||||
printk(err, clocksource_32k.name);
|
||||
/*
|
||||
* 120000 rough estimate from the calculations in
|
||||
* __clocksource_updatefreq_scale.
|
||||
*/
|
||||
clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
|
||||
32768, NSEC_PER_SEC, 120000);
|
||||
|
||||
if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
|
||||
clocksource_mmio_readl_up))
|
||||
printk(err, "32k_counter");
|
||||
|
||||
init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
|
||||
32768, SC_MULT, SC_SHIFT);
|
||||
|
|
|
@ -152,7 +152,7 @@ struct dpll_data {
|
|||
u16 max_multiplier;
|
||||
u8 last_rounded_n;
|
||||
u8 min_divider;
|
||||
u8 max_divider;
|
||||
u16 max_divider;
|
||||
u8 modes;
|
||||
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
||||
void __iomem *autoidle_reg;
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#ifndef __ASM_ARCH_DMTIMER_H
|
||||
#define __ASM_ARCH_DMTIMER_H
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#define __ASM__ARCH_OMAP_I2C_H
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-omap.h>
|
||||
|
||||
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
|
||||
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
|
@ -46,10 +47,13 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
|||
*/
|
||||
struct omap_i2c_dev_attr {
|
||||
u8 fifo_depth;
|
||||
u8 flags;
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
void __init omap1_i2c_mux_pins(int bus_id);
|
||||
void __init omap2_i2c_mux_pins(int bus_id);
|
||||
|
||||
struct omap_hwmod;
|
||||
int omap_i2c_reset(struct omap_hwmod *oh);
|
||||
|
||||
#endif /* __ASM__ARCH_OMAP_I2C_H */
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
|
||||
static struct platform_device omap_mcbsp##port_nr = { \
|
||||
.name = "omap-mcbsp-dai", \
|
||||
.id = OMAP_MCBSP##port_nr, \
|
||||
.id = port_nr - 1, \
|
||||
}
|
||||
|
||||
#define MCBSP_CONFIG_TYPE2 0x2
|
||||
|
@ -331,14 +331,6 @@ struct omap_mcbsp_reg_cfg {
|
|||
u16 rccr;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
OMAP_MCBSP1 = 0,
|
||||
OMAP_MCBSP2,
|
||||
OMAP_MCBSP3,
|
||||
OMAP_MCBSP4,
|
||||
OMAP_MCBSP5
|
||||
} omap_mcbsp_id;
|
||||
|
||||
typedef enum {
|
||||
OMAP_MCBSP_WORD_8 = 0,
|
||||
OMAP_MCBSP_WORD_12,
|
||||
|
@ -385,8 +377,6 @@ struct omap_mcbsp {
|
|||
void __iomem *io_base;
|
||||
u8 id;
|
||||
u8 free;
|
||||
omap_mcbsp_word_length rx_word_length;
|
||||
omap_mcbsp_word_length tx_word_length;
|
||||
|
||||
int rx_irq;
|
||||
int tx_irq;
|
||||
|
|
|
@ -40,11 +40,7 @@
|
|||
* framework starts. The "_if_" is to avoid name collisions with the
|
||||
* PM idle-loop code.
|
||||
*/
|
||||
#ifdef CONFIG_OMAP_PM_NONE
|
||||
#define omap_pm_if_early_init() 0
|
||||
#else
|
||||
int __init omap_pm_if_early_init(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap_pm_if_init - OMAP PM init code called after clock fw init
|
||||
|
@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
|
|||
* The main initialization code. OPP tables are passed in here. The
|
||||
* "_if_" is to avoid name collisions with the PM idle-loop code.
|
||||
*/
|
||||
#ifdef CONFIG_OMAP_PM_NONE
|
||||
#define omap_pm_if_init() 0
|
||||
#else
|
||||
int __init omap_pm_if_init(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap_pm_if_exit - OMAP PM exit code
|
||||
|
|
|
@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
|
|||
#define HWMOD_IDLEMODE_FORCE (1 << 0)
|
||||
#define HWMOD_IDLEMODE_NO (1 << 1)
|
||||
#define HWMOD_IDLEMODE_SMART (1 << 2)
|
||||
/* Slave idle mode flag only */
|
||||
#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
|
||||
|
||||
/**
|
||||
|
@ -98,7 +97,7 @@ struct omap_hwmod_mux_info {
|
|||
/**
|
||||
* struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
|
||||
* @name: name of the IRQ channel (module local name)
|
||||
* @irq_ch: IRQ channel ID
|
||||
* @irq: IRQ channel ID (should be non-negative except -1 = terminator)
|
||||
*
|
||||
* @name should be something short, e.g., "tx" or "rx". It is for use
|
||||
* by platform_get_resource_byname(). It is defined locally to the
|
||||
|
@ -106,13 +105,13 @@ struct omap_hwmod_mux_info {
|
|||
*/
|
||||
struct omap_hwmod_irq_info {
|
||||
const char *name;
|
||||
u16 irq;
|
||||
s16 irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_dma_info - DMA channels used by the hwmod
|
||||
* @name: name of the DMA channel (module local name)
|
||||
* @dma_req: DMA request ID
|
||||
* @dma_req: DMA request ID (should be non-negative except -1 = terminator)
|
||||
*
|
||||
* @name should be something short, e.g., "tx" or "rx". It is for use
|
||||
* by platform_get_resource_byname(). It is defined locally to the
|
||||
|
@ -120,7 +119,7 @@ struct omap_hwmod_irq_info {
|
|||
*/
|
||||
struct omap_hwmod_dma_info {
|
||||
const char *name;
|
||||
u16 dma_req;
|
||||
s16 dma_req;
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -220,7 +219,6 @@ struct omap_hwmod_addr_space {
|
|||
* @clk: interface clock: OMAP clock name
|
||||
* @_clk: pointer to the interface struct clk (filled in at runtime)
|
||||
* @fw: interface firewall data
|
||||
* @addr_cnt: ARRAY_SIZE(@addr)
|
||||
* @width: OCP data width
|
||||
* @user: initiators using this interface (see OCP_USER_* macros above)
|
||||
* @flags: OCP interface flags (see OCPIF_* macros above)
|
||||
|
@ -239,7 +237,6 @@ struct omap_hwmod_ocp_if {
|
|||
union {
|
||||
struct omap_hwmod_omap2_firewall omap2;
|
||||
} fw;
|
||||
u8 addr_cnt;
|
||||
u8 width;
|
||||
u8 user;
|
||||
u8 flags;
|
||||
|
@ -258,6 +255,7 @@ struct omap_hwmod_ocp_if {
|
|||
#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
|
||||
#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
|
||||
#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
|
||||
#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
|
||||
|
||||
/* omap_hwmod_sysconfig.sysc_flags capability flags */
|
||||
#define SYSC_HAS_AUTOIDLE (1 << 0)
|
||||
|
@ -468,8 +466,8 @@ struct omap_hwmod_class {
|
|||
* @name: name of the hwmod
|
||||
* @class: struct omap_hwmod_class * to the class of this hwmod
|
||||
* @od: struct omap_device currently associated with this hwmod (internal use)
|
||||
* @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
|
||||
* @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
|
||||
* @mpu_irqs: ptr to an array of MPU IRQs
|
||||
* @sdma_reqs: ptr to an array of System DMA request IDs
|
||||
* @prcm: PRCM data pertaining to this hwmod
|
||||
* @main_clk: main clock: OMAP clock name
|
||||
* @_clk: pointer to the main struct clk (filled in at runtime)
|
||||
|
@ -482,8 +480,6 @@ struct omap_hwmod_class {
|
|||
* @_sysc_cache: internal-use hwmod flags
|
||||
* @_mpu_rt_va: cached register target start address (internal use)
|
||||
* @_mpu_port_index: cached MPU register target slave ID (internal use)
|
||||
* @mpu_irqs_cnt: number of @mpu_irqs
|
||||
* @sdma_reqs_cnt: number of @sdma_reqs
|
||||
* @opt_clks_cnt: number of @opt_clks
|
||||
* @master_cnt: number of @master entries
|
||||
* @slaves_cnt: number of @slave entries
|
||||
|
@ -531,8 +527,6 @@ struct omap_hwmod {
|
|||
u16 flags;
|
||||
u8 _mpu_port_index;
|
||||
u8 response_lat;
|
||||
u8 mpu_irqs_cnt;
|
||||
u8 sdma_reqs_cnt;
|
||||
u8 rst_lines_cnt;
|
||||
u8 opt_clks_cnt;
|
||||
u8 masters_cnt;
|
||||
|
@ -572,6 +566,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
|
|||
|
||||
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
|
||||
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
|
||||
int omap_hwmod_softreset(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_count_resources(struct omap_hwmod *oh);
|
||||
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
|
||||
|
|
|
@ -869,9 +869,6 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
|
|||
if (cpu_is_omap34xx())
|
||||
omap_st_start(mcbsp);
|
||||
|
||||
mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
|
||||
mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
|
||||
|
||||
/* Only enable SRG, if McBSP is master */
|
||||
w = MCBSP_READ_CACHE(mcbsp, PCR0);
|
||||
if (w & (FSXM | FSRM | CLKXM | CLKRM))
|
||||
|
@ -969,6 +966,33 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
|
|||
}
|
||||
EXPORT_SYMBOL(omap_mcbsp_stop);
|
||||
|
||||
/*
|
||||
* The following functions are only required on an OMAP1-only build.
|
||||
* mach-omap2/mcbsp.c contains the real functions
|
||||
*/
|
||||
#ifndef CONFIG_ARCH_OMAP2PLUS
|
||||
int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
|
||||
{
|
||||
WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void omap2_mcbsp1_mux_clkr_src(u8 mux)
|
||||
{
|
||||
WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
void omap2_mcbsp1_mux_fsr_src(u8 mux)
|
||||
{
|
||||
WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
#define max_thres(m) (mcbsp->pdata->buffer_size)
|
||||
#define valid_threshold(m, val) ((val) <= max_thres(m))
|
||||
|
|
|
@ -236,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
|
||||
{
|
||||
return container_of(pdev, struct omap_device, pdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
|
||||
* @od: struct omap_device *od
|
||||
|
@ -316,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
|
|||
struct omap_device *od;
|
||||
u32 ret = 0;
|
||||
|
||||
od = _find_by_pdev(pdev);
|
||||
od = to_omap_device(pdev);
|
||||
|
||||
if (od->hwmods_cnt)
|
||||
ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
|
||||
|
@ -611,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev)
|
|||
int ret;
|
||||
struct omap_device *od;
|
||||
|
||||
od = _find_by_pdev(pdev);
|
||||
od = to_omap_device(pdev);
|
||||
|
||||
if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
|
||||
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
|
||||
|
@ -650,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev)
|
|||
int ret;
|
||||
struct omap_device *od;
|
||||
|
||||
od = _find_by_pdev(pdev);
|
||||
od = to_omap_device(pdev);
|
||||
|
||||
if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
|
||||
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
|
||||
|
@ -681,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev)
|
|||
int ret, i;
|
||||
struct omap_device *od;
|
||||
|
||||
od = _find_by_pdev(pdev);
|
||||
od = to_omap_device(pdev);
|
||||
|
||||
if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
|
||||
od->_state != OMAP_DEVICE_STATE_IDLE) {
|
||||
|
@ -722,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
|
|||
int ret = -EINVAL;
|
||||
struct omap_device *od;
|
||||
|
||||
od = _find_by_pdev(pdev);
|
||||
od = to_omap_device(pdev);
|
||||
|
||||
if (new_wakeup_lat_limit == od->dev_wakeup_lat)
|
||||
return 0;
|
||||
|
|
|
@ -3,6 +3,33 @@
|
|||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* Version 2 of the I2C peripheral unit has a different register
|
||||
* layout and extra registers. The ID register in the V2 peripheral
|
||||
* unit on the OMAP4430 reports the same ID as the V1 peripheral
|
||||
* unit on the OMAP3530, so we must inform the driver which IP
|
||||
* version we know it is running on from platform / cpu-specific
|
||||
* code using these constants in the hwmod class definition.
|
||||
*/
|
||||
|
||||
#define OMAP_I2C_IP_VERSION_1 1
|
||||
#define OMAP_I2C_IP_VERSION_2 2
|
||||
|
||||
/* struct omap_i2c_bus_platform_data .flags meanings */
|
||||
|
||||
#define OMAP_I2C_FLAG_NO_FIFO BIT(0)
|
||||
#define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
|
||||
#define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
|
||||
#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
|
||||
#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
|
||||
#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
|
||||
#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
|
||||
/* how the CPU address bus must be translated for I2C unit access */
|
||||
#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
|
||||
#define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7)
|
||||
#define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8)
|
||||
#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
|
||||
|
||||
struct omap_i2c_bus_platform_data {
|
||||
u32 clkrate;
|
||||
void (*set_mpu_wkup_lat)(struct device *dev, long set);
|
||||
|
|
Loading…
Reference in New Issue