Commit Graph

16 Commits

Author SHA1 Message Date
Ken Cox dbe91a2e6e C6X: add basic support for TMS320C6678 SoC
This patch adds support for the TMS320C6678 SoC on an EVMC6678LE
evaluation board. The 6678 is a C66x family CPU which is very similar
to the already supported C64x CPUs with the addition of floating point
instructions.

Signed-off-by: Ken Cox <jkc@redhat.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Aurelien Jacquiot <a-jacquiot@ti.com>
CC: linux-c6x-dev@linux-c6x.org
2012-07-18 23:52:31 -04:00
Mark Salter b3f8956210 C6X: remove megamod-pic requirement on direct-mapped core pic
The megamodule PIC cascades a number of interrupt sources into the core
priority PIC. The megamodule code depends on the core hardware interrupt
numbers being mapped one-to-one with regard to linux interrupt numbers.
This patch removes that dependence in order to pave the way for removing
the direct mapping in the core PIC code.

Signed-off-by: Mark Salter <msalter@redhat.com>
2012-07-18 23:43:37 -04:00
David Howells 6a846f3f82 Disintegrate asm/system.h for C6X
Disintegrate asm/system.h for C6X.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
cc: linux-c6x-dev@linux-c6x.org
2012-03-28 18:30:02 +01:00
Grant Likely c1e572e650 irq_domain/c6x: Use library of xlate functions
The c6x irq controllers don't need to define custom .xlate hooks

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-16 06:11:24 -07:00
Grant Likely 15a25980d4 irq_domain/c6x: constify irq_domain structures
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Mark Salter <msalter@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-16 06:11:24 -07:00
Mark Salter 0bd761e1b6 irq_domain/c6x: Convert c6x to use generic irq_domain support.
The C6X IRQ support was copied almost verbatim from the PowerPC virtual IRQ
code. The PowerPC code was used as the basis for generic irq_domain support,
so this patch mostly copies what what done to arch/powerpc by Grant Likely
in his irq_domain patch series.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-16 06:11:24 -07:00
Mark Salter 25b48ff852 C6X: fix timer64 initialization
Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08 15:12:17 -05:00
Mark Salter 4a059ff3a9 C6X: fix layout of EMIFA registers
Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08 15:12:09 -05:00
Mark Salter 9de98fb4ec C6X: DSCR - Device State Configuration Registers
All SoCs provide an area of device configuration registers called the DSCR. The
location of specific registers as well as their use varies considerably from
implementation to implementation. Rather than having to rely on additional
SoC-specific DSCR code for each new supported SoC, this code generalize things
as much as possible using device tree properties. Initialization must take
place early on (setup_arch time) in case the event timer device needs to be
enable via the DSCR.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:48:36 -04:00
Mark Salter 6bbfd8975c C6X: EMIF - External Memory Interface
Several SoC parts provide a simple bridge to support external memory mapped
devices. This code probes the device tree for an EMIF node and sets up the
bridge registers if such a node is found. Beyond initial set up, there is no
further need to access the bridge control registers. External devices on the
bus are accessed through their MMIO registers using suitable drivers. The
bridge hardware does provide for timeout and other error interrupts, but these
are not yet supported.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:48:29 -04:00
Aurelien Jacquiot 784bdcd0aa C6X: cache control
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter <msalter@redhat.com>

Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:48:10 -04:00
Mark Salter 81ec988981 C6X: clocks
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
feeding into the cores or peripheral clock domains. The hardware is very similar
to arm/mach-davinci clocks. This is still a work in progress which needs to be
updated once device tree clock binding changes shake out.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:48:07 -04:00
Aurelien Jacquiot ec500af305 C6X: interrupt handling
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter <msalter@redhat.com>

Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:47:54 -04:00
Aurelien Jacquiot 546a39546c C6X: time management
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter <msalter@redhat.com>

Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:47:51 -04:00
Mark Salter 041cadca70 C6X: devicetree support
This is the basic devicetree support for C6X. Currently, four boards are
supported. Each one uses a different SoC part. Two of the four supported
SoCs are multicore. One with 3 cores and the other with 6 cores. There is
no coherency between the core-level caches, so SMP is not an option. It is
possible to run separate kernel instances on the various cores. There is
currently no C6X bootloader support for device trees so we build in the DTB
for now.

There are some interesting twists to the hardware which are of note for device
tree support. Each core has its own interrupt controller which is controlled
by special purpose core registers. This core controller provides 12 general
purpose prioritized interrupt sources. Each core is contained within a
hardware "module" which provides L1 and L2 caches, power control, and another
interrupt controller which cascades into the core interrupt controller. These
core module functions are controlled by memory mapped registers. The addresses
for these registers are the same for each core. That is, when coreN accesses
a module-level MMIO register at a given address, it accesses the register for
coreN even though other cores would use the same address to access the register
in the module containing those cores. Other hardware modules (timers, enet, etc)
which are memory mapped can be accessed by all cores.

The timers need some further explanation for multicore SoCs. Even though all
timer control registers are visible to all cores, interrupt routing or other
considerations may make a given timer more suitable for use by a core than
some other timer. Because of this and the desire to have the same image run
on more than one core, the timer nodes have a "ti,core-mask" property which
is used by the driver to scan for a suitable timer to use.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:47:33 -04:00
Aurelien Jacquiot c278400c52 C6X: build infrastructure
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter <msalter@redhat.com>

Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06 19:47:25 -04:00