A bunch of changes to improve support on the Nyan Big (Acer Chromebook
13). These enable the trackpad and make the WiFi card work. Changes to
the userspace-exposed name of the soundcard are required for a better
audio experience.
Support for Nyan Blaze (HP Chromebook 14) is added. It is very similar
to Nyan Big and therefore can enjoys many of the above improvements.
Since the EMC driver can now be used to scale the frequency at which
external memory is clocked, corresponding EMC frequency tables are added
for Jetson TK1 and the Nyan boards.
The Jetson TK1, Beaver and Nyan boards now also use generated pinmux
data, which makes it easier to keep it in sync with the data provided by
syseng.
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Merge tag 'tegra-for-4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Merge "ARM: tegra: Device tree changes for v4.1-rc1" from Thierry Reding:
A bunch of changes to improve support on the Nyan Big (Acer Chromebook
13). These enable the trackpad and make the WiFi card work. Changes to
the userspace-exposed name of the soundcard are required for a better
audio experience.
Support for Nyan Blaze (HP Chromebook 14) is added. It is very similar
to Nyan Big and therefore can enjoys many of the above improvements.
Since the EMC driver can now be used to scale the frequency at which
external memory is clocked, corresponding EMC frequency tables are added
for Jetson TK1 and the Nyan boards.
The Jetson TK1, Beaver and Nyan boards now also use generated pinmux
data, which makes it easier to keep it in sync with the data provided by
syseng.
* tag 'tegra-for-4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add EMC timings to Nyan Blaze device tree
ARM: tegra: Add EMC timings to Nyan Big device tree
ARM: tegra: Add EMC timings to Jetson TK1 device tree
ARM: tegra: Add EMC to Tegra124 device tree
ARM: tegra: Add Tegra124 ACTMON support
of: Add binding for NVIDIA Tegra ACTMON node
ARM: tegra: nyan: The WiFi card is kept powered during suspend
ARM: tegra: nyan: Add gpio-restart node
ARM: tegra: nyan: Set maximum frequency for SPI flash
ARM: tegra: Use generated pinmux data for Nyan Big
ARM: tegra: Use pwrseq-simple for the wifi in Nyan
ARM: tegra: Add node for trackpad in Nyan boards
ARM: tegra: Add DTS for the nyan-blaze board
ARM: tegra: Move generic parts out of the nyan-big DT
ARM: tegra: Change model of sound card in Nyan Big
ARM: tegra: Use generated pinmux for Beaver board
ARM: tegra: Import latest Jetson TK1 pinmux
Signed-off-by: Olof Johansson <olof@lixom.net>
Paul Walmsley <paul@pwsan.com>:
OMAP hwmod data changes for AM43xx and DRA7xx for v4.1
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
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Merge tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap soc changes for v4.1" from Tony Lindgren:
SoC related changes for omaps. Mostly hwmod related changes via
Paul Walmsley <paul@pwsan.com>:
OMAP hwmod data changes for AM43xx and DRA7xx for v4.1
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
* tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
ARM: DRA7: hwmod: Add data for GPTimers 13 through 16
ARM: omap-device: add missed callback for suspend-to-disk
ARM: OMAP2: hwmod: AM43XX: Add hwmod support for HDQ-1W
Signed-off-by: Olof Johansson <olof@lixom.net>
This is mostly to enable errata 798181 and thermal support for dra7,
configure ocp2scp for am437x, remove dead code for OMAP4_ERRATA_I688
and fix build warnings for omap1510 only config.
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Merge tag 'omap-for-v4.1/fixes-0' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "omap non-urgent fixes for v4.1" from Tony Lindgren:
Fixes for omaps that were not considered urgent enough for the -rc cycle.
This is mostly to enable errata 798181 and thermal support for dra7,
configure ocp2scp for am437x, remove dead code for OMAP4_ERRATA_I688
and fix build warnings for omap1510 only config.
* tag 'omap-for-v4.1/fixes-0' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: Enable Cortex A15 errata 798181
ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102
ARM: dts: DRA7: Add bandgap and related thermal nodes
bus: ocp2scp: SYNC2 value should be changed to 0x6
ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP
ARM: OMAP2+: remove superfluous NULL pointer check
ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688
MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT
ARM: OMAP1: PM: fix some build warnings on 1510-only Kconfigs
Signed-off-by: Olof Johansson <olof@lixom.net>
This series reworks some of the CCI-400 PMU code so that it can be used
on both ARM and ARM64-based systems, without the need to boot in secure
mode on the latter. This paves the way for CCI-500 support in future.
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Merge tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers
Merge "arm-cci PMU updates for 4.1" from Will Deacon:
CCI-400 PMU updates
This series reworks some of the CCI-400 PMU code so that it can be used
on both ARM and ARM64-based systems, without the need to boot in secure
mode on the latter. This paves the way for CCI-500 support in future.
* tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
+ Linux 4.0-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle states device bindings for cpuidle support for APQ
8974/8074.
Support Standalone power collapse (SPC) idle state (power down that does
not affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
PMA8084 have 2 SPMI devices per physical package. Add their
configuration nodes and include them in boards which are using
AQP8084 based chipset.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
PM8841 and PM8941 have 2 SPMI devices per physical package.
Add their configuration nodes and include them in boards
which are using 8x74 based chipset.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the node for the LPASS clock controller found on a few qcom
SoCs so that the clock driver can probe.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
[sboyd@codeaurora.org: Added apq8064 and msm8960 nodes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than
16 partitions
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Merge tag 'qcom-defconfig-for-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/defconfig
Merge "qcom defconfig changes for 4.1-1" from Kumar Gala:
Qualcomm ARM Based defconfig Updates for v4.1-1
* Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than
16 partitions
* tag 'qcom-defconfig-for-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
data instead of platform data from Eliad Peller <eliad@wizery.com>:
- Add device-tree support to the wlcore (wl12xx/wl18xx) driver.
- Update the current users to use the bindings instead of pdata-quirks.
- Finally, remove the deprecated wl12xx_platform_data struct
Note that da850 board file code that still uses the platform data,
but we have da850.dtsi that can be used instead. So it was decided
that we should try to remove the wl12xx support from the da850
board file as suggested by Sekhar Nori <nsekhar@ti.com>. As it's
the last patch in the series, the last patch can be simply reverted
if needed.
As this series touches quite a bit of arch code, it was suggested
by Kalle Valo <kvalo@codeaurora.org> that the whole series should
be merged via the arm-soc tree.
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Merge tag 'omap-for-v4.1/wl12xx-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "wireless wl12xx and omap device tree changes for v4.1" from Tony
Lindgren:
Wireless and omap changes to make wl12xx driver to use device tree
data instead of platform data from Eliad Peller <eliad@wizery.com>:
- Add device-tree support to the wlcore (wl12xx/wl18xx) driver.
- Update the current users to use the bindings instead of pdata-quirks.
- Finally, remove the deprecated wl12xx_platform_data struct
Note that da850 board file code that still uses the platform data,
but we have da850.dtsi that can be used instead. So it was decided
that we should try to remove the wl12xx support from the da850
board file as suggested by Sekhar Nori <nsekhar@ti.com>. As it's
the last patch in the series, the last patch can be simply reverted
if needed.
As this series touches quite a bit of arch code, it was suggested
by Kalle Valo <kvalo@codeaurora.org> that the whole series should
be merged via the arm-soc tree.
* tag 'omap-for-v4.1/wl12xx-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
wlcore: remove wl12xx_platform_data
ARM: dts: add wl12xx/wl18xx bindings
wlcore: add device-tree support
dt: bindings: add TI's wilink wireless device
wl12xx: use frequency instead of enumerations for pdata clocks
wlcore: set irq_trigger in board files instead of hiding behind a quirk
+ Linux 4.0-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
* Removal of mach-msm and associated drivers cleanups that have been
ack'd by associated maintainers
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Merge tag 'qcom-cleanup-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/cleanup
Merge "qcom cleanup changes for 4.1" from Kumar Gala:
General cleanups for MSM/QCOM for 4.1
* Removal of mach-msm and associated drivers cleanups that have been
ack'd by associated maintainers
* tag 'qcom-cleanup-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
mmc: Remove msm_sdcc driver
gpio: Remove gpio-msm-v1 driver
ARM: Remove mach-msm and associated ARM architecture code
+ Linux 4.0-rc3
Signed-off-by: Olof Johansson <olof@lixom.net>
Nothing really standing out here, just a few options to enable in the defconfigs
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Merge tag 'sunxi-defconfig-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/defconfig
Merge "Allwinner defconfig changes for 4.1" from Maxime Ripard:
Nothing really standing out here, just a few options to enable in the defconfigs
* tag 'sunxi-defconfig-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi_defconfig: increase the number of maximum number of CPUs to 8
ARM: multi_v7_defconfig: Enable CONFIG_PHY_SUN9I_USB
ARM: sunxi_defconfig: Enable CONFIG_PHY_SUN9I_USB
Signed-off-by: Olof Johansson <olof@lixom.net>
The custom suspend callback is removed for this change. The extra call
to exynos_cpu_power_up(() that was present at the end of exynos_suspend()
is now relocated to the cpu_is_up callback.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently the cpu argument validity check uses a hardcoded limit of 4.
The DCSCB configuration data provides the actual number of CPUs and
we already use it elsewhere. Let's improve the cpu argument validity
check by using that information instead.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
All backends are reimplementing a variation of the same CPU reference
count handling. They are also responsible for driving the MCPM special
low-level locking. This is needless duplication, involving algorithmic
requirements that are not necessarily obvious to the uninitiated.
And from past code review experience, those were all initially
implemented badly.
After 3 years, it is time to refactor as much common code to the core
MCPM facility to make the backends as simple as possible. To avoid a
flag day, the new scheme is introduced in parallel to the existing
backend interface. When all backends are converted over, the
compatibility interface could be removed.
The new MCPM backend interface implements simpler methods addressing
very platform specific tasks performed under lock protection while
keeping the algorithmic complexity and race avoidance local to the
core code.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Remove default cpuidle driver, it does not appear to serve any purpose
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Merge tag 'renesas-soc-cleanup3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Third Round of Renesas ARM Based SoC Cleanup for v4.1" from Simon
Horman:
* Remove default cpuidle driver, it does not appear to serve any purpose
* tag 'renesas-soc-cleanup3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: cpuidle: Remove the pointless default driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Broadcom Device Tree changes for 4.1 #3" from Brian Norris:
This pull request contains changes to the BCM7445 reference DTS files from
Brian:
- making a clock-frequency property decimal instead of hexadecimal
- adding the irq0 interrupt controller node to make the reference DTS bootable
again
* tag 'arm-soc/for-4.1/devicetree-part-3' of http://github.com/broadcom/stblinux:
ARM: dts: brcmstb: add IRQ0 controller
ARM: dts: brcmstb: un-hexify clock frequency
Signed-off-by: Olof Johansson <olof@lixom.net>
* Fixed WAITMONITORINGTIME programming to be based on
GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider
programming is fixed for both synchronous and asynchronous
modes.
* Allow GPMC's children of default bus type to be populated in
the device tree.
* Improved DEBUG output data and format.
* Prevent writing 1 into reserved bits of GPMC_CONFIG7.
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Merge tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux into next/drivers
Merge "OMAP-GPMC driver fixes for v4.1" from Roger Quandros:
* Fixed WAITMONITORINGTIME programming to be based on
GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider
programming is fixed for both synchronous and asynchronous
modes.
* Allow GPMC's children of default bus type to be populated in
the device tree.
* Improved DEBUG output data and format.
* Prevent writing 1 into reserved bits of GPMC_CONFIG7.
* tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux:
ARM OMAP2+ GPMC: fix programming/showing reserved timing parameters
ARM OMAP2+ GPMC: fix WAITMONITORINGTIME divider bug
ARM OMAP2+ GPMC: calculate GPMCFCLKDIVIDER based on WAITMONITORINGTIME
ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDER
ARM OMAP2+ GPMC: change get_gpmc_timing_reg output for DTS
ARM OMAP2+ GPMC: fix debug output alignment
ARM OMAP2+ GPMC: add bus children
ARM OMAP2+ GPMC: don't undef DEBUG
ARM: OMAP2+: gpmc: make gpmc_cs_get_name() static
ARM: OMAP2+: gpmc: Fix writing in gpmc_cs_set_memconf
Signed-off-by: Olof Johansson <olof@lixom.net>
- add support for Performance Monitor Unit on most of mvebu SoCs
- add nas2big support
- add support for USB3 port On Armada 385 AP
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Merge tag 'mvebu-dt-4.1-2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: dt changes for v4.1 (round 2)" from Gregory Clement:
mvebu dt changes for v4.1 (part #2)
- add support for Performance Monitor Unit on most of mvebu SoCs
- add nas2big support
- add support for USB3 port On Armada 385 AP
* tag 'mvebu-dt-4.1-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: armada-385-ap: Enable USB3 port
ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC
ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs
ARM: Kirkwood: add DT description for nas2big
Signed-off-by: Olof Johansson <olof@lixom.net>
- add perf support in mvebu_v7_defconfig
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Merge tag 'mvebu-defconfig-4.1-2' of git://git.infradead.org/linux-mvebu into next/defconfig
Merge "ARM: mvebu: defconfig changes for v4.1 (round 2)" from Gregory Clement:
mvebu defconfig changes for v4.1 (part #2)
- add perf support in mvebu_v7_defconfig
* tag 'mvebu-defconfig-4.1-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Enable perf support in mvebu_v7_defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
* Consolidate the pm code for R-Car Gen2
* Correct SYSCIER value for r8a7790 and r8a7791 SoCs
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Merge tag 'renesas-pm-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Renesas ARM Based SoC PM Updates for v4.1" from Simon Horman:
* Consolidate the pm code for R-Car Gen2
* Correct SYSCIER value for r8a7790 and r8a7791 SoCs
* tag 'renesas-pm-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Consolidate the pm code for R-Car Gen2
ARM: shmobile: r8a7791: Correct SYSCIER value
ARM: shmobile: r8a7790: Correct SYSCIER value
Signed-off-by: Olof Johansson <olof@lixom.net>
We want to get omap3 moved over to device tree only based booting.
These three board-*.c files seem to be inactive, so let's attempt
to drop them now rather than later. With these dropped, we have
omap3 device tree conversion status in a known state. Then we know
that we have .dts support for the remaining omap3 board-*.c files,
or it's being worked on.
By dropping these files now, we can simply revert them if really
needed for the next few merge cycles if we run into suprises.
Reverting things later on will not be so easily done.
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Merge tag 'v4.1-legacy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
Merge "omap legacy boot clean-up for v4.1" from Tony Lindgren:
Drop three omap3 legacy board-*.c files
We want to get omap3 moved over to device tree only based booting.
These three board-*.c files seem to be inactive, so let's attempt
to drop them now rather than later. With these dropped, we have
omap3 device tree conversion status in a known state. Then we know
that we have .dts support for the remaining omap3 board-*.c files,
or it's being worked on.
By dropping these files now, we can simply revert them if really
needed for the next few merge cycles if we run into suprises.
Reverting things later on will not be so easily done.
* tag 'v4.1-legacy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Remove legacy support for omap3 TouchBook
ARM: OMAP3: Remove legacy support for devkit8000
ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board
Signed-off-by: Olof Johansson <olof@lixom.net>
loadable modules.
Note that I'll do patches for armv7_defconfig for these at some
point too once we're happy with omap2plus_defconfig to avoid
extra churn on the defconfig files.
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Merge tag 'v4.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig
Merge "omap defconfig changes for v4.1" from Tony Lindgren:
Few omap2plus_defconfig updates to add commonly used drivers as
loadable modules.
Note that I'll do patches for armv7_defconfig for these at some
point too once we're happy with omap2plus_defconfig to avoid
extra churn on the defconfig files.
* tag 'v4.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: omap2plus_defconfig: Enable n900 modem as loadable modules
ARM: omap2plus_defconfig: Update bluetooth options
ARM: omap2plus_defconfig: Enable leds-pwm
ARM: omap1_defconfig: drop obsolete Kconfig symbols
arm: config: omap2plus_defconfig: switch over to LZMA compression
ARM: omap2plus_defconfig: Enable EXTCON_GPIO_USB
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support for ChiliSOM
- Add support for OpenPandora
- Add support for BeagleBoard NAND
- Enable crypto devices for omap3 devices
- Add bindings for omap3 camera support
- Updates for am437x and dra7x and dm816x SoCs
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Merge tag 'v4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap device tree changes for v4.1, part1" from Tony Lindgren:
Device tree related changes for omaps:
- Add support for ChiliSOM
- Add support for OpenPandora
- Add support for BeagleBoard NAND
- Enable crypto devices for omap3 devices
- Add bindings for omap3 camera support
- Updates for am437x and dra7x and dm816x SoCs
* tag 'v4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits)
ARM: dts: Update Nanobone dts file
ARM: dts: n950, n9: Add primary camera support
ARM: dts: omap3: Add DT entries for OMAP 3 ISP
Documentation: DT: Add bindings for omap3isp
ARM: dts: Remove files omap34xx-hs.dtsi and omap36xx-hs.dtsi
ARM: dts: omap3-tao3530: Include directly omap34xx.dtsi
ARM: dts: n900: Enable omap sham and include directly omap34xx.dtsi
ARM: dts: n9/n950: Enable omap crypto support
ARM: dts: Remove PIN_INPUT for dm816x McSPI
ARM: dts: Add cppi41 support for dm816x MUSB
ARM: dts: Fix typo for dm816x usb0_pins
ARM: dts: dra7x-evm: beagle-x15: Fix USB Peripheral
ARM: dts: am57xx-beagle-x15: Do not include the atl header
ARM: dts: DRA7: Remove ti,timer-dsp and ti,timer-pwm properties
Documentation: omap-twl4030: Move ti,codec property to optional
ARM: dts: omap3: Remove all references to ti,codec property
ARM: dts: omap3-beagle: Add NAND device
ARM: dts: AM4372: update hdq compatible property
ARM: dts: omap3-pandora: add DM3730 1 GHz version
ARM: dts: omap3-pandora: add OMAP3530 600 MHz version
...
Signed-off-by: Olof Johansson <olof@lixom.net>
When building a legacy (non-multi) platforms and if the ARCH_AT91 config option
is enabled there is a build error. We need AT91 to depend on multi-platform
core type options.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds support for the N900's accelerometer to
the Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Éric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Keeping drivers related to HW tracing on ARM, i.e coresight,
under "drivers/coresight" doesn't make sense when other
architectures start rolling out technologies of the same
nature.
As such creating a new "drivers/hwtracing" directory where all
drivers of the same kind can reside, reducing namespace
pollution under "drivers/".
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.
Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Most CoreSight blocks are 64-bit ready. As such move configuration
entries from "arch/arm/Kconfig.config" to the driver's subdirectory
and source the newly created Kconfig from architecture specific
Kconfig.debug files.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Now there are generic phy type constants declared in phy.h, migrate over to
using them rather than defining our own. This change has been done as one
atomic commit to be bisectable.
Note: The values of the defines are the same, so there is no ABI breakage
with this patch.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Replace the clockevents_notify() call with an explicit function call.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Link: http://lkml.kernel.org/r/2131111.rjxRLX1eZB@vostro.rjw.lan
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Replace the clockevents_notify() call with an explicit function call.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Lindgren <tony@atomide.com>
Link: http://lkml.kernel.org/r/3123047.uVjevtxDV7@vostro.rjw.lan
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Replace the clockevents_notify() call with an explicit function call.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Lindgren <tony@atomide.com>
Link: http://lkml.kernel.org/r/2124877.3nbWGILHCV@vostro.rjw.lan
Signed-off-by: Ingo Molnar <mingo@kernel.org>
As part of addressing "y2038 problem" for in-kernel uses, this
patch converts read_boot_clock() to read_boot_clock64() and
read_persistent_clock() to read_persistent_clock64() using
timespec64 by converting clock_access_fn to use timespec64.
Signed-off-by: Xunlei Pang <pang.xunlei@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Acked-by: Thierry Reding <treding@nvidia.com> (for tegra part)
Cc: Russell King <rmk@dyn-67.arm.linux.org.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1427945681-29972-7-git-send-email-john.stultz@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
As part of addressing "y2038 problem" for in-kernel uses, this
patch adds the y2038-safe omap_read_persistent_clock64() using
timespec64.
Because we rely on some subsequent changes to convert arm
multiarch support, omap_read_persistent_clock() will be removed
then.
Also remove the needless spinlock, because
read_persistent_clock() doesn't run simultaneously.
Signed-off-by: Xunlei Pang <pang.xunlei@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1427945681-29972-5-git-send-email-john.stultz@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Conflicts:
drivers/net/usb/asix_common.c
drivers/net/usb/sr9800.c
drivers/net/usb/usbnet.c
include/linux/usb/usbnet.h
net/ipv4/tcp_ipv4.c
net/ipv6/tcp_ipv6.c
The TCP conflicts were overlapping changes. In 'net' we added a
READ_ONCE() to the socket cached RX route read, whilst in 'net-next'
Eric Dumazet touched the surrounding code dealing with how mini
sockets are handled.
With USB, it's a case of the same bug fix first going into net-next
and then I cherry picked it back into net.
Signed-off-by: David S. Miller <davem@davemloft.net>
The omap3isp MMIO register block is contiguous in the MMIO register space
apart from the fact that the ISP IOMMU register block is in the middle of
the area. Ioremap it at two occasions, and keep the rest of the layout of
the register space internal to the omap3isp driver.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
The syscon register isn't part of the ISP, use it through the syscom driver
regmap instead. The syscom block is considered to be from 343x on ISP
revision 2.0 whereas 15.0 is assumed to have 3630 syscon.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Make omap3isp configuration data structures more suitable for consumption by
the DT by separating the I2C bus information of all the sub-devices in a
group and the ISP bus information from each other. The ISP bus information
is made a pointer instead of being directly embedded in the struct.
In the case of the DT only the sensor specific information on the ISP bus
configuration is retained. The structs are renamed to reflect that.
After this change the structs needed to describe device configuration can be
allocated and accessed separately without those needed only in the case of
platform data. The platform data related structs can be later removed once
the support for platform data can be removed.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Igor Grinberg <grinberg@compulab.co.il> (for cm-t35)
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
The "MAKEFLAGS += --include-dir=$(srctree)" line in the top Makefile
allows us to do this.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Enabling CPU_DCACHE_DISABLE on a SMP capable system will prevent the
kernel from booting because of the following ldrex instruction in
arch_spin_lock:
(gdb) x/10i $pc
=> 0xc053cfa8 <_raw_spin_lock+4>: ldrex r3, [r0]
0xc053cfac <_raw_spin_lock+8>: add r2, r3, #65536 ; 0x10000
which is taken by the very first printk call:
at /home/fainelli/work/linux/arch/arm/include/asm/spinlock.h:65
fmt=0xc0637650 " 01 66Booting Linux on physical CPU 0x%xn", args=<incomplete type>)
at kernel/printk/printk.c:1525
fmt=0xc05370f4 <printk+52> " 24320215342 04340235344 20320215342 36377/341 17") at kernel/printk/printk.c:1688
ldrex requires exclusive monitor(s) (local or global) which are no longer
working when the Data cache is disabled in CP15 and will just hang the CPU
there.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Several interrupt controllers support both edge and level interrupts, so
it's useful to provide that information in /proc/interrupts.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When trying to kexec into a new kernel on a platform where multiple CPU
cores are present, but no SMP bringup code is available yet, the
kexec_load system call fails with:
kexec_load failed: Invalid argument
The SMP test added to machine_kexec_prepare() in commit 2103f6cba6
("ARM: 7807/1: kexec: validate CPU hotplug support") wants to prohibit
kexec on SMP platforms where it cannot disable secondary CPUs.
However, this test is too strict: if the secondary CPUs couldn't be
enabled in the first place, there's no need to disable them later at
kexec time. Hence skip the test in the absence of SMP bringup code.
This allows to add all CPU cores to the DTS from the beginning, without
having to implement SMP bringup first, improving DT compatibility.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
IOMMU should be able to use single pages as well as bigger blocks, so if
higher order allocations fail, we should not affect state of the system,
with events such as OOM killer, but rather fall back to order 0
allocations.
This patch changes the behavior of ARM IOMMU DMA allocator to use
__GFP_NORETRY, which bypasses OOM invocation, for orders higher than
zero and, only if that fails, fall back to normal order 0 allocation
which might invoke OOM killer.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: David Rientjes <rientjes@google.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move shutdown and reboot related code to a separate file, out of
process.c. This helps to avoid polluting process.c with non-process
related code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Normally, when a CPU wants to clear a cache line to zero in the external
L2 cache, it would generate bus cycles to write each word as it would do
with any other data access.
However, a Cortex A9 connected to a L2C-310 has a specific feature where
the CPU can detect this operation, and signal that it wants to zero an
entire cache line. This feature, known as Full Line of Zeros (FLZ),
involves a non-standard AXI signalling mechanism which only the L2C-310
can properly interpret.
There are separate enable bits in both the L2C-310 and the Cortex A9 -
the L2C-310 needs to be enabled and have the FLZ enable bit set in the
auxiliary control register before the Cortex A9 has this feature
enabled.
Unfortunately, the suspend code was not respecting this - it's not
obvious from the code:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image()
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
At this point, we end up with the L2C disabled, but the Cortex A9 with
FLZ enabled - which means any memset() or zeroing of a full cache line
will fail to take effect.
A similar issue exists in the resume path, but it's slightly more
complex:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image() /* image with A9 auxcr saved */
...
swsusp_arch_resume()
call_with_stack()
arch_restore_image() /* restores image with A9 auxcr saved above */
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
Again, here we end up with the L2C disabled, but Cortex A9 FLZ enabled.
There's no need to turn off the L2C in either of these two paths; there
are benefits from not doing so - for example, the page copies will be
faster with the L2C enabled.
Hence, fix this by providing a variant of soft_restart() which can be
used without turning the L2 cache controller off, and use it in both
of these paths to keep the L2C enabled across the respective resume
transitions.
Fixes: 8ef418c717 ("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
Reported-by: Sean Cross <xobs@kosagi.com>
Tested-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- reworked arch/arm/mach-at91/Kconfig and arch/arm/Kconfig to switch to
multi-platform
- updated at91_dt_defconfig
- continue the cleanup of unneeded files and code chunks
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Merge tag 'at91-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/multiplatform
Merge "at91: multiplatform for 4.1 #1" from Nicolas Ferre:
This is the multi-platform support for AT91:
- reworked arch/arm/mach-at91/Kconfig and arch/arm/Kconfig to switch to
multi-platform
- updated at91_dt_defconfig
- continue the cleanup of unneeded files and code chunks
* tag 'at91-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (61 commits)
ARM: at91: drop AT91_TIMER_HZ
ARM: at91: remove hardware.h
ARM: at91: remove SoC headers
ARM: at91: remove useless mach/cpu.h
ARM: at91: remove unused headers
ARM: at91: switch at91_dt_defconfig to multiplatform
ARM: at91: switch to multiplatform
ARM: at91: remove useless include
clocksource: atmel-st: remove mach/hardware dependency
clocksource: atmel-st: use syscon/regmap
ARM: at91: time: move the system timer driver to drivers/clocksource
ARM: at91: properly initialize timer
ARM: at91: at91rm9200: remove deprecated arm_pm_restart
watchdog: at91rm9200: implement restart handler
watchdog: at91rm9200: use the system timer syscon
mfd: syscon: Add atmel system timer registers definition
ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
ARM: at91: remove old setup
ARM: at91: sama5d4: remove useless map_io
ARM: at91: sama5 use SoC detection infrastructure
...
Signed-off-by: Olof Johansson <olof@lixom.net>
non-urgent fixes for DaVinci McASP platform
support code.
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Merge tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/cleanup
Merge "DaVinci McASP changes for v4.1" from Sekhar Nori:
This pull request contains cleanups and non-urgent fixes for DaVinci
McASP platform support code.
* tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: dm646x: Add interrupt resource for McASPs
ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
ARM: davinci: dm646x: Clean up the McASP DMA resources
ARM: davinci: devices-da8xx: Add support for McASP2 on da830
ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation
ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs
ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas R-Car sound (= rsnd) needs 2 DMAC which are called as
Audio DMAC (= 1st DMAC) and Audio DMAC peri peri (2nd DMAC).
And rsnd had assumed that 1st / 2nd DMACs are implemented as DMAEngine.
But, in result of DMA ML discussion, 2nd DMAC was concluded that it is
not a general purpose DMAC (2nd DMAC is for Device to Device inside
sound system). Additionally, current DMAEngine can't support Device to
Device, and we don't have correct DT bindings for it at this point.
So the easiest solution for it is that move it from DMAEngine to rsnd
driver.
Audio DMAC peri peri DMAEngine is no longer needed.
Remove all CONFIG_RCAR_AUDMAC_PP from ARM defconfigs
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add DMA sound support to r8a7791 and r8a7790 SoCs
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Merge tag 'renesas-dt3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Third Round of Renesas ARM Based SoC DT Updates for v4.1" from Simon
Horman:
* Add DMA sound support to r8a7791 and r8a7790 SoCs
* tag 'renesas-dt3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: sound enables Audio DMAC entry on DTSI
ARM: shmobile: r8a7790: sound enables Audio DMAC entry on DTSI
ARM: shmobile: r8a7791: enable Audio DMAC peri peri via sound driver
ARM: shmobile: r8a7790: enable Audio DMAC peri peri via sound driver
ARM: shmobile: r8a7791: add reg-names for sound
ARM: shmobile: r8a7790: add reg-names for sound
Signed-off-by: Olof Johansson <olof@lixom.net>
the gmac on the firefly board. A new board the Popmetal-rk3288 is also
added. And finally the pmic supplies for act8846 based boards are added,
as the act8865/act8846 driver gained supply handling in the regulator tree.
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Merge tag 'v4.1-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "ARM: rockchip: dts changes for 4.1" from Heiko Stuebner:
This adds and enables the usbphy nodes on the rk3288 boards and enables
the gmac on the firefly board. A new board the Popmetal-rk3288 is also
added. And finally the pmic supplies for act8846 based boards are added,
as the act8865/act8846 driver gained supply handling in the regulator tree.
* tag 'v4.1-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: complete rk3288-evb pmic supplies
ARM: dts: rockchip: add input supplies for the act8846 on Radxa Rock
ARM: dts: add rk3288 PopMetal board
dt-bindings: add root compatible property for PopMetal board
ARM: dts: rockchip: enable gmac on rk3288-firefly
ARM: dts: rockchip: enable usbphy on rk3288-firefly
ARM: dts: rockchip: Enable usb PHY on rk3288-evb board
ARM: dts: rockchip: add rk3288 usb PHY
Signed-off-by: Olof Johansson <olof@lixom.net>
watchdog does not reset after 12 hours and a change to constify and
staticize some smp parts.
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Merge tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc
Merge "ARM: rockchip: soc code changes for 4.1" from Heiko Stuebner:
Some suspend improvements reducing resume time and making sure the
watchdog does not reset after 12 hours and a change to constify and
staticize some smp parts.
* tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: disable watchdog during suspend
ARM: rockchip: decrease the wait time for resume
ARM: rockchip: Constify struct regmap_config and staticize local function
Signed-off-by: Olof Johansson <olof@lixom.net>
* Merged the based Qualcomm SCM and SCM boot support
* Cleaned up SCM interface to only expose functional SCM APIs
* Moved Qualcomm SCM code into drivers/firmware
* Updated the SCM APIs for setting cpu cold and warm boot addresses
* Added support for ADM CRCI muxing
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Merge tag 'qcom-soc-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers
Merge "qcom SoC changes for v4.1" from Kumar Gala:
Qualcomm ARM Based SoC Updates for v4.1
* Merged the based Qualcomm SCM and SCM boot support
* Cleaned up SCM interface to only expose functional SCM APIs
* Moved Qualcomm SCM code into drivers/firmware
* Updated the SCM APIs for setting cpu cold and warm boot addresses
* Added support for ADM CRCI muxing
* tag 'qcom-soc-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
soc: qcom: gsbi: Add support for ADM CRCI muxing
firmware: qcom: scm: Support cpu power down through SCM
firmware: qcom: scm: Add qcom_scm_set_warm_boot_addr function
firmware: qcom: scm: Clean cold boot entry to export only the API
firmware: qcom: scm: Move the scm driver to drivers/firmware
ARM: qcom: Prep scm code for move to drivers/firmware
ARM: qcom: Cleanup scm interface to only export what is needed
ARM: qcom: Merge scm and scm boot code together
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add multiplatform support to sh73a0 and its kzm9g board
* Use Bus State Controller to enable ethernet for multiplatform sh73a0/kzm9g
* Add PM domain support to multiplatform sh73a0
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Merge tag 'renesas-sh73a0-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Merge "Renesas ARM Based SoC sh73a0 Multiplatform Updates for v4.1" from Simon
Horman:
* Add multiplatform support to sh73a0 and its kzm9g board
* Use Bus State Controller to enable ethernet for multiplatform sh73a0/kzm9g
* Add PM domain support to multiplatform sh73a0
* tag 'renesas-sh73a0-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
ARM: shmobile: sh73a0: Remove restart callback
ARM: shmobile: sh73a0 dtsi: Add PM domain support
ARM: shmobile: sh73a0: Remove unused sh73a0_add_standard_devices_dt()
ARM: shmobile: sh73a0 dtsi: Add Cortex-A9 TWD node
ARM: shmobile: kzm9g-reference: Remove board C code and DT file
ARM: shmobile: kzm9g dts: Move Ethernet node to BSC
ARM: shmobile: sh73a0 dtsi: Add Bus State Controller node
ARM: shmobile: kzm9g: Build DTS for Multiplatform
ARM: shmobile: kzm9g dts: Sync with kzm9g-reference dts
ARM: shmobile: sh73a0: Add Multiplatform support
ARM: shmobile: sh73a0: Introduce generic setup callback
ARM: shmobile: r8a7794: add SDHI DT support
ARM: shmobile: r8a7790: add ADSP clocks
ARM: shmobile: r8a7791: add ADSP clocks
ARM: shmobile: henninger: add CAN0 DT support
ARM: shmobile: r8a7791: add CAN DT support
ARM: shmobile: r8a7791: add CAN clocks
ARM: shmobile: r8a7790: add CAN DT support
ARM: shmobile: r8a7790: add CAN clocks
ARM: shmobile: emev2-kzm9d dts: Add PFC information for uart1
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Following the introduction of the Marvell Armada 39x support, let's
enable this support by default in multi_v7_defconfig.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <arm@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Use the new tick_suspend/resume_local() and get rid of the
homebrewn implementation of these in the ARM bL switcher. The
check for the cpumask is completely pointless. There is no harm
to suspend a per cpu tick device unconditionally. If that's a
real issue then we fix it proper at the core level and not with
some completely undocumented hacks in some random core code.
Move the tick internals to the core code, now that this nuisance
is gone.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
[ rjw: Rebase, changelog ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1655112.Ws17YsMfN7@vostro.rjw.lan
Signed-off-by: Ingo Molnar <mingo@kernel.org>
OMAP4, OMAP5 and DRA7 now parse DT entries for control module address spaces,
and set up syscon mappings appropriately. Low level IO init is updated to
remove the legacy control module mappings for these devices also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
omap4_ctrl_pad_readl/writel are no longer used by anybody, so remove
these. Syscon / pinctrl should be used to access the padconf area
instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The legacy control module APIs will be gone, thus convert the display
driver to use syscon. This change should eventually be moved to
display driver from the board directory.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tony Lindgren <tony@atomide.com>
This patch creates an l4_wkup interconnect for AM43xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM nodea as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Pinmux node should be a reference to the base one, not a complete re-write
of it. Having the node like this also prevents modifying the node layout
in the base am4372.dtsi file, which is needed for control module changes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates an l4_core interconnect for OMAP3, and moves some
of the generic peripherals under it. System control module nodes are
moved under this new interconnect also, and the SCM clock layout
is changed to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tony Lindgren <tony@atomide.com>
This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430
SoCs, and moves some of the generic peripherals under it. System control
module nodes are moved under this new interconnect also, and the SCM
clock layout is changed to use the new SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Control module driver needs to support syscon for register accesses, as
the DT hierarchy for control module driver is going to be changed. All
the control module related features will be moved under control module
node, including clocks, pinctrl, and generic configuration register
access. Temporary iomap is still provided very early in the boot for
access while syscon is not yet ready.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to read the register with every invocation of the function,
as the value is constant. Thus, cache the value in a static variable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Some of the TI clock providers will be converted to use syscon, thus
low-level regmap support is needed for the clock drivers also. This
patch adds this support, which can be enabled for individual drivers
in later patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The compatible DT node is now passed with the prm init, so there is no
need to do node matching here again. Added a new flag to the init data
also, to detect default IRQ support for OMAP4. Also, any booting omap4
DT setup always has a PRM node, so there is no need to check against
the special case where it would be missing.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Currently some cpu_is_X checks are used to setup prm_features, however
the same can be accomplished by just passing these flags from the PRM
init data. This is done in preparation to make PRM a separate driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This gets rid of need for some exported driver APIs, and simplifies the
initialization of the CM driver. Done in preparation to make CM a
separate driver. The init data is now also passed to the SoC specific
implementations, allowing future expansion to add feature flags etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
PRM device instance offset is now provided through the prm_init_data.
This gets rid of some cpu_is_X / soc_is_X calls from PRM core code,
preparing for PRM to be its own separate driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This gets rid of need for some exported driver APIs, and simplifies the
initialization of the PRM driver. Done in preparation to make PRM a
separate driver. The init data is now also passed to the SoC specific
implementations, allowing future expansion to add feature flags etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
On Armada 38x SoCs, under heavy I/O load, the system hangs when CPU
Idle is enabled. Waiting for a solution to this issue, this patch
disables the CPU Idle support for this SoC.
As CPU Hot plug support also uses some of the CPU Idle functions it is
also affected by the same issue. This patch disables it also for the
Armada 38x SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.17 +
Flag all ARMv8 AES helper ciphers as internal ciphers to prevent
them from being called by normal users.
Signed-off-by: Stephan Mueller <smueller@chronox.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Flag all NEON bit sliced AES helper ciphers as internal ciphers to
prevent them from being called by normal users.
Signed-off-by: Stephan Mueller <smueller@chronox.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Flag all GHASH ARMv8 vmull.p64 helper ciphers as internal ciphers
to prevent them from being called by normal users.
Signed-off-by: Stephan Mueller <smueller@chronox.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
As the infrastructure for eventfd has now been merged, report the
ioeventfd capability as being supported.
Signed-off-by: Nikolay Nikolaev <n.nikolaev@virtualopensystems.com>
[maz: grouped the case entry with the others, fixed commit log]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Currently we have struct kvm_exit_mmio for encapsulating MMIO abort
data to be passed on from syndrome decoding all the way down to the
VGIC register handlers. Now as we switch the MMIO handling to be
routed through the KVM MMIO bus, it does not make sense anymore to
use that structure already from the beginning. So we keep the data in
local variables until we put them into the kvm_io_bus framework.
Then we fill kvm_exit_mmio in the VGIC only, making it a VGIC private
structure. On that way we replace the data buffer in that structure
with a pointer pointing to a single location in a local variable, so
we get rid of some copying on the way.
With all of the virtual GIC emulation code now being registered with
the kvm_io_bus, we can remove all of the old MMIO handling code and
its dispatching functionality.
I didn't bother to rename kvm_exit_mmio (to vgic_mmio or something),
because that touches a lot of code lines without any good reason.
This is based on an original patch by Nikolay.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Cc: Nikolay Nikolaev <n.nikolaev@virtualopensystems.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Add the DT description for the SGTL5000 found on the Hummingboard Pro
model.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds some not yet defined pinfunctions. It also adds two
comments about mistakes in the i.MX25 reference manual so it is easier
to spot the difference between reference manual and pinfunction
definitions.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While adding the MSCM interrupt router, all interrupts have been moved
to vfxxx.dtsi again. However, some properties got lost. Readd the
missing interrupt properties.
Fixes: 97e6466ab9d0 ("ARM: dts: vf610: add Miscellaneous System Control
Module (MSCM)")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The Cubox has a recessed button between the HDMI and RJ-45 connectors
that wasn't mapped in the device tree, so I've mapped it to gpio-keys
BTN_0.
Signed-off-by: George Joseph <george.joseph@fairview5.com>
Tested-by: George Joseph <george.joseph@fairview5.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds a new file, tegra124-nyan-blaze-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Blaze.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the timings for the ram-code 1 is present as that's
what could be tested currently, though downstream has timings for more
ram-codes.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds a new file, tegra124-nyan-big-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Big.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the timings for the ram-code 1 is present as that's
what could be tested currently, though downstream has timings for more
ram-codes.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main Jetson TK1 device tree.
The data is generated from the V5.0.17 version of the DVFS tables.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds a node for the EMC memory controller. It is always enabled, but only
provides read-only functionality without board-specific timing tables.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Setup pwm lines as follows -
pwm1: In case HummingBoard base carrier; this pin drives through a serial
capacitor the mono out of the audio jack.
In case HummingBoard pro the this pad can be reached by wiring to
C8 capacitors on the board.
pwm2: Setup pwm2 on gpio-1 but leave the default function of the iopad as
a gpio.
The user can change the io pad mux in user space and therefore use
this function on gpio-1 (pin number 7 on the 26 pin header).
pwm3,pwm4: unused
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
[tweaked alias for pwm pinctrl group --rmk]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Enable the commented out PCF8523 RTC support for Hummingboard pro
base boards.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It may be useful to disable the internal snvs-rtc when an external rtc is
available. This patch adds a label so that dts files can disable it.
Based on a patch from Markus Pargmann for imx6qdl.dtsi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It may be useful to disable the internal snvs-rtc when an external rtc is
available. This patch adds a label so that dts files can disable it.
Based on a patch from Markus Pargmann for imx6qdl.dtsi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.
This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While converting the GPC code to a stacked irqchip, we lost the
possibility to change the CPU affinity of an interrupt routed
through the GPC.
This patch restore the expected behaviour by forwarding the
affinity setup to the underlying irqchip (GIC).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Warp has a Murata chip based on a BCM4330 that provides Wifi and Bluetooth
functionality.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
input values are only useful for pin functions which define a input
register. This patch removes all input values of pin functions which do
not have an input configuration register.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
USDHC2 port uses all the 8 data signals, so pass the 'bus-width' property
accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since PWMs are only useful if they are actually connected to an output pin,
let users enable them explicitly in their device trees where they should
also set up the pin configuration.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled and a list of clocks to be enabled during powerup
for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The chipidea driver adds an extra line of spam to the log when a
host-only chipidea instance is left set to the default of a dual role
controller.
[ 2.010873] ci_hdrc ci_hdrc.1: doesn't support gadget
Set the dr_mode property to host on all the host-only nodes
to avoid this warning.
Signed-off-by: Matt Porter <mporter@konsulko.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The WaRP Board is a Wearable Reference Plaform. The board features:
- Freescale i.MX6 SoloLite processor with 512MB of RAM
- Freescale FXOS8700CQ 6-axis Xtrinsic sensor
- Freescale Kinetis KL16 MCU
- Freescale Xtrinsic MMA955xL intelligent motion sensing platform
The board implements a hybrid architecture to address the evolving
needs of the wearables market. The platform consists of a main board
and an example daughtercard with the ability to add additional
daughtercards for different usage models.
For more information about the project, visit:
http://www.warpboard.org/
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The anyway depricated gpio-range-cells property was never used
by the pin controller driver. This patch removes it.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add some defines currently missing, fix ordering to make the list
sorted by (mux_reg, mux_val), make sure pins are grouped by mux_reg.
The same definitions are missing from the old pinmux header
(arch/arm/mach-imx/iomux-mx25.h) but as only legacy machine support uses
that and therefor the existing list is obviously good enough I didn't
spend the effort to add the corresponding definitions there, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Noticed while looking over the pad definitions. None of the bogus
definitions is used in-tree.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It may be useful to disable the internal rtc snvs-rtc because an
external rtc is available. This patch adds a label so that board files
can disable this rtc.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device. This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since imx6sx-sdb reva board is experimental and will not be used
formally (eg, no software release based on it), we set revb board
as the formal imx6sx-sdb board.
The imx6sx-sdb uses pfuse200 as pmic which has only one power supply
for both VDDARM_IN and VDDSOC_IN, so VDDARM_IN and VDDSOC_IN have to
use the same (higher one in the same frequency) one as its power supply,
that's the reason we override the OPP setting in board dts file.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The imx6sx sdb board has two revisions, the current mainline one
is reva which is experimental and mainly for internal use. In
this commit, we rename imx6sx-sdb.dts to imx6sx-sdb.dtsi, and
move the reva dedicated contents to imx6sx-sdb-reva.dts.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
MCP2515 CAN controller is available on Colibri Evaluation board.
Hence enable MCP2515 CAN.
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This code calls cpu_resume() using a straight branch (b), so
now that we have moved cpu_resume() back to .text, this should
be moved there as well.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This code calls cpu_resume() using a straight branch (b), so
now that we have moved cpu_resume() back to .text, this should
be moved there as well. Any direct references to symbols that will
remain in the .data section are replaced with explicit PC-relative
references.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move cpu_resume() to the .text section where it belongs. Change
the adr reference to sleep_save_sp to an explicit PC relative
reference so sleep_save_sp itself can remain in .data.
This helps prevent linker failure on large kernels, as the code
in the .data section may be too far away to be in range for normal
b/bl instructions.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When building a very large kernel, it is up to the linker to decide
when and where to insert stubs to allow calls to functions that are
out of range for the ordinary b/bl instructions.
However, since the kernel is built as a position dependent binary,
these stubs (aka veneers) may contain absolute addresses, which will
break far calls performed with the MMU off.
For instance, the call from __enable_mmu() in the .head.text section
to __turn_mmu_on() in the .idmap.text section may be turned into
something like this:
c0008168 <__enable_mmu>:
c0008168: f020 0002 bic.w r0, r0, #2
c000816c: f420 5080 bic.w r0, r0, #4096
c0008170: f000 b846 b.w c0008200 <____turn_mmu_on_veneer>
[...]
c0008200 <____turn_mmu_on_veneer>:
c0008200: 4778 bx pc
c0008202: 46c0 nop
c0008204: e59fc000 ldr ip, [pc]
c0008208: e12fff1c bx ip
c000820c: c13dfae1 teqgt sp, r1, ror #21
[...]
c13dfae0 <__turn_mmu_on>:
c13dfae0: 4600 mov r0, r0
[...]
After adding --pic-veneer to the LDFLAGS, the veneer is emitted like
this instead:
c0008200 <____turn_mmu_on_veneer>:
c0008200: 4778 bx pc
c0008202: 46c0 nop
c0008204: e59fc004 ldr ip, [pc, #4]
c0008208: e08fc00c add ip, pc, ip
c000820c: e12fff1c bx ip
c0008210: 013d7d31 teqeq sp, r1, lsr sp
c0008214: 00000000 andeq r0, r0, r0
Note that this particular example is best addressed by moving
.head.text and .idmap.text closer together, but this issue could
potentially affect any code that needs to execute with the
MMU off.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This moves all fixup snippets to the .text.fixup section, which is
a special section that gets emitted along with the .text section
for each input object file, i.e., the snippets are kept much closer
to the code they refer to, which helps prevent linker failure on
large kernels.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arm64 builds with GCC 5 have caused the __asmeq assertions in the PSCI
calling code to fire, so move the ARM PSCI calls out of line into their
own assembly file for consistency and to safeguard against the same
issue occuring with the 32-bit toolchain.
[will: brought into line with arm64 implementation]
Reported-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The latest and greatest fixes for ARM platform code. Worth pointing out are:
- Lines-wise, largest is a PXA fix for dealing with interrupts on DT that was
quite broken. It's still newish code so while we could have held this off,
it seemed appropriate to include now
- Some GPIO fixes for OMAP platforms added a few lines. This was also fixes for
code recently added (this release).
- Small OMAP timer fix to behave better with partially upstreamed platforms,
which is quite welcome.
- Allwinner fixes about operating point control, reducing overclocking in some
cases for better stability.
+ a handful of other smaller fixes across the map.
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Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"The latest and greatest fixes for ARM platform code. Worth pointing
out are:
- Lines-wise, largest is a PXA fix for dealing with interrupts on DT
that was quite broken. It's still newish code so while we could
have held this off, it seemed appropriate to include now
- Some GPIO fixes for OMAP platforms added a few lines. This was
also fixes for code recently added (this release).
- Small OMAP timer fix to behave better with partially upstreamed
platforms, which is quite welcome.
- Allwinner fixes about operating point control, reducing
overclocking in some cases for better stability.
plus a handful of other smaller fixes across the map"
* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: juno: Fix misleading name of UART reference clock
ARM: dts: sunxi: Remove overclocked/overvoltaged OPP
ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting
ARM: socfpga: dts: fix spi1 interrupt
ARM: dts: Fix gpio interrupts for dm816x
ARM: dts: dra7: remove ti,hwmod property from pcie phy
ARM: OMAP: dmtimer: disable pm runtime on remove
ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure
ARM: OMAP2+: Fix socbus family info for AM33xx devices
ARM: dts: omap3: Add missing dmas for crypto
ARM: dts: rockchip: disable gmac by default in rk3288.dtsi
MAINTAINERS: add rockchip regexp to the ARM/Rockchip entry
ARM: pxa: fix pxa interrupts handling in DT
ARM: pxa: Fix typo in zeus.c
ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage
There's a few fixes to merge for 4.0, one to add a select in the machine
Kconfig option to fix a potential build failure, and two fixing cpufreq related
issues.
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Merge tag 'sunxi-fixes-for-4.0' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Allwinner fixes for 4.0
There's a few fixes to merge for 4.0, one to add a select in the machine
Kconfig option to fix a potential build failure, and two fixing cpufreq related
issues.
* tag 'sunxi-fixes-for-4.0' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dts: sunxi: Remove overclocked/overvoltaged OPP
ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting
ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fix a device tree based booting vs legacy booting regression for
omap3 crypto hardware by adding the missing DMA channels.
- Fix /sys/bus/soc/devices/soc0/family for am33xx devices.
- Fix two timer issues that can cause hangs if the timer related
hwmod data is missing like it often initially is for new SoCs.
- Remove pcie hwmods entry from dts as that causes runtime PM to
fail for the PHYs.
- A paper bag type dts configuration fix for dm816x GPIO
interrupts that I just noticed. This is most of the changes
diffstat wise, but as it's a basic feature for connecting
devices and things work otherwise, it should be fixed.
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Merge tag 'fixes-v4.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for the -rc cycle:
- Fix a device tree based booting vs legacy booting regression for
omap3 crypto hardware by adding the missing DMA channels.
- Fix /sys/bus/soc/devices/soc0/family for am33xx devices.
- Fix two timer issues that can cause hangs if the timer related
hwmod data is missing like it often initially is for new SoCs.
- Remove pcie hwmods entry from dts as that causes runtime PM to
fail for the PHYs.
- A paper bag type dts configuration fix for dm816x GPIO
interrupts that I just noticed. This is most of the changes
diffstat wise, but as it's a basic feature for connecting
devices and things work otherwise, it should be fixed.
* tag 'fixes-v4.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Fix gpio interrupts for dm816x
ARM: dts: dra7: remove ti,hwmod property from pcie phy
ARM: OMAP: dmtimer: disable pm runtime on remove
ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure
ARM: OMAP2+: Fix socbus family info for AM33xx devices
ARM: dts: omap3: Add missing dmas for crypto
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fix interrupt number for SPI1 interface
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Merge tag 'socfpga_fix_for_v4.0_2' of git://git.rocketboards.org/linux-socfpga-next into fixes
Late fix for v4.0 on the SoCFPGA platform:
- Fix interrupt number for SPI1 interface
* tag 'socfpga_fix_for_v4.0_2' of git://git.rocketboards.org/linux-socfpga-next:
ARM: socfpga: dts: fix spi1 interrupt
Signed-off-by: Olof Johansson <olof@lixom.net>
There are only 2 fixes, one for the zeus board about the regulator changes,
where a typo prevented the zeus board from having a working can regulator,
and one regression triggered by the interrupts IRQ shift of 16 affecting all
boards.
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Merge tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux into fixes
arm: pxa: fixes for v4.0-rc5
There are only 2 fixes, one for the zeus board about the regulator changes,
where a typo prevented the zeus board from having a working can regulator,
and one regression triggered by the interrupts IRQ shift of 16 affecting all
boards.
* tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux:
ARM: pxa: fix pxa interrupts handling in DT
ARM: pxa: Fix typo in zeus.c
Signed-off-by: Olof Johansson <olof@lixom.net>
When the patch for e16343c47e (ARM: 8160/1: drop warning about
return_address not using unwind tables) was created there was still more
code in said branch. Probably this simplification was just missed during
conflict resolution when the patch was applied.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch makes it possible to enter zImage in Thumb mode for ARMv7-M
(Cortex-M) CPUs that do not support ARM mode. The kernel entry is also
made in Thumb mode.
[ukl: fix spelling in commit log, return early in call_cache_fn]
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Stefan Agner <stefan@agner.ch>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Usually ELF_ET_DYN_BASE is 2/3 of TASK_SIZE. With 3G/1G user/kernel
split this is not so, because 2*TASK_SIZE overflows 32 bits,
so the actual value of ELF_ET_DYN_BASE is:
(2 * TASK_SIZE / 3) = 0x2a000000
When ASLR is disabled PIE binaries will load at ELF_ET_DYN_BASE address.
On 32bit platforms AddressSanitzer uses addresses [0x20000000 - 0x40000000]
for shadow memory [1]. So ASan doesn't work for PIE binaries when ASLR disabled
as it fails to map shadow memory.
Also after Kees's 'split ET_DYN ASLR from mmap ASLR' patchset PIE binaries
has a high chance of loading somewhere in between [0x2a000000 - 0x40000000]
even if ASLR enabled. This makes ASan with PIE absolutely incompatible.
Fix overflow by dividing TASK_SIZE prior to multiplying.
After this patch ELF_ET_DYN_BASE equals to (for CONFIG_VMSPLIT_3G=y):
(TASK_SIZE / 3 * 2) = 0x7f555554
[1] https://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm#Mapping
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Reported-by: Maria Guseva <m.guseva@samsung.com>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When running the 32-bit ARM kernel on ARMv8 capable bare metal (e.g.,
32-bit Android userland and kernel on a Cortex-A53), or as a KVM guest
on a 64-bit host, we should advertise the availability of the Crypto
instructions, so that userland libraries such as OpenSSL may use them.
(Support for the v8 Crypto instructions in the 32-bit build was added
to OpenSSL more than six months ago)
This adds the ID feature bit detection, and sets elf_hwcap2 accordingly.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The various CPU feature registers consist of 4-bit blocks that
represent signed quantities, whose positive values represent
incremental features, and whose negative values are reserved.
To improve forward compatibility, update the feature detection
code to take possible future higher values into account, but
ignore negative values.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This moves the .idmap.text section closer to .head.text, so that
relative branches are less likely to go out of range if the kernel
text gets bigger.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch replaces the 'branch to setup()' instructions embedded
in the PROCINFO structs with the offset to that setup function
relative to the base of the struct. This preserves the position
independent nature of that field, but uses a data item rather
than an instruction.
This is mainly done to prevent linker failures on large kernels,
where the setup function is out of reach for the branch.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Occasionally, there's a question about the method we use to find the
start of physical memory. Add some documentation so we don't have to
keep repeating outselves on the mailing list.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow users to enable the vdso in Kconfig; include the vdso in the
build if CONFIG_VDSO is enabled. Add 'vdso_install' target.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Initialize the VDSO page list at boot, install the VDSO mapping at
exec time, and update the data page during timer ticks. This code is
not built if CONFIG_VDSO is not enabled.
Account for the VDSO length when randomizing the offset from the
stack. The [vdso] and [vvar] pages are placed immediately following
the sigpage with separate _install_special_mapping calls.
We want to "penalize" systems lacking the arch timer as little
as possible. Previous versions of this code installed the VDSO
unconditionally and unmodified, making it a measurably slower way for
glibc to invoke the real syscalls on such systems. E.g. calling
gettimeofday via glibc goes from ~560ns to ~630ns on i.MX6Q.
If we can indicate to glibc that the time-related APIs in the VDSO are
not accelerated, glibc can continue to invoke the syscalls directly
instead of dispatching through the VDSO only to fall back to the slow
path.
Thus, if the architected timer is unusable for whatever reason, patch
the VDSO at boot time so that symbol lookups for gettimeofday and
clock_gettime return NULL. (This is similar to what powerpc does and
borrows code from there.) This allows glibc to perform the syscall
directly instead of passing control to the VDSO, which minimizes the
penalty. In my measurements the time taken for a gettimeofday call
via glibc goes from ~560ns to ~580ns (again on i.MX6Q), and this is
solely due to adding a test and branch to glibc's gettimeofday syscall
wrapper.
An alternative to patching the VDSO at boot would be to not install
the VDSO at all when the arch timer isn't usable. Another alternative
is to include a separate "dummy" vdso.so without gettimeofday and
clock_gettime, which would be selected at boot time. Either of these
would get cumbersome if the VDSO were to gain support for an API such
as getcpu which is unrelated to arch timer support.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Place VDSO-related user-space code in arch/arm/kernel/vdso/.
It is almost completely written in C with some assembly helpers to
load the data page address, sample the counter, and fall back to
system calls when necessary.
The VDSO can service gettimeofday and clock_gettime when
CONFIG_ARM_ARCH_TIMER is enabled and the architected timer is present
(and correctly configured). It reads the CP15-based virtual counter
to compute high-resolution timestamps.
Of particular note is that a post-processing step ("vdsomunge") is
necessary to produce a shared object which is architecturally allowed
to be used by both soft- and hard-float EABI programs.
The 2012 edition of the ARM ABI defines Tag_ABI_VFP_args = 3 "Code is
compatible with both the base and VFP variants; the user did not
permit non-variadic functions to pass FP parameters/results."
Unfortunately current toolchains do not support this tag, which is
ideally what we would use.
The best available option is to ensure that both EF_ARM_ABI_FLOAT_SOFT
and EF_ARM_ABI_FLOAT_HARD are unset in the ELF header's e_flags,
indicating that the shared object is "old" and should be accepted for
backward compatibility's sake. While binutils < 2.24 appear to
produce a vdso.so with both flags clear, 2.24 always sets
EF_ARM_ABI_FLOAT_SOFT, with no way to inhibit this behavior. So we
have to fix things up with a custom post-processing step.
In fact, the VDSO code in glibc does much less validation (including
checking these flags) than the code for handling conventional
file-backed shared libraries, so this is a bit moot unless glibc's
VDSO code becomes more strict.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Define the layout of the data structure shared between kernel and
userspace.
Track the vdso address in the mm_context; needed for communicating
AT_SYSINFO_EHDR to the ELF loader.
Add declarations for arm_install_vdso; implementation is in a
following patch.
Define AT_SYSINFO_EHDR, and, if CONFIG_VDSO=y, report the vdso shared
object address via the ELF auxiliary vector.
Note - this adds the AT_SYSINFO_EHDR in a new user-visible header
asm/auxvec.h; this is consistent with other architectures.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM errata 798181 is applicable for OMAP5/DRA7 based devices. So enable
the same in the build.
DRA7xx is based on Cortex-A15 r2p2 revision.
ARM Errata extract and workaround information is as below.
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
adequately shooting down all use of the old entries. The
ARM_ERRATA_798181 option enables the Linux kernel workaround
for this erratum which sends an IPI to the CPUs that are running
the same ASID as the one being invalidated.
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
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Merge tag 'for-v4.1/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.1/soc
OMAP hwmod data changes for AM43xx and DRA7xx for v4.1
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
The maintainers for mach-msm no longer have any plans to support
or test the platforms supported by this architecture[1]. Most likely
there aren't any active users of this code anyway, so let's
delete it.
[1] http://lkml.kernel.org/r/20150307031212.GA8434@fifo99.com
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This patch separates the PMU driver code from the low level
CCI driver code and enables the PMU driver for ARM64.
Introduces config options for both.
ARM_CCI400_PORT_CTRL - controls the low level driver code for
CCI400 ports.
ARM_CCI400_PMU - controls the PMU driver code
ARM_CCI400_COMMON - Common defintions for CCI400
This patch also changes:
ARM_CCI - common code for probing the CCI devices. This can be
used for adding support for newer CCI versions(e.g, CCI-500).
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Avoid secure transactions while probing the CCI PMU. The
existing code makes use of the Peripheral ID2 (PID2) register
to determine the revision of the CCI400, which requires a
secure transaction. This puts a limitation on the usage of the
driver on systems running non-secure Linux(e.g, ARM64).
Updated the device-tree binding for cci pmu node to add the explicit
revision number for the compatible field.
The supported strings are :
arm,cci-400-pmu,r0
arm,cci-400-pmu,r1
arm,cci-400-pmu - DEPRECATED. See NOTE below
NOTE: If the revision is not mentioned, we need to probe the cci revision,
which could be fatal on a platform running non-secure. We need a reliable way
to know if we can poke the CCI registers at runtime on ARM32. We depend on
'mcpm_is_available()' when it is available. mcpm_is_available() returns true
only when there is a registered driver for mcpm. Otherwise, we assume that we
don't have secure access, and skips probing the revision number(ARM64 case).
The MCPM should figure out if it is safe to access the CCI. Unfortunately
there isn't a reliable way to indicate the same via dtb. This patch doesn't
address/change the current situation. It only deals with the CCI-PMU, leaving
the assumptions about the secure access as it has been, prior to this patch.
Cc: devicetree@vger.kernel.org
Cc: Punit Agrawal <punit.agrawal@arm.com>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Just as we thought we'd fixed this, another old linker reared its ugly
head trying to build linux-next. Unfortunately, it's the linker binary
provided on kernel.org, so give up trying to be clever and align the
hyp page to 4k.
Older binutils do not support expressions involving the values of
external symbols so just round up the HYP region to the page size.
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[will: when will this ever end?!]
Signed-off-by: Will Deacon <will.deacon@arm.com>
board-rx51 has no card detect pin in the mmc slot, but can detect that
the (cell-phone) cover has been removed and the card is accessible.
The semantics between cover/card detect differ, the gpio on the slot
informs you after the card has been removed, cover removal does not
necessarily mean that the card has been removed.
This means different code paths are necessary. To complete this we
also want different fields in the platform data for cover and card
detect. This separation is not pushed all the way down into struct
omap2_hsmmc_info which is used to initialize the platform data.
If we did that we had to go over all board files and set the new
gpio_cod pin to -EINVAL. If we forget one board or some out-of-tree
archicture forgets that the default '0' is used which is a valid pin
number.
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
'enum clock_event_mode' is used for two purposes today:
- to pass mode to the driver of clockevent device::set_mode().
- for managing state of the device for clockevents core.
For supporting new modes/states we have moved away from the
legacy set_mode() callback to new per-mode/state callbacks. New
modes/states shouldn't be exposed to the legacy (now OBSOLOTE)
callbacks and so we shouldn't add new states to 'enum
clock_event_mode'.
Lets have separate enums for the two use cases mentioned above.
Keep using the earlier enum for legacy set_mode() callback and
mark it OBSOLETE. And add another enum to clearly specify the
possible states of a clockevent device.
This also renames the newly added per-mode callbacks to reflect
state changes.
We haven't got rid of 'mode' member of 'struct
clock_event_device' as it is used by some of the clockevent
drivers and it would automatically die down once we migrate
those drivers to the new interface. It ('mode') is only updated
now for the drivers using the legacy interface.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Preeti U Murthy <preeti@linux.vnet.ibm.com>
Cc: linaro-kernel@lists.linaro.org
Cc: linaro-networking@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/b6b0143a8a57bd58352ad35e08c25424c879c0cb.1425037853.git.viresh.kumar@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
An upcoming patch will depend on tai_ns() and NMI-safe ktime_get_raw_fast(),
so merge timers/core here in a separate topic branch until it's all cooked
and timers/core is merged upstream.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
There is no need to provide the control module base address through a
low-level API from the low-level IO init, as this information is
available through DT. This patch adds a new API to initialize the
control module though, but mostly makes the old API obsolete. The
old API can be completely removed once OMAP3 is made DT only.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to provide the PRM base address through a low-level API
from the low-level IO init, as this information is available through DT.
Re-routed the parsing function to be called from the PRM drivers also to
simplify the implementation under io.c.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to provide the CM base address through a low-level API
from the low-level IO init, as this information is available through DT.
Re-routed the parsing function to be called from the CM drivers also to
simplify the implementation under io.c.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Splits the clock related provider module inits under their own driver files.
Previously this was done for all modules under the common PRM driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Splits the clock provider init out of the PRM driver and moves it to
clock driver. This is needed so that once the PRCM drivers are separated,
they can logically just access the clock driver not needing to go through
common PRM code. This would be wrong in the case of control module for
example.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
When operating in left-justfied mode both the frame-clock and the
bit-clock need to be inverted to be standards compliant.
This means that the exta clock inversion setting in the armadillo800eva
machine driver for CPU component should now be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
The DAI link format should be specified for the whole link rather than just
one component on the link. So move the format specification for the HDMI
audio link from the CPU component to the link itself.
Since the sh-mobile-hdmi DAI driver doesn't implement the set_fmt() callback
in this case there is no functional difference between only specifying the
the format for the CPU side or for the whole link, but the later it will
allow us to remove support for just specifying the format for one component.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
virt/kvm was never really a good include directory for anything else
than locally included headers.
With the move of iodev.h there is no need anymore to add this
directory the compiler's include path, so remove it from the arm and
arm64 kvm Makefile.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
BeagleBoard-X15 has capability for a fan and has an onboard TMP102
temperature sensor as well. This allows us to create a new thermal
zone (called, un-imaginatively "board"), and allows us to use some
active cooling as temperatures start edge upward in the system by
creating a new alert temperature (emperically 50C) for cpu.
NOTE: Fan is NOT mounted by default on the platform, in such a case,
all we end up doing is switch on a regulator and leak very minimal
current.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7. Introduce CPU, GPU, core nodes
for the moment as they are direct reuse of OMAP5 entities.
NOTE: OMAP4 has a finer counter granularity, which allows for a delay
of 1000ms in the thermal zone polling intervals. DRA7 have different
counter mechanism, which allows at maximum a 500ms timer. Adjust the
cpu thermal zone accordingly for DRA7.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[t-kristo@ti.com: few reuse from OMAP5 entities]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added a new compatible string "ti,am437x-ocp2scp" for OCP2SCP module.
This is needed since except for the OCP2SCP used in AM437x, SYNC2 value
in OCP2SCP TIMING should be changed whereas the default value is sufficient
in AM437x.
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AFTR mode support brings reduced energy consumption and is
a prerequisite for more advanced W-AFTR/LPA power saving modes.
AFTR mode has been already supported on other Exynos SoCs for
few years and this patch adds its support for Exynos3250 SoC.
The differences in Exynos3250 SoC AFTR mode support when compared
to Exynos4x12 SoCs are:
- different secure firmware calls are used
- different S5P_WAKEUP_MASK wakeup mask is used
- S5P_WAKEUP_MASK2 wakeup mask needs to be set in addition to
the standard S5P_WAKEUP_MASK one
- C2_STATE BOOT mode flag needs to be set/cleared pre/post AFTR
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The NULL pointer check for superset->muxnames will always evaluate
true since muxnames is an array within struct omap_mux. Remove the
superfluous check to avoid warnings when using LLVM/clang.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This code is needed for cpuidle (W-)AFTR mode support on Exynos3250.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
This patch also fixes hotplug issues during resume from S2R:
$ echo mem > /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Many Exynos boards have an HDMI port so enable Exynos DRM HDMI
support.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
There are two PMICs on Cragganmore, currently one dynamically assign
its IRQ base and the other uses a fixed base. It is possible for the
statically assigned PMIC to fail if its IRQ is taken by the dynamically
assigned one. Fix this by statically assigning both the IRQ bases.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Changes fixes the misspelled of #interrups-cell.
arch/arm/boot/dts/exynos5420.dtsi:224: WARNING: 'interrups'
may be misspelled - perhaps 'interrupts'?
Tested on OdroidXU3 board.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
[kgene@kernel.org: added fixing same typo in exynos5250]
Signed-off-by: Kukjin Kim <kgene@kernel.org>
HS400 timing values are added for SMDK5420, exynos5420-peach-pit
and exynos5800-peach-pi boards. This also adds RCLK GPIO line,
this gpio should be in pull-down state.
This also enables HS400 on peach-pi and this updates the clock
frequency to 800MHz to be set as input clock to controller.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
[alim.akhtar@samsung.com: addressed review comments]
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
This patch enables the options to mount a rootfs over NFS and also
support for automatic configuration of IP addresses during boot as
needed by NFS.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
There are currently more than 16 partitions on the eMMC of all recent
Qualcomm devices. Increase the number of minors per block device to
detect all available partitions.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Using ASSERT() with an expression that involves a symbol that
is only supplied through a PROVIDE() definition in the linker
script itself is apparently not supported by some older versions
of binutils.
So instead, rewrite the expression so that only the section
boundaries __hyp_idmap_text_start and __hyp_idmap_text_end
are used. Note that this reverts the fix in 06f75a1f62
("ARM, arm64: kvm: get rid of the bounce page") for the ASSERT()
being triggered erroneously when unrelated linker emitted veneers
happen to end up in the HYP idmap region.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
All clock provider related drivers will now register their iomaps
with a static index. This makes it easier to split up the individual
drivers to their own files in subsequent patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
OMAP4 has different ordering of PRM and CM init calls in the early init.
Re-oder these accordingly for OMAP4 also. This is needed so that we
can do some optimizations in the following patches for the PRCM init.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to call this separately from io.c, rather this can be
done commonly under the CM driver. Also, this patch makes the API static,
as it is no longer used outside the driver file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to call this separately from io.c, rather this can be
done commonly under the PRM driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
OMAP2/3 now use generic API for the prm_clear_mod_irqs, the SoC specific
implementation details are provided through prm_ll_data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This makes the API the same as used with OMAP2, and makes it possible
to implement a generic driver API for the functionality.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The const declaration for char* is actually duplicated, however
the array of strings is currently not constant. However, typically
the dt_compat array is declared as const char *const. Follow
that convention and also add the __initconst macro for constant
initialization data.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Branden <sbranden@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Tested-by: Ray Jui <rjui@broadcom.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Without proper regulator support for individual boards, it is dangerous
to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase
the frequency without the accompanying voltage increase, resulting in
an unstable system.
Remove them for now. We can revisit them with the new version of OPP
bindings, which support boost settings and frequency ranges, among
other things.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Olimex A10-Lime is known to be unstable when running at 1008MHz.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
GPTimer 4 is a regular timer and not a secure timer, so fix
the hwmod to use the correct hwmod class (even though there
are no differences in the class definition itself).
Signed-off-by: Suman Anna <s-anna@ti.com>
[paul@pwsan.com: dropped dra7xx_timer_secure_hwmod_class and
dra7xx_timer_secure_sysc to avoid compiler warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the hwmod data for GPTimers 13, 14, 15 and 16. All these
timers are present in the L4PER3 clock domain.
The corresponding DT nodes are already present but disabled.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Now that we have wlcore device-tree bindings in place
(for both wl12xx and wl18xx), remove the legacy
wl12xx_platform_data struct, and move its members
into the platform device data (that is passed to wlcore)
Davinci 850 is the only platform that still set
the platform data in the legacy way (and doesn't
have DT bindings), so remove the relevant
code/Kconfig option from the board file (as suggested
by Sekhar Nori)
Since no one currently uses wlcore_spi, simply remove its
platform data support (DT bindings will have to be added
if someone actually needs it)
Signed-off-by: Luciano Coelho <luca@coelho.fi>
Signed-off-by: Eliad Peller <eliad@wizery.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Kalle Valo <kvalo@codeaurora.org>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Replace all the pdata-quirks for setting wl12xx/wl18xx
platform data with proper DT definitions.
Signed-off-by: Eliad Peller <eliad@wizery.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Tony Lindgren <tony@atomide.com>
Acked-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Instead of defining an enumeration with the FW specific values for the
different clock rates, use the actual frequency instead. Also add a
boolean to specify whether the clock is XTAL or not.
Change all board files to reflect this.
Signed-off-by: Luciano Coelho <luca@coelho.fi>
[Eliad - small fixes, update board file changes]
Signed-off-by: Eliad Peller <eliad@wizery.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Kalle Valo <kvalo@codeaurora.org>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.
This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Even if the host controller doesn't have power during suspend, the card
is kept powered.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This fixes a bug in the new v8 Crypto Extensions GHASH code
that only manifests itself in big-endian mode.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The Nyan Chromebooks have a GPIO line dedicated to restarting the
system. Using this line will make sure that the TPM is restarted as
well.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Google has submitted a board config for the pinmux programming of the
Nyan Big board. Use the whole of it as it's generated to make it easier
to update as the configuration gets fixed in the future.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Nyan boards have a Marvell 88w8897 wifi card connected through SDIO
that needs the reset line to be asserted before mmc power up and deasserted
afterwards.
This patch also adds references to the power supplies of the card so that
the regulators are enabled when it's probed.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Nyan boards have a eKTH3000 from Elan as their trackpad, connected
through I2C.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
It's commercial name is HP Chromebook 14 and is substantially similar to
the Acer Chromebook 13 (nyan-big).
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
In preparation for adding the DT for the nyan-blaze board.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Change it from "Acer Chromebook 13" to GoogleNyanBig so it's unique and
identifiable.
With this change the card id exposed to userspace becomes GoogleNyanBig
instead of the current A13.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Replace the current incomplete pinmux setup with a proper one generated
using the tegra pinmux scripts.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded
from https://developer.nvidia.com/hardware-design-and-development.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current state of the different cpuidle drivers is the different PM
operations are passed via the platform_data using the platform driver
paradigm.
This approach allowed to split the low level PM code from the arch specific
and the generic cpuidle code.
Unfortunately there are complaints about this approach as, in the context of the
single kernel image, we have multiple drivers loaded in memory for nothing and
the platform driver is not adequate for cpuidle.
This patch provides a common interface via cpuidle ops for all new cpuidle
driver and a definition for the device tree.
It will allow with the next patches to a have a common definition with ARM64
and share the same cpuidle driver.
The code is optimized to use the __init section intensively in order to reduce
the memory footprint after the driver is initialized and unify the function
names with ARM64.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Rob Herring <robherring2@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Conflicts:
net/netfilter/nf_tables_core.c
The nf_tables_core.c conflict was resolved using a conflict resolution
from Stephen Rothwell as a guide.
Signed-off-by: David S. Miller <davem@davemloft.net>
Olof Johansson
Lina Iyer
Kenneth Westfield
Ivan T. Ivanov
Kumar Gala
Andy Gross
Nicolas Pitre
Nicolas Ferre
Sebastian Reichel
Mathieu Poirier
Kaixu Xia
Peter Griffin
Sami Tolvanen
Thomas Gleixner
Xunlei Pang
David S. Miller
Sakari Ailus
Ingo Molnar
Masahiro Yamada
Florian Fainelli
Geert Uytterhoeven
Tomasz Figa
Russell King
Kuninori Morimoto
Thomas Petazzoni
Tony Lindgren
Tero Kristo
Gregory CLEMENT
Stephan Mueller
Nikolay Nikolaev
Andre Przywara
Markus Pargmann
Stefan Agner
George Joseph
Matthias Brugger
Tomeu Vizoso
Mikko Perttunen
Rabeeh Khoury
Uwe Kleine-König
Fabio Estevam
Marc Zyngier
Peter Chen
Gwenhael Goavec-Merou
Philipp Zabel
Matt Porter
Otavio Salvador
Liu Ying
Bhuvanchandra DV
Shawn Guo
Ard Biesheuvel
Mark Rutland
Linus Torvalds
Joachim Eastwood
Andrey Ryabinin
Nathan Lynch
Praneeth Bajjuri
Stephen Boyd
Suzuki K. Poulose
Will Deacon
Andreas Fenkart
Viresh Kumar
Lars-Peter Clausen
Nishanth Menon
Keerthy
Kishon Vijay Abraham I
Bartlomiej Zolnierkiewicz
Javier Martinez Canillas
Charles Keepax
Anand Moon
Seungwon Jeon
Georgi Djakov
Daniel Lezcano
Chen-Yu Tsai
Suman Anna
Eliad Peller
Luciano Coelho
Lucas Stach
Stephen Warren
Bjorn Helgaas