Commit Graph

288 Commits

Author SHA1 Message Date
Linus Torvalds d4113f2f17 ARM: SoC: late fixes and dependencies
This is a collection of a few late fixes and other misc. stuff that
 had dependencies on things being merged from other trees.
 
 Other than the fixes, the primary feature being added is the
 conversion of some OMAP drivers to the new generic wakeirq interface.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVlXl/AAoJEFk3GJrT+8ZlDccQAJ5vxvImNvJmoqeCv+6Tkshm
 UOGtoTBWKu+1wVgvYvYWXbNL06NKtS1c/CP8CZE0V6XdLQ+EHd4RWsHyRLHi4xwS
 6qqtwVfqYwFLli++87NKqzizl01a0eImPiHl5Rwo9oFy0u81+lsivwWbCBk+Dh0n
 HtkmuKzWnKSYL3rgnApq1USL4dhbc6SbNYo0pwvZXNDTK57FrQN/2Z2Pl1FZS9RQ
 BQgnqDSdhvF5PD/fWJ5KHs2k2WDtjMMN2TgVMtMjMg2x5kSMAN6fBwi49wYgcwUz
 ndHtuHosX4BkPgDHvzIv7jRCYHeRaHOYxbPG+tzYXci4gXUUEn3i8jte91Hb3+ri
 tDcgAnod+R1SoBmSRdj/nqM7Y8Qw7Pnjo2tuKYfb1NFaX5KtjrjaaDx/09G7PD+U
 fw400HKPi4r2h11n96Y5MZUbLv9XgB9BAePmIdNLuQZabFc1DcsUOG9JbRsMArRT
 5g6Sk+Lar9FGH32fLk5sGEAroFs52YmGmLviHKiAsbBSOV751SN2AcA8NDXBuKI1
 L+hC41NslENztHTgLsmEt6YY4H/4+jW66du5GYc4ZkPd1scO2+esXDzPZ864vxo+
 rIIMnRNQHb2hGiNvImyzEt2NgelSk/xKQR5Dl6MNiKCmiyw2XHlR5UTkRRBZXDd+
 5T1KnOvKE2THuxWyWARH
 =bhUU
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late fixes and dependencies from Kevin Hilman:
 "This is a collection of a few late fixes and other misc stuff that had
  dependencies on things being merged from other trees.

  Other than the fixes, the primary feature being added is the
  conversion of some OMAP drivers to the new generic wakeirq interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: multi_v7_defconfig: Enable BRCMNAND driver
  ARM: BCM: Do not select CONFIG_MTD_NAND_BRCMNAND
  ARM: at91/dt: update udc compatible strings
  ARM: at91/dt: trivial: fix USB udc compatible string
  arm64: dts: Add APM X-Gene standby GPIO controller DTS entries
  soc: qcom: spm: Fix idle on THUMB2 kernels
  ARM: dove: fix legacy dove IRQ numbers
  ARM: mvebu: fix suspend to RAM on big-endian configurations
  ARM: mvebu: adjust Armada XP DT spi muxing after pinctrl function rename
  serial: 8250_omap: Move wake-up interrupt to generic wakeirq
  serial: omap: Switch wake-up interrupt to generic wakeirq
  mmc: omap_hsmmc: Change wake-up interrupt to use generic wakeirq
2015-07-02 14:40:49 -07:00
Linus Torvalds 47f92418c7 Remove __cpuinit macros and users.
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVkO0aAAoJEOvOhAQsB9HWoRUQAII3ueftazj4ZYVEF5QBIdNL
 MrEyUbPMyXHYBKmcAVkig5N4JLkITvPnuT/LRQ3ba7gMyeYKUFCHpLniRHwGkHIJ
 UAHgDYzLXO7bv2ZhHiSk6ZL6XtEq2vY+dcedS26CAoR53erjmRiniakYhT/NbfSf
 rFfPKaVOH7E7yGn7OrFAASGSPlKbzjICqfnUQQi5Z9XxAfdXcHLiuX98KufSaXbM
 a27KDJudH11/guwCkACvD0C0NnUoRxe6X7/JyTmt/ldqH3f9JR2jEnDgrh/jakJE
 LgsguiHGcDuZjC1n4jb5n72Iua0zOtyrKhvDAZ77bG7NEcK6OlvhY0No3rEvXA9X
 XhScF3BUd1/pBKRwVALWTprHJ0q8HjQAfci1ONX9qMWNhjpY1jU6J8cUpAEKf8hk
 nHSsSesvsXKLogTEY05vF4sOUupILi1zlP/1dGDLXr/FVWX52U4BFlur67Vay7pN
 PtjvKl30Tw0yLOLkZwr53jKpqFZOgcTy+mm/DF3j2v77da1JXS94pCV3PcV8lNxT
 xlQPB2O6LvYn5LPnyJ8SwuLm466+OD3jfLNBPgXVLgZb+lY/GpL/mHgxoK+/FweH
 quHj3e7q3OWADxPEdnJswuCKpeG/w+jcpK7fWWo+4haC4bMcSDM42Dc78o9ve4rU
 E9Ex9ymil7W4DmAWsd2g
 =qNLm
 -----END PGP SIGNATURE-----

Merge tag 'cpuinit-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux

Pull __cpuinit removal from Paul Gortmaker:
 "Remove __cpuinit macros and users.

  We removed the __cpuinit stuff in 3.11-rc1 with commit 22f0a27367
  ("init.h: remove __cpuinit sections from the kernel") but we left some
  no-op stubs as a courtesy to unmerged code.

  Here we get rid of the stubs as well, since (as can be seen in these
  changes) they are enabling use cases to sneak back in, primarily from
  older BSP code that has been living out of tree for some time prior to
  getting mainlined.  So we get rid of these "new" users 1st and then
  get rid of the stubs.

  Obviously, getting rid of the stubs can't happen until all the users
  are gone, so I had to keep this together as a series, even though some
  of these commits since got picked up into maintainers trees as well.

  The nature of this change is such that it should have zero impact on
  the generated runtime.

  This is one of several independent cleanup branches aimed at enabling
  better organization in the init.h and module.h code.  They have been
  getting coverage in the linux-next tree for the last month, in
  addition to my local testing, which also covers approximately a half
  dozen or more architectures"

* tag 'cpuinit-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux:
  init: delete the __cpuinit related stubs
  kernel/cpu.c: remove new instance of __cpuinit that crept back in
  sched/core: remove __cpuinit section tag that crept back in.
  mips/mm/tlbex: remove new instance of __cpuinit that crept back in
  mips/c-r4k: remove legacy __cpuinit section that crept in
  mips/bcm77xx: remove legacy __cpuinit sections that crept in
  mips/ath25: remove legacy __cpuinit section that crept in
  arm/mach-hisi: remove legacy __CPUINIT section that crept in
  arm/mach-rockchip: remove legacy __cpuinit section that crept in
  arm/mach-mvebu: remove legacy __cpuinit sections that crept in
  arm/mach-keystone: remove legacy __cpuinit sections that crept in
2015-07-02 09:54:14 -07:00
Kevin Hilman 375d610ff5 mvebu fixes for 4.2 (part 0)
Fix legacy dove IRQ numbers
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlWSPfkACgkQCwYYjhRyO9VKKgCgmYkea99EaF8JyQnYxr5pAxGp
 c1cAn39dJD1oblKHzFl7BiUjNaigbXIp
 =kPSW
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-fixes-4.2-0' of git://git.infradead.org/linux-mvebu into next/late

Merge "ARM: mvebu: fixes for v4.2" from Gregory Clement:

mvebu fixes for 4.2 (part 0)

Fix legacy dove IRQ numbers

* tag 'mvebu-fixes-4.2-0' of git://git.infradead.org/linux-mvebu:
  ARM: dove: fix legacy dove IRQ numbers
  ARM: mvebu: fix suspend to RAM on big-endian configurations
2015-07-01 13:01:03 -07:00
Thomas Petazzoni 2f5bc307be ARM: mvebu: fix suspend to RAM on big-endian configurations
The current Armada XP suspend to RAM implementation, as added in
commit 27432825ae ("ARM: mvebu: Armada XP GP specific
suspend/resume code") does not handle big-endian configurations
properly: the small bit of assembly code putting the DRAM in
self-refresh and toggling the GPIOs to turn off power forgets to
convert the values to little-endian.

This commit fixes that by making sure the two values we will write to
the DRAM controller register and GPIO register are already in
little-endian before entering the critical assembly code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.19+
Fixes: 27432825ae ("ARM: mvebu: Armada XP GP specific suspend/resume code")
2015-06-17 17:23:36 +02:00
Paul Gortmaker ff6138ad19 arm/mach-mvebu: remove legacy __cpuinit sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time
ago.  However these ones crept back in as of commit 1ee89e2231
("ARM: mvebu: add SMP support for Armada 375 and Armada 38x")

Since we want to clobber the stubs soon, get this removed now.
Note that there would normally be a corresponding removal of
a ".previous" directive for each __CPUINIT in asm files, but in
this case it appears that this single function file was never
paired off with one.

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:21 -04:00
Russell King 02b4e2756e ARM: v7 setup function should invalidate L1 cache
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-01 11:30:26 +01:00
Linus Torvalds e6c81cce56 ARM: SoC platform updates for v4.1
Our SoC branch usually contains expanded support for new SoCs and other core
 platform code. In this case, that includes:
 
 - Support for the new Annapurna Labs "Alpine" platform
 - A rework greatly simplifying adding new platform support to the MCPM
   subsystem (Multi-cluster power management)
 - Cpuidle and PM improvements for Exynos3250
 - Misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have
   gone in other branches but ended up here for various reasons.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVNzfWAAoJEIwa5zzehBx3idcP/Rt042tqb0bian/4M1Ud1aQ7
 AMRd4oU5MfWAlzaGPeMBS+b1eo/eENj6wyWsvBQIByZN76ImlUXtxsx0U0frLrVg
 mWVo9zOLRuoE6yyq329zZgg1IM1RtRIruS6zucKsHgKtq0DcjhYGGUH0ZVZk/rKI
 RLtRK8U6Jr0lnpu1TDE5mii7GCCZlEl5dG+J3w5ewC9y7RLRlM09xjK/Zsj0QOqY
 JvMOIaHuHMT6l7BQ6QajtVxTeGECOJ3YDqC6mDHCVD7f3v88+7H5C20xNGPK921w
 tLfB5qOojnj+kKZRPhi8EGnRzKwrBq6/mE5CvvigTCGlAEUOzy7PFSY9oNE80QeL
 6mUdPTuZuqz7ZEIF0kj8I0AkB6k8B+aYfqA9mqM5yGpa11HvZZGfP7CwI4izoe6+
 sT++0OeDPwbsMyRxZjqNQLs4QYaKGYMP4NCgA17zz5ToRCQZy7e5hd2GYzaRouyi
 kTpR9FbxwDcBIwTcA3F7oJ90BEMJ0tvGz/Al11UQpzPePhTwQt2yB5bRZyK/RYIU
 x8k8RHArG3fmS89D4aOViL3sy/zoUBedx4UfAo6jVbrvoZGALQL23KHdqBqDiPmP
 sMRj/sSr+0h9nJCVNM6I/OUD4/IrpFGaeX9V7rpEsHVe7j83eV7Q2wNRPyVTgxdn
 jS8TS0FNAXIv8FO9EoNH
 =tcGs
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Olof Johansson:
 "Our SoC branch usually contains expanded support for new SoCs and
  other core platform code.  In this case, that includes:

   - support for the new Annapurna Labs "Alpine" platform

   - a rework greatly simplifying adding new platform support to the
     MCPM subsystem (Multi-cluster power management)

   - cpuidle and PM improvements for Exynos3250

   - misc updates for Renesas, OMAP, Meson, i.MX.  Some of these could
     have gone in other branches but ended up here for various reasons"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
  ARM: alpine: add support for generic pci
  ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction
  ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction
  ARM: vexpress: DCSCB: tighten CPU validity assertion
  ARM: vexpress: migrate TC2 to the new MCPM backend abstraction
  ARM: MCPM: move the algorithmic complexity to the core code
  ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC
  ARM: EXYNOS: add AFTR mode support for Exynos3250
  ARM: EXYNOS: add code for setting/clearing boot flag
  ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
  ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore
  ARM: cygnus: fix const declaration bcm_cygnus_dt_compat
  ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
  ARM: DRA7: hwmod: Add data for GPTimers 13 through 16
  ARM: EXYNOS: Remove left over 'extra_save'
  ARM: EXYNOS: Constify exynos_pm_data array
  ARM: EXYNOS: use static in suspend.c
  ARM: EXYNOS: Use platform device name as power domain name
  ARM: EXYNOS: add support for async-bridge clocks for pm_domains
  ARM: omap-device: add missed callback for suspend-to-disk
  ...
2015-04-22 09:08:39 -07:00
Linus Torvalds d0440c59f5 ARM: SoC cleanups for v4.1
We've got a fairly large cleanup branch this time. The bulk of this is removal
 of non-DT platforms of several flavors:
 
 - Atmel at91 platforms go full-DT, with removal of remaining board-file based
   support
 - OMAP removes legacy board files for three more platforms
 - Removal of non-DT mach-msm, newer Qualcomm platforms now live in mach-qcom
 - Freescale i.MX25 also removes non-DT platform support
 
 Most of the rest of the changes here are fallout from the above, i.e. for
 example removal of drivers that now lack platforms, etc.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVNzI3AAoJEIwa5zzehBx3ePwQAJKb4Mf72/4iiKb4dbVcooQN
 EiZ84fwWiWD6Mww/3A76xVnz/b7JWmB3vwW0b4fcbvzubmOjnROBmZgCWeNy4ZTv
 dOZc3/9jK7OrlwvpFBeZykQwHcbz+550+m3WxmLft1oqH/7BA1k5aunwYtFB96ii
 5Owi4Cy9OmxEyALQAvzktFaJdI7J66LNb+i30r5zIZHlkVooeF3UyadndiswUP2o
 EBzCE8UPqRi5kV6FuwVyf4MZaV28FWoglTqdx9OxogcTnKNFT6RlHQ39q/iPu348
 Wkh4kOryVy7Rlab1K4wQRpBoOwkonKDV73u2H2ifRFj7V9ZAdjibK8pgKn3kjkba
 bJkwHIqlqtqqqjj2Hh93wl+8hKSypoLXO9tagPWYBiLtFXCH/+EVsihWYpAc/A5E
 pUS6hJrJyXKJouwwsXu6459zP0ieqhvpbQG72xs9PRimAfAdSTulSTzdI/dMh42Q
 pwYkmvh+ReY3Ll4MeCzu7+eCIY0qAKsor48W1ImuziwQhg2lZj16qWtA4YdPk3+O
 N8ckyaaFg663PAfsZgBx1qTgxw5v0ec2k68/iEVGS5mUJCgcWxFvR95chTDIxQXq
 ZmJ+SuMFyLB/2zVSiGU96L1PQTcUkxJJ8LVB3qNp6KlYT7qUSsgAU+qYveFlUh+p
 X8MVsSVh8n1MTNepsLij
 =BV8A
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "We've got a fairly large cleanup branch this time.  The bulk of this
  is removal of non-DT platforms of several flavors:

   - Atmel at91 platforms go full-DT, with removal of remaining
     board-file based support

   - OMAP removes legacy board files for three more platforms

   - removal of non-DT mach-msm, newer Qualcomm platforms now live in
     mach-qcom

   - Freescale i.MX25 also removes non-DT platform support"

Most of the rest of the changes here are fallout from the above, i.e. for
example removal of drivers that now lack platforms, etc.

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (58 commits)
  mmc: Remove msm_sdcc driver
  gpio: Remove gpio-msm-v1 driver
  ARM: Remove mach-msm and associated ARM architecture code
  ARM: shmobile: cpuidle: Remove the pointless default driver
  ARM: davinci: dm646x: Add interrupt resource for McASPs
  ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
  ARM: davinci: dm646x: Clean up the McASP DMA resources
  ARM: davinci: devices-da8xx: Add support for McASP2 on da830
  ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation
  ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs
  ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request
  ARM: OMAP2+: Remove legacy support for omap3 TouchBook
  ARM: OMAP3: Remove legacy support for devkit8000
  ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board
  ARM: shmobile: Consolidate the pm code for R-Car Gen2
  ARM: shmobile: r8a7791: Correct SYSCIER value
  ARM: shmobile: r8a7790: Correct SYSCIER value
  ARM: at91: remove old setup
  ARM: at91: sama5d4: remove useless map_io
  ARM: at91: sama5 use SoC detection infrastructure
  ...
2015-04-22 09:04:39 -07:00
Gregory CLEMENT 548ae94c1c ARM: mvebu: Disable CPU Idle on Armada 38x
On Armada 38x SoCs, under heavy I/O load, the system hangs when CPU
Idle is enabled. Waiting for a solution to this issue, this patch
disables the CPU Idle support for this SoC.

As CPU Hot plug support also uses some of the CPU Idle functions it is
also affected by the same issue. This patch disables it also for the
Armada 38x SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.17 +
2015-03-31 18:47:33 +02:00
Thomas Petazzoni 242ede0bdd ARM: mvebu: add core support for Armada 39x
This commit adds the core support for Armada 39x, which is quite
simple:

 - a new Kconfig option which selects the appropriate clock and
   pinctrl drivers as well as other common features (GIC, L2 cache,
   SMP, etc.)

 - a new DT_MACHINE_START which references the top-level compatible
   strings supported for the Marvell Armada 39x.

 - a new SMP enable-method. The mechanism to enable CPUs for Armada
   39x appears to be the same as Armada 38x. However, we do not want
   to use marvell,armada-380-smp in the Device Tree, in the case of
   the discovery of a subtle difference in the future, which would
   require changing the Device Tree. And the enable-method isn't a
   compatible string: you can't specify several values and expect a
   fallback on the second string if the first one isn't
   supported. Therefore, we simply declare the SMP enable method
   "marvell,armada-390-smp" as doing the same thing as the
   "marvell,armada-380-smp" one.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-03-04 15:35:38 +01:00
Thomas Petazzoni bc2d7a58b9 ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables
As suggested by Stephen Boyd, this commit adds the __initconst
specifier to the dt_compat table declarations used by the
DT_MACHINE_START structures in mach-mvebu land.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-03-04 14:56:21 +01:00
Uwe Kleine-König 444d2d33d8 ARM: make of_device_ids const
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by <linux/of.h> work with const of_device_ids. So mark the
non-const structs in arch/arm as const, too.

While at it also add some __initconst annotations.

Acked-by: Jason Cooper <jason@lakedameon.net>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-02-19 09:44:25 +01:00
Arnd Bergmann 165235180f ARM: mvebu: build armada375-smp code conditionally
mvebu_armada375_smp_wa_init is only used on armada 375 but is defined
for all mvebu machines. As it calls a function that is only provided
sometimes, this can result in a link error:

arch/arm/mach-mvebu/built-in.o: In function `mvebu_armada375_smp_wa_init':
:(.text+0x228): undefined reference to `mvebu_setup_boot_addr_wa'

To solve this, we can just change the existing #ifdef around the
function to also check for Armada375 SMP platforms.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 305969fb62 ("ARM: mvebu: use the common function for Armada 375 SMP workaround")
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
2015-02-18 12:20:29 +01:00
Linus Torvalds 878ba61aa9 ARM: SoC platform changes
New and updated SoC support. Also included are some cleanups where the
 platform maintainers hadn't separated cleanups from new developent in
 separate branches.
 
 Some of the larger things worth pointing out:
 
 - A large set of changes from Alexandre Belloni and Nicolas Ferre
   preparing at91 platforms for multiplatform and cleaning up quite a
   bit in the process.
 - Removal of CSR's "Marco" SoC platform that never made it out to the
   market. We love seeing these since it means the vendor published
   support before product was out, which is exactly what we want!
 
 New platforms this release are:
 
 - Conexant Digicolor (CX92755 SoC)
 - Hisilicon HiP01 SoC
 - CSR/sirf Atlas7 SoC
 - ST STiH418 SoC
 - Common code changes for Nvidia Tegra132 (64-bit SoC)
 
 We're seeing more and more platforms having a harder time labelling
 changes as cleanups vs new development -- which is a good sign that
 we've come quite far on the cleanup effort. So over time we might start
 combining the cleanup and new-development branches more.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4uiiAAoJEIwa5zzehBx3LtoQAIP4eInJAumhB67MexzWGIBx
 eOsloBRMEBrjBQdSYsdsypN6T61WjDu1aieCxEGzIqitcMa59AIyyzglmlXy3UmV
 XQuSnIBag2fsOqrvqd+c6ewzAMxm2/Nbi3+zjzApkf27NDlBLhEjxuK6pAAf4Yw9
 gyWqB9g0d4V06XdqRInRvyyVfMu6fdApHLnadtjcMdiorQGd1bcOE1sQYygy6N6e
 d6vGvyKSv4ygyDG9//njzm6C5OnmHliimMToeuDC2Scel69RM97EnMXys988CqUH
 0Ru7XANEujtHXSOBYOyCv1kk4V5NguGzlfepe23oidOew8MjUdyRvKrwUiMt3AnT
 SVqcZ9UU5wjJC6j+iADh+E7zww2H0rA6vFRzXy297dDuLg2C2ONFljBj/tIKGc71
 ++gLc6LRn7UmSyK98JMzkxDhmnnPn8w2O0M5GdabAqzZSfHlL1juW9ljp9Al5P6y
 apLRzqMGjEoyC4huXvB3XVfrxGfepe5pco6wVlwmF3ilwf7iHnfuHONC1aw2mPRO
 aOKiS+0gHWL3rNZtZQtyW7Ws0I2HJFip2CWIloBK1/2ntEoh51PH7jGw8iu/6jTk
 //DCXqPBNXcLqonB9CHJZ/EWt0wup0BcHyLjlWX7iEjsdP/QJXrDgnrV3qdHibbh
 AJASjs0YVDcdvRsRStlg
 =szd9
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New and updated SoC support.  Also included are some cleanups where
  the platform maintainers hadn't separated cleanups from new developent
  in separate branches.

  Some of the larger things worth pointing out:

   - A large set of changes from Alexandre Belloni and Nicolas Ferre
     preparing at91 platforms for multiplatform and cleaning up quite a
     bit in the process.

   - Removal of CSR's "Marco" SoC platform that never made it out to the
     market.  We love seeing these since it means the vendor published
     support before product was out, which is exactly what we want!

  New platforms this release are:

   - Conexant Digicolor (CX92755 SoC)
   - Hisilicon HiP01 SoC
   - CSR/sirf Atlas7 SoC
   - ST STiH418 SoC
   - Common code changes for Nvidia Tegra132 (64-bit SoC)

  We're seeing more and more platforms having a harder time labelling
  changes as cleanups vs new development -- which is a good sign that
  we've come quite far on the cleanup effort.  So over time we might
  start combining the cleanup and new-development branches more"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
  ARM: at91/trivial: unify functions and machine names
  ARM: at91: remove at91_dt_initialize and machine init_early()
  ARM: at91: change board files into SoC files
  ARM: at91: remove at91_boot_soc
  ARM: at91: move alternative initial mapping to board-dt-sama5.c
  ARM: at91: merge all SOC_AT91SAM9xxx
  ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
  ARM: digicolor: select syscon and timer
  ARM: zynq: Simplify SLCR initialization
  ARM: zynq: PM: Fixed simple typo.
  ARM: zynq: Setup default gpio number for Xilinx Zynq
  ARM: digicolor: add low level debug support
  ARM: initial support for Conexant Digicolor CX92755 SoC
  ARM: OMAP2+: Add dm816x hwmod support
  ARM: OMAP2+: Add clock domain support for dm816x
  ARM: OMAP2+: Add board-generic.c entry for ti81xx
  ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
  ARM: at91: remove unused mach/system_rev.h
  ARM: at91: stop using HAVE_AT91_DBGUx
  ARM: at91: fix ordering of SRAM and PM initialization
  ...
2015-02-17 09:27:54 -08:00
Thomas Petazzoni dcad68876c ARM: mvebu: don't set the PL310 in I/O coherency mode when I/O coherency is disabled
Since commit f2c3c67f00 (merge commit that adds commit "ARM: mvebu:
completely disable hardware I/O coherency"), we disable I/O coherency
on Armada EBU platforms.

However, we continue to initialize the coherency fabric, because this
coherency fabric is needed on Armada XP for inter-CPU
coherency. Unfortunately, due to this, we also continued to execute
the coherency fabric initialization code for Armada 375/38x, which
switched the PL310 into I/O coherent mode. This has the effect of
disabling the outer cache sync operation: this is needed when I/O
coherency is enabled to work around a PCIe/L2 deadlock. But obviously,
when I/O coherency is disabled, having the outer cache sync operation
is crucial.

Therefore, this commit fixes the armada_375_380_coherency_init() so
that the PL310 is switched to I/O coherent mode only if I/O coherency
is enabled.

Without this fix, all devices using DMA are broken on Armada 375/38x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.8+
2015-01-28 11:23:56 -06:00
Thomas Petazzoni 1bd4d8a6de ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O coherency
Now that we have enabled automatic I/O synchronization barriers, we no
longer need any explicit barriers. We can therefore simplify
arch/arm/mach-mvebu/coherency.c by using the existing
arm_coherent_dma_ops instead of our custom mvebu_hwcc_dma_ops, and
re-enable hardware I/O coherency support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
[Andrew Lunn <andrew@lunn.ch>: Remove forgotten comment]
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2015-01-19 16:05:57 -06:00
Andrew Lunn fe6e91e338 Merge branch 'mvebu/fixes-3' into mvebu/soc 2015-01-19 16:00:15 -06:00
Thomas Petazzoni 8f1e8ee286 ARM: mvebu: completely disable hardware I/O coherency
The current hardware I/O coherency is known to cause problems with DMA
coherent buffers, as it still requires explicit I/O synchronization
barriers, which is not compatible with the semantics expected by the
Linux DMA coherent buffers API.

So, in order to have enough time to validate a new solution based on
automatic I/O synchronization barriers, this commit disables hardware
I/O coherency entirely. Future patches will re-enable it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2015-01-17 11:46:55 -06:00
Gregory CLEMENT c657454214 ARM: mvebu: Update the SoC ID and revision definitions
Add the missing SoC and revision ID for the Armada 370 and 38x SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2015-01-09 09:22:53 -06:00
Thomas Petazzoni 842f7d2c4d ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
This commit adjusts the registration of the cpufreq-dt driver in the
mvebu platform to indicate to the cpufreq driver that the platform has
independent clocks for each CPU.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-12-04 17:31:32 +01:00
Arnd Bergmann ab64920c37 mvebu SoC suspend changes for v3.19
- Armada 370/XP suspend/resume support
 
  - mvebu SoC driver suspend/resume support
     - irqchip
     - clocksource
     - mbus
     - clk
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJUe0lIAAoJEP45WPkGe8Zn/IgP/jOO8c7t7dohRbAe3axzIcaC
 DLL7d7j0AScZGXLx1/xJrFFY/P3gn3dlLR7HnT0t4K7vcW0kP4orMGo6FcGicSOZ
 VzQf88cOkunKf9NTM1Y0LOXVWTHGuACiXAnxook5A6k+l0xQ1t+uewgEKrg/33VK
 6WQ6woe2eYFwghkFwL3ybjttOPM5nxPef6v3TZ3LfwSUBsnSm70F1XiO8xZJH+LM
 fL83P409LGWgohwSaXYRdPJcNM0U7QMNo6i/If9NNBhIkdKb6llhQ/DvI+aXUvqB
 aD9/4t+Q75yki0mXIin6irltjspWsR8OFbaKZOM5IBFp/XrsKvNU+wy++7z9se9z
 qfG1QYmKk3ddI0isoksuIJpfbrlbQqFKCGlNkn8HVi4xCYCijNgb5bUrHQ27Aa4U
 GGisAOhqs9Ktpz96WeNKjvNQBSJZ3ESd6tlLrwCei8DwEdT0Z73jr1aEnulurpPG
 A3kiUhVpRIU+w0cth5Kix2bZj7JGsykzu1x5xORLE+MN8RSgmoveGyY5CBp2MHrl
 NxR/u98SD9I/rWT3DwQIKxM5ZqF4AAnyj4SaSWR/f40kWMU+A+eMEfo8VUeO88fl
 ygeeHTghSf58gbdgganRfDyY8OaQHeYNNKbWK6c7vxyMX98vwHOtOb5JS3nn0p7q
 Fugy/6qf+ZqYHT4nczJO
 =uX+e
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc

Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:

 - Armada 370/XP suspend/resume support

 - mvebu SoC driver suspend/resume support
    - irqchip
    - clocksource
    - mbus
    - clk

* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-12-04 16:46:43 +01:00
Thomas Petazzoni b9b1de0f4d ARM: mvebu: synchronize secondary CPU clocks on resume
The Armada XP has multiple cores clocked by independent clocks. The
SMP startup code contains a function called set_secondary_cpus_clock()
called in armada_xp_smp_prepare_cpus() to ensure the clocks of the
secondary CPUs match the clock of the boot CPU.

With the introduction of suspend/resume, this operation is no longer
needed when booting the system, but also when existing the suspend to
RAM state. Therefore this commit reworks a bit the logic: instead of
configuring the clock of all secondary CPUs in
armada_xp_smp_prepare_cpus(), we do it on a per-secondary CPU basis in
armada_xp_boot_secondary(), as this function gets called when existing
suspend to RAM for each secondary CPU.

Since the function now only takes care of one CPU, we rename it from
set_secondary_cpus_clock() to set_secondary_cpu_clock(), and it looses
its __init marker, as it is now used beyond the system initialization.

Note that we can't use smp_processor_id() directly, because when
exiting from suspend to RAM, the code is apparently executed with
preemption enabled, so smp_processor_id() is not happy (prints a
warning). We therefore switch to using get_cpu()/put_cpu(), even
though we pretty much have the guarantee that the code starting the
secondary CPUs is going to run on the boot CPU and will not be
migrated.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-14-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:16 +00:00
Thomas Petazzoni 77ea46d133 ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
The armada_370_xp_cpu_resume() until now was used only as the function
called by the SoC when returning from a deep idle state (as used in
cpuidle, or when the CPU is brought offline using CPU hotplug).

However, it is now also used when exiting the suspend to RAM state. In
this case, it is the bootloader that calls back into this function,
with the MMU left enabled by the BootROM. Having the MMU enabled when
entering this function confuses the kerrnel because we are not using
the kernel page tables at this point, but in other mvebu functions we
use the information on whether the MMU is enabled or not to find out
whether we should talk to the coherency fabric using a physical
address or a virtual address. To fix that, we simply disable the MMU
when entering this function, so that the kernel is in an expected
situation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-13-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:15 +00:00
Thomas Petazzoni 27432825ae ARM: mvebu: Armada XP GP specific suspend/resume code
On the Armada XP GP platform, entering suspend to RAM state is
triggering by talking to an external PIC micro-controller connected to
the SoC using 3 GPIOs. There is then a small magic sequence of GPIO
toggling that needs to be used to tell the PIC to turn off the SoC.

The code uses the Device Tree to find out which GPIOs are used to
connect to the PIC micro-controller, and then registers its
mvebu_armada_xp_gp_pm_enter() callback to the SoC-level PM code. The
SoC PM code will call back into this registered function at the very
end of the suspend procedure.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-12-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:14 +00:00
Thomas Petazzoni 8da2b2f7ce ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
When going out of suspend to RAM, the Marvell EBU platforms go through
the bootloader, which re-configures the DRAM controller. To achieve
this, the bootloader executes a piece of code called the "DDR3
training code". It does some reads/writes to the memory to find out
the optimal timings for the memory chip being used.

This has the nasty side effect that the first 10 KB of each DRAM
chip-select are overwritten by the bootloader when exiting the suspend
to RAM state.

Therefore, this commit implements the ->reserve() hook for the 'struct
machine_desc' used on Armada XP, to reserve the 10 KB of each DRAM
chip-select using the memblock API.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:13 +00:00
Thomas Petazzoni 8446be5d03 ARM: mvebu: implement suspend/resume support for Armada XP
This commit implements the core of the platform code to enable
suspend/resume on Armada XP. It registers the platform_suspend_ops
structure, and implements the ->enter() hook of this structure.

It is worth mentioning that this commit only provides the SoC-level
part of suspend/resume, which calls into some board-specific code
provided in a follow-up commit.

The most important thing that this SoC-level code has to do is to
build an in-memory structure that contains a magic number, the return
address in the kernel after resume, and a set of address/value
pairs. This structure is used by the bootloader to restore a certain
number of registers (according to the set of address/value pairs) and
then jump back into the kernel at the provided location.

The code also puts the SDRAM into self-refresh mode, before calling
into board-specific code to actually enter the suspend to RAM state.

[ jac - add email exchange between Andrew Lunn and Thomas Petazzoni to better
describe who consumes the address/value pairs ]

> > Is this a well defined mechanism supported by mainline uboot, barebox
> > etc. Or is it some Marvell extension to their uboot?
>
> As far as I know, it is a Marvell extension to their "binary header",
> so it's done even before U-Boot starts. Since the hardware needs
> assistance from the bootloader to do suspend/resume, there is
> necessarily a certain amount of cooperation/agreement needed by what
> the kernel does and what the bootloader expects. I'm not sure there's
> any "standard" mechanism here. Do you know of any?
>
> I know the suspend/resume on the Blackfin architecture works the same
> way (at least it used to work that way years ago when I did a bit of
> Blackfin stuff). And here as well, there was some cooperation between
> the kernel and the bootloader. See
> arch/blackfin/mach-common/dpmc_modes.S, function do_hibernate() at the
> end.
>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:12 +00:00
Gregory CLEMENT 626d686487 ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs
This commit implements the CPU hotplug support for the Marvell Armada
38x platform. Similarly to what was done for the Armada XP, this
commit:

 * Implements the ->cpu_die() function of SMP operations by calling
   armada_38x_do_cpu_suspend() to enter the deep idle state for
   CPUs going offline.

 * Implements a dummy ->cpu_kill() function, simply needed for the
   kernel to know we have CPU hotplug support.

 * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up
   the CPU if waiting in deep idle state by sending an IPI before
   deasserting the CPUs from reset. This is because
   mvebu_cortex_a9_boot_secondary() is now used in two different
   situations: for the initial boot of secondary CPUs (where CPU reset
   deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
   is used to take CPU out of deep idle).

 * At boot time, we exit from the idle state in the
    ->smp_secondary_init() hook.

This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:38 +00:00
Gregory CLEMENT f5789cbb22 ARM: mvebu: Fix the secondary startup for Cortex A9 SoC
During the secondary startup the SCU was assumed to be in normal
mode. It is not always the case, and especially after a kexec. This
commit adds the needed sequence to put the SCU in normal mode.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-4-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:20 +00:00
Gregory CLEMENT f746ac327b ARM: mvebu: Move SCU power up in a function
This will allow reusing the same function in the secondary_startup
for the Cortex A9 SoC.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:08 +00:00
Gregory CLEMENT 316fbbc400 ARM: mvebu: Clean-up the Armada XP support
This patch removes the unneeded include of the armada-370-xp.h header.

It also moves some declarations from this file into more accurate
places.

Finally, it also adds a comment explaining that we can't remove yet the
smp field in the dt machine struct due to backward compatibly of the
device tree.

In a few releases, when the old device tree will be obsolete, we will be
able to remove the smp field and then the armada-370-xp.h header.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:13:24 +00:00
Thomas Petazzoni e12f12ac1a ARM: mvebu: update comments in coherency.c
The coherency.c top-level comment mentions that it supports the
coherency fabric for Armada 370 and XP, but it also supports the
coherency fabric on Armada 375 and 38x, so this commit updates the
comment accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:42 +00:00
Thomas Petazzoni ef01c6c36b ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency
This reverts commit 5ab5afd8ba ("ARM: mvebu: implement Armada 375
coherency workaround"), since we are removing the support for the very
early Z1 revision of the Armada 375 SoC.

This commit is an exact revert, with two exceptions:

 - minor adaptations needed due to other changes that have taken place
   in coherency.c since the original commit

 - keep the definition of pr_fmt. This shouldn't originally have been
   part of the Armada 375 Z1 workaround commit since it had nothing to
   do with it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:37 +00:00
Thomas Petazzoni 3b8509b5f2 ARM: mvebu: remove unused register offset definition
Since commit b21dcafea3 ("arm: mvebu: remove dependency of SMP init
on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register
offset definition is no longer used, so this commit removes it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:35 +00:00
Thomas Petazzoni e553554536 ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada
38x and Armada XP requires a certain number of conditions:

 - On Armada 370, the cache policy must be set to write-allocate.

 - On Armada 375, 38x and XP, the cache policy must be set to
   write-allocate, the pages must be mapped with the shareable
   attribute, and the SMP bit must be set

Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions
are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none
of these conditions are met. With Armada 370, the situation is worse:
since the processor is single core, regardless of whether CONFIG_SMP
or !CONFIG_SMP is used, the cache policy will be set to write-back by
the kernel and not write-allocate.

Since solving this problem turns out to be quite complicated, and we
don't want to let users with a mainline kernel known to have
infrequent but existing data corruptions, this commit proposes to
simply disable hardware I/O coherency in situations where it is known
not to work.

And basically, the is_smp() function of the kernel tells us whether it
is OK to enable hardware I/O coherency or not, so this commit slightly
refactors the coherency_type() function to return
COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate
type of the coherency fabric in the other case.

Thanks to this, the I/O coherency fabric will no longer be used at all
in !CONFIG_SMP configurations. It will continue to be used in
CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x
(which are multiple cores processors), but will no longer be used on
Armada 370 (which is a single core processor).

In the process, it simplifies the implementation of the
coherency_type() function, and adds a missing call to of_node_put().

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fixes: e60304f8cb ("arm: mvebu: Add hardware I/O Coherency support")
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:33 +00:00
Thomas Petazzoni 30cdef9710 ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and
ll_disable_coherency() are used on Armada XP to control the coherency
fabric. However, they make the assumption that the coherency fabric is
always available, which is currently a correct assumption but will no
longer be true with a followup commit that disables the usage of the
coherency fabric when the conditions are not met to use it.

Therefore, this commit modifies those functions so that they check the
return value of ll_get_coherency_base(), and if the return value is 0,
they simply return without configuring anything in the coherency
fabric.

The ll_get_coherency_base() function is also modified to properly
return 0 when the function is called with the MMU disabled. In this
case, it normally returns the physical address of the coherency
fabric, but we now check if the virtual address is 0, and if that's
case, return a physical address of 0 to indicate that the coherency
fabric is not enabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:27 +00:00
Jason Cooper 93a93d19c7 Merge branch 'mvebu/fixes' into mvebu/soc 2014-11-22 01:48:20 +00:00
Ezequiel Garcia 172ed82cef ARM: mvebu: Remove thermal quirk for A375 Z1 revision
The Armada 375 Z1 SoC revision is no longer supported. This commit
removes the quirk required to "fix" the reg property and the compatible
string of the thermal devicetree node.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1415116839-4323-3-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-09 03:19:39 +00:00
Thomas Petazzoni 2eb04ae010 ARM: mvebu: add missing of_node_put() call in coherency.c
There is a missing of_node_put() to decrement the device_node
reference counter after a of_find_matching_node() in coherency_init().

Fixes: 501f928e00 ("ARM: mvebu: add a coherency_available() call")
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1414423955-5933-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-07 02:56:36 +00:00
Andrew Lunn 5129ee22ce ARM: mvebu: armada xp: Generalize use of i2c quirk
A second product has come to light which makes use of the A0 stepping
of the Armada XP SoC. A0 stepping has a hardware bug in the i2c core
meaning that hardware offload does not work, resulting in the kernel
failing to boot. The quirk detects that the kernel is running on an A0
stepping SoC and disables the use of hardware offload.

Currently the quirk is only enabled for PlatHome Openblocks AX3. The
AX3 has been produced with both A0 and B0 stepping SoCs. The second
product is the Lenovo Iomega IX4-300d. It seems likely that this
device will also swap from A0 to B0 SoC sometime during its life.

If there are two products using A0, it seems likely there are more
products with A0. Also, since the number of A0 SoCs is limited, these
products are also likely to transition to B0. Hence detecting at run
time is the safest option. So enable the quirk for all Armada XP
boards.

Tested on an AX3 with A0 stepping.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: stable@vger.kernel.org # v3.12+
Fixes: 930ab3d403ae: ("i2c: mv64xxx: Add I2C Transaction Generator support")
Link: https://lkml.kernel.org/r/1406395238-29758-2-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-01 22:07:44 +00:00
Viresh Kumar bbcf071969 cpufreq: cpu0: rename driver and internals to 'cpufreq_dt'
The naming convention of this driver was always under the scanner, people
complained that it should have a more generic name than cpu0, as it manages all
CPUs that are sharing clock lines.

Also, in future it will be modified to support any number of clusters with
separate clock/voltage lines.

Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-10-03 15:37:54 +02:00
Linus Torvalds b3345d7c57 ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5Dp+AAoJEIwa5zzehBx3w1sP/0vjT/LQOmC8Lv8RW2Ley2ua
 hNu3HcNPnT/N40JEdU9YNv3q0fdxGgcfKj011CNN+49zPSUf1xduk2wfCAk9yV50
 8Sbt1PfDGm1YyUugGN420CzI431pPoM1OGXHZHkAmg+2J286RtUi3NckB//QDbCY
 QhEjhpYc9SXhAOCGwmB4ab7thOljOFSPzKTLMTu3+PNI5zRPRgkDkt6w9XlsAYmB
 nuR271BnzsROkMzAjycwaJ3kdim7wqrMRfk8g96o0jHSF5qf4zsT5uWYYAjTxdUQ
 8Ajz6zjeHe4+95TwTDcq+lCX6rDLZgwkvCAc6hFbeg0uR7Dyek0h6XMEYtwdjaiU
 KNPwOENrYdENNDAGRpkFp1x4h/rY9Plfru0bBo5o6t7aPBvmNeCDzRtlTtLiUNDV
 dG8sfDMtrS/wFHVjylDSQ60Mb+wuW0XneC8D7chY/iRhIllUYi6YXXvt+/tH5C20
 oYDOWqqcDFSb0sJhE5pn4KBV82ZaHx9jMBWGLl+erg2sDX/SK8SxOkLqKYZKtKB5
 0leOGE3Y+C70xt3G9HftLz2sAvvt+C8UPsApPT+dHNE401TWJOYx6LphPkQKjeeK
 P1iwKi+It3l+FaBypgJy/LeMQRy7EyvDBK2I5WoVL/R2qq14EmP1ui3Tthjj0bhq
 tBBof6P9c8OnRVj1Lz3R
 =5TJ6
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
2014-08-08 11:14:29 -07:00
Linus Torvalds c489d98c8c Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
 "Included in this update:

   - perf updates from Will Deacon:

     The main changes are callchain stability fixes from Jean Pihet and
     event mapping and PMU name rework from Mark Rutland

     The latter is preparatory work for enabling some code re-use with
     arm64 in the future.

   - updates for nommu from Uwe Kleine-König:

     Two different fixes for the same problem making some ARM nommu
     configurations not boot since 3.6-rc1.  The problem is that
     user_addr_max returned the biggest available RAM address which
     makes some copy_from_user variants fail to read from XIP memory.

   - deprecate legacy OMAP DMA API, in preparation for it's removal.

     The popular drivers have been converted over, leaving a very small
     number of rarely used drivers, which hopefully can be converted
     during the next cycle with a bit more visibility (and hopefully
     people popping out of the woodwork to help test)

   - more tweaks for BE systems, particularly with the kernel image
     format.  In connection with this, I've cleaned up the way we
     generate the linker script for the decompressor.

   - removal of hard-coded assumptions of the kernel stack size, making
     everywhere depend on the value of THREAD_SIZE_ORDER.

   - MCPM updates from Nicolas Pitre.

   - Make it easier for proper CPU part number checks (which should
     always include the vendor field).

   - Assembly code optimisation - use the "bx" instruction when
     returning from a function on ARMv6+ rather than "mov pc, reg".

   - Save the last kernel misaligned fault location and report it via
     the procfs alignment file.

   - Clean up the way we create the initial stack frame, which is a
     repeated pattern in several different locations.

   - Support for 8-byte get_user(), needed for some DRM implementations.

   - mcs locking from Will Deacon.

   - Save and restore a few more Cortex-A9 registers (for errata
     workarounds)

   - Fix various aspects of the SWP emulation, and the ELF hwcap for the
     SWP instruction.

   - Update LPAE logic for pte_write and pmd_write to make it more
     correct.

   - Support for Broadcom Brahma15 CPU cores.

   - ARM assembly crypto updates from Ard Biesheuvel"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (53 commits)
  ARM: add comments to the early page table remap code
  ARM: 8122/1: smp_scu: enable SCU standby support
  ARM: 8121/1: smp_scu: use macro for SCU enable bit
  ARM: 8120/1: crypto: sha512: add ARM NEON implementation
  ARM: 8119/1: crypto: sha1: add ARM NEON implementation
  ARM: 8118/1: crypto: sha1/make use of common SHA-1 structures
  ARM: 8113/1: remove remaining definitions of PLAT_PHYS_OFFSET from <mach/memory.h>
  ARM: 8111/1: Enable erratum 798181 for Broadcom Brahma-B15
  ARM: 8110/1: do CPU-specific init for Broadcom Brahma15 cores
  ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAE
  ARM: 8108/1: mm: Introduce {pte,pmd}_isset and {pte,pmd}_isclear
  ARM: hwcap: disable HWCAP_SWP if the CPU advertises it has exclusives
  ARM: SWP emulation: only initialise on ARMv7 CPUs
  ARM: SWP emulation: always enable when SMP is enabled
  ARM: 8103/1: save/restore Cortex-A9 CP15 registers on suspend/resume
  ARM: 8098/1: mcs lock: implement wfe-based polling for MCS locking
  ARM: 8091/2: add get_user() support for 8 byte types
  ARM: 8097/1: unistd.h: relocate comments back to place
  ARM: 8096/1: Describe required sort order for textofs-y (TEXT_OFFSET)
  ARM: 8090/1: add revision info for PL310 errata 588369 and 727915
  ...
2014-08-05 10:05:29 -07:00
Arnd Bergmann 39fbf98408 mvebu SoC changes for v3.17 (round 4)
- Armada XP
     - Fix return value check in pmsu code
     - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)
 
  - Armada 370/38x
     - Add cpuidle support
 
  - mvebu
     - Fix build when no platforms are selected
     - Update EBU SoC status in docs
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJT0kjkAAoJEP45WPkGe8ZnqpsQALFvbZKqBmvm+dj4G/dB9YYg
 ihJM1FasU5yrHWhQlUSJw3Lntf/WwK2Qbrq3NmeCNo9qxx5r3IOv8inLah+XsXWv
 C4RyiqmbnbiUg24QwHHGHLnRZuKCZdciiCyVmDO5DxRiT7Ov7EffOiiEws1WIUU1
 6os30LEp82UpfcUkevJi12AkQvgTcX8tQXN2Kc7TgbxzJcyOt9M03BUej9gDdqD3
 XfeBZv/WTapZllifRF04zsVJUtPKx48BmR0KdInYlsRfjg7knbYb1qkC7iysPJvv
 G2XPWYOTVC7bbY+ZRfDcreowcTbBxXNiVbtPMM0+5kfli76/thPFutlA9/hi5plR
 WeGa6V+M61RMdOexg9C/lVIpdqXLpI1xINlRv4vyjalm28JgvzAoucaaFnY6Rdxt
 ApDIbhHzYCWyHwMn9DXi5s2nhMFL7i7JXCL/iDySzZB+ZNSKd+ULn1AhTOnOjFSL
 jU7S9htD8tNZ7MuTX1Jg6gsuGxH1yr8x6kUX99DymUiYlKT7XbrXPa3Xf9vS8dx+
 j0y7J6aJET7dlReH3tScehKOjnt44Djwgb9HiEilMNNYCWUQkKwxZCxnDQ6xNFCV
 COXfu+nx87yVbBhSlJH+m0hQbf3jBmx/vuKnjYLRrZ/ATeWv/uWd78G2tZV7ercU
 AiXn0eiPzFWML9isjqzd
 =y40Y
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu SoC changes for v3.17 (round 4)" from Jason Cooper:

 - Armada XP
    - Fix return value check in pmsu code
    - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)

 - Armada 370/38x
    - Add cpuidle support

 - mvebu
    - Fix build when no platforms are selected
    - Update EBU SoC status in docs

* tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu: (21 commits)
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
  ARM: mvebu: use a local variable to store the resume address
  ARM: mvebu: make the cpuidle initialization more generic
  ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
  ARM: mvebu: use the common function for Armada 375 SMP workaround
  ARM: mvebu: add a common function for the boot address work around
  ARM: mvebu: sort the #include of pmsu.c in alphabetic order
  ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
  ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
  clk: mvebu: extend clk-cpu for dynamic frequency scaling
  ARM: mvebu: extend PMSU code to support dynamic frequency scaling
  ...

Conflicts:
	arch/arm/mach-mvebu/Kconfig
	drivers/cpuidle/cpuidle-armada-370-xp.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 18:17:08 +02:00
Arnd Bergmann f169f4007e Linux 3.16-rc6
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJTzJFGAAoJEHm+PkMAQRiGNzQH/087gQch5K+A2HKvPzjUXq57
 G82DJHLONMMq8+NY3Vqhp8g2V8zRbXGJEvMJMsyuscO37Vo7ADcrYo8lqY9w5bIl
 h+Zarhkqz0rqRs2SfMMIVzdd2W7MzL+lqj3GplGPxHztw0+qk7PRKILx6eRppGaH
 JaD4NfkD5+1vfve/2d1ze9D5pCiw6PFNzjesKZxScQhNhIyLdRamfSTY4r9XeURo
 CxpwjphEYfvAcgc39mwzEHPHyKSqULu0By6R8FXQpJ9QjVtzcGEiF+cPqGncpZOR
 5ZSyU5e1CpBl9w8o6Lm9ewXmaCSnBU/VFrOwWvZrXfokZedXBOz7KdShU93XFjU=
 =0VJM
 -----END PGP SIGNATURE-----

Merge branches 'samsung/cleanup' and 'samsung/s5p-cleanup-v2', tag 'v3.16-rc6' into next/soc

The following samsung branches are based on these cleanups,
which are already in mainline before this branch gets pulled.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 11:59:20 +02:00
Arnd Bergmann ce800342c8 ARM: mvebu: fix build without platforms selected
When building a multiplatform kernel that enables 'ARCH_MVEBU' but
none of the individual options under it, we get this link error:

arch/arm/mach-mvebu/built-in.o: In function `mvebu_armada375_smp_wa_init':
:(.text+0x190): undefined reference to `mvebu_setup_boot_addr_wa'

The best solution seems to be to ensure that in this configuration,
we don't actually build any of the mvebu code.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/7339332.ZE2mWIdyDh@wuerfel
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 23:14:36 +00:00
Jason Cooper 54ef3fe697 Merge branch 'mvebu/soc-cpuidle' into mvebu/soc
Conflicts:
	arch/arm/mach-mvebu/pmsu.c
2014-07-24 23:10:02 +00:00
Gregory CLEMENT e53b1fd432 ARM: mvebu: add cpuidle support for Armada 38x
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9
core. Consequently, the procedure to enter the idle state is
different: interaction with the SCU, not disabling snooping, etc.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-16-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:40 +00:00
Gregory CLEMENT 3b9e4b1441 ARM: mvebu: add cpuidle support for Armada 370
This commit introduces the cpuidle support for Armada 370. The main
difference compared to the already supported Armada XP is that the
Armada 370 has an issue caused by "a slow exit process from the deep
idle state due to heavy L1/L2 cache cleanup operations performed by
the BootROM software" (cf errata GL-BootROM-10).

To work around this issue, we replace the restart code of the BootROM
by some custom code located in an internal SRAM. For this purpose, we
use the common function mvebu_boot_addr_wa() introduced in the commit
"ARM: mvebu: Add a common function for the boot address work around".

The message in case of failure to suspend the system was switched from
the warn level to the debug level. Indeed due to the "slow exit
process from the deep idle state" in Armada 370, this situation
happens quite often. Using the debug level avoids spamming the kernel
logs, but still allows to enable it if needed.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-15-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:37 +00:00
Gregory CLEMENT f50ee82471 cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
This driver will be able to manage the cpuidle for more SoCs than just
Armada 370 and XP. It will also support Armada 38x and potentially
other SoC of the Marvell Armada EBU family. To take this into account,
this patch renames the driver and its symbols.

It also changes the driver name from cpuidle-armada-370-xp to
cpuidle-armada-xp, because separate platform drivers will be
registered for the other SoC types. This change must be done
simultaneously in the cpuidle driver and in the PMSU code in order to
remain bisectable.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lkml.kernel.org/r/1406120453-29291-12-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:11 +00:00
Gregory CLEMENT 6a2b5343e2 ARM: mvebu: export the SCU address
The SCU address will be needed in other files than board-v7.c,
especially in pmsu.c for cpuidle related activities. So this patch
adds a function that allows to retrieve the virtual address at which
the SCU has been mapped.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:40 +00:00