Commit Graph

55 Commits

Author SHA1 Message Date
Arnd Bergmann 738590a3fe ARM SCMI updates/fixes for v5.4
Handful of fixes/updates including:
 1. SCMI v2.0(recently released) support for:
 	- Performance protocol fast channels
 	- Reset Management Protocol
 2. SCMI infrastructure/core support for recieve(Rx) channels,
    asynchronous commands and delayed response
 3. Usage of asynchronous commands for clock rate setting and sensor
    reading based on the attributes read from the firmware
 4. Miscellaneous cleanups(typos, naming alignment with specification,
    and SPDX License identifier)
 5. Couple of fixes: removal of extra check for invalid length and
    additional check to ensure platform/firmware has released shared
    memory before using it in OSPM
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Merge tag 'scmi-updates-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers

ARM SCMI updates/fixes for v5.4

Handful of fixes/updates including:
1. SCMI v2.0(recently released) support for:
	- Performance protocol fast channels
	- Reset Management Protocol
2. SCMI infrastructure/core support for recieve(Rx) channels,
   asynchronous commands and delayed response
3. Usage of asynchronous commands for clock rate setting and sensor
   reading based on the attributes read from the firmware
4. Miscellaneous cleanups(typos, naming alignment with specification,
   and SPDX License identifier)
5. Couple of fixes: removal of extra check for invalid length and
   additional check to ensure platform/firmware has released shared
   memory before using it in OSPM

* tag 'scmi-updates-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (22 commits)
  reset: Add support for resets provided by SCMI
  firmware: arm_scmi: Add RESET protocol in SCMI v2.0
  dt-bindings: arm: Extend SCMI to support new reset protocol
  firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
  firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
  firmware: arm_scmi: Use {get,put}_unaligned_le{32,64} accessors
  firmware: arm_scmi: Use asynchronous CLOCK_RATE_SET when possible
  firmware: arm_scmi: Drop config flag in clk_ops->rate_set
  firmware: arm_scmi: Add asynchronous sensor read if it supports
  firmware: arm_scmi: Drop async flag in sensor_ops->reading_get
  firmware: arm_scmi: Add support for asynchronous commands and delayed response
  firmware: arm_scmi: Add mechanism to unpack message headers
  firmware: arm_scmi: Separate out tx buffer handling and prepare to add rx
  firmware: arm_scmi: Add receive channel support for notifications
  firmware: arm_scmi: Segregate tx channel handling and prepare to add rx
  firmware: arm_scmi: Reorder some functions to avoid forward declarations
  firmware: arm_scmi: Check if platform has released shmem before using
  firmware: arm_scmi: Use the term 'message' instead of 'command'
  firmware: arm_scmi: Fix few trivial typos in comments
  firmware: arm_scmi: Remove extra check for invalid length message responses
  ...

Link: https://lore.kernel.org/r/20190814172454.26191-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-14 20:46:38 +02:00
Sudeep Holla c8ae9c2da1 reset: Add support for resets provided by SCMI
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

Adds support for the resets provided using SCMI protocol for performing
reset management of various devices present on the SoC. Various reset
functionalities are achieved by the means of different ARM SCMI device
operations provided by the ARM SCMI framework.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-12 12:23:02 +01:00
Gustavo Pimentel ea651ffd4f reset: Add DesignWare IP support to simple reset
The reset-simple driver can be now used on DesignWare IPs by
default by selecting the following compatible strings:
 - snps,dw-high-reset for active high resets inputs
 - snps,dw-low-reset for active low resets inputs

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Luis Oliveira <luis.oliveira@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-08-06 15:31:13 +02:00
Olof Johansson 8c0993621c Reset controller changes for v5.3
This tag adds support for the Bitmain BM1880 reset controller to the
 reset-simple driver and fixes a spelling mistake in the i.MX7 reset
 controller binding document.
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Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers

Reset controller changes for v5.3

This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.

* tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: reset: imx7: Fix the spelling of 'indices'
  reset: Add reset controller support for BM1880 SoC
  dt-bindings: reset: Add devicetree binding for BM1880 reset controller

Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-04 07:05:23 -07:00
Manivannan Sadhasivam 64c47b624f reset: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC reusing the
reset-simple driver.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-05-24 16:08:14 +02:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Andrey Smirnov c979dbf599 reset: imx7: Add support for i.MX8MQ IP block variant
Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.

Cc: p.zabel@pengutronix.de
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[p.zabel@pengutronix.de: fixed whitespace alignment]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-28 11:16:04 +01:00
Florian Fainelli 77750bc089 reset: Add Broadcom STB SW_INIT reset controller driver
Add support for resetting blocks through the Linux reset controller
subsystem when reset lines are provided through a SW_INIT-style reset
controller on Broadcom STB SoCs.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-28 11:16:04 +01:00
Kunihiko Hayashi 3eb8f765f5 reset: uniphier-usb3: Rename to reset-uniphier-glue
This driver works for controlling the reset lines including USB3
glue layer, however, this can be applied to other glue layers.
Now this patch renames the driver from "reset-uniphier-usb3" to
"reset-uniphier-glue".

At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to
CONFIG_RESET_UNIPHIER_GLUE.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-07 16:38:51 +01:00
Dinh Nguyen b3ca9888f3 reset: socfpga: add an early reset driver for SoCFPGA
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.

We do not need this early reset driver for Stratix10, because on
arm64, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer. Thus, we use
a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
The Stratix10 platform will continue to use the reset-simple platform
driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-07 16:38:50 +01:00
Sibi Sankar eea2926b0a reset: qcom: PDC Global (Power Domain Controller) reset controller
Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-10-05 10:33:44 +02:00
Jerome Brunet d903779b58 reset: meson: add meson audio arb driver
The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-20 18:17:31 +02:00
Kunihiko Hayashi 499fef09a3 reset: uniphier: add USB3 core reset control
Add a reset line to enable USB3 core implemented in UniPhier SoCs.

This reuses only the reset operations in reset-simple, because
the reset-simple doesn't handle any SoC-dependent clocks and resets.
This reset line is included in the USB3 glue layer, and it's necessary
to enable clocks and deassert resets of the layer before using this
reset line.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-16 12:15:55 +02:00
Sibi Sankar 5ecb065165 reset: qcom: AOSS (always on subsystem) reset controller
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-16 12:15:51 +02:00
Gabriel Fernandez 197858b685 reset: stm32mp1: Enable stm32mp1 reset driver
stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
	activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register	has no effect
Writing '1' on reset CLEAR register
	releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-03-27 10:44:04 +02:00
Masahiro Yamada 8fa566206e reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
This config select's MFD_SYSCON, but does not depend on HAS_IOMEM.

Compile testing on architecture without HAS_IOMEM causes "unmet
direct dependencies" in Kconfig phase.

Detected by "make ARCH=score allyesconfig".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-03-27 10:44:02 +02:00
Joel Stanley 1d7592f84f reset: simple: Enable for ASPEED systems
ASPEED BMC SoCs have a reset controller in the LPC IP that can be
controlled using this driver to release the UARTs from reset.

No special configuration is required, so only the compatible string is
added.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-02-20 17:42:29 +01:00
Philipp Zabel 542befbb18 Merge branch 'reset/arc' into reset/next
Merge the AXS10x driver, which is also merged into
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git for-next
2017-10-18 15:59:30 +02:00
Philipp Zabel f0e0ada67d reset: zx2967: use the reset-simple driver
The reset-simple driver can be used without changes.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
2017-10-18 15:51:04 +02:00
Philipp Zabel 0af8a13736 reset: stm32: use the reset-simple driver
The reset-simple driver can be used without changes.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2017-10-18 15:51:03 +02:00
Philipp Zabel adf20d7ce7 reset: socfpga: use the reset-simple driver
Add reset line status readback, inverted status support, and socfpga
device tree quirks to the simple reset driver, and use it to replace
the socfpga driver.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-18 15:51:02 +02:00
Philipp Zabel e13c205ac3 reset: sunxi: use reset-simple driver
Use the newly created copies in the reset-simple driver to replace the
sunxi platform driver code and reset operations. The separate sunxi
driver still remains to register the early reset controllers, but it
reuses the reset operations in reset-simple.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-10-17 15:35:24 +02:00
Philipp Zabel 81c22ad0cc reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967
Copy reusable parts from the sunxi driver, to add a driver for simple
reset controllers with reset lines that can be controlled by toggling
bits in exclusive, contiguous register ranges using read-modify-write
cycles under a spinlock.

The following patches will replace compatible reset drivers with
reset-simple, extending it where necessary.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2017-10-17 15:35:20 +02:00
Dinh Nguyen db21f9cfd5 reset: socfpga: build the reset-socfpga for Stratix10 SOC
Enable the reset driver to get built for the Stratix10 platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-04 10:36:02 +02:00
Geert Uytterhoeven 544e3bf4f0 reset: Restrict RESET_HSDK to ARC_SOC_HSDK or COMPILE_TEST
The HSDK reset driver is only useful when building for an ARC HSDK
platform.

While at it, drop the "default n", as that is the default.

Fixes: e0be864f14 ("ARC: reset: introduce HSDKv1 reset driver")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
[p.zabel@pengutronix.de: rebased, renamed RESET_HSDK_V1 to RESET_HSDK]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-21 12:44:01 +02:00
Eugeniy Paltsev 376349232a ARC: reset: introduce AXS10x reset driver
ARC AXS10x boards support custom IP-block which allows to control
reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines. This regiter is self-clearing so we
don't need to deassert line after reset.

As of today only the following lines are used:
 - DW GMAC - line 5

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-18 18:41:27 +02:00
Vineet Gupta 13541226dc ARC: reset: remove the misleading v1 suffix all over
There is no plan yet to do a v2 board. And even if we were to do it only
some IPs would actually change, so it be best to add suffixes at that
point, not now !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-18 13:02:03 +02:00
Thomas Meyer 2d48a237c8 ARC: reset: Only build on archs that have IOMEM
This avoids the error:
drivers/reset/reset-hsdk-v1.o: In function `hsdkv1_reset_probe':
/home/thomas/git/linux/drivers/reset/reset-hsdk-v1.c:101: undefined
reference to `devm_ioremap_resource'
collect2: error: ld returned 1 exit status

Signed-off-by: Thomas Meyer <thomas@m3y3r.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-09-18 10:57:48 +02:00
Linus Torvalds 7318413077 Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.14 for MIPS; below a summary of
  the non-merge commits:

  CM:
   - Rename mips_cm_base to mips_gcr_base
   - Specify register size when generating accessors
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Add cluster & block args to mips_cm_lock_other()

  CPC:
   - Use common CPS accessor generation macros
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Introduce register modify (set/clear/change) accessors
   - Use change_*, set_* & clear_* where appropriate
   - Add CM/CPC 3.5 register definitions
   - Use GlobalNumber macros rather than magic numbers
   - Have asm/mips-cps.h include CM & CPC headers
   - Cluster support for topology functions
   - Detect CPUs in secondary clusters

  CPS:
   - Read GIC_VL_IDENT directly, not via irqchip driver

  DMA:
   - Consolidate coherent and non-coherent dma_alloc code
   - Don't use dma_cache_sync to implement fd_cacheflush

  FPU emulation / FP assist code:
   - Another series of 14 commits fixing corner cases such as NaN
     propgagation and other special input values.
   - Zero bits 32-63 of the result for a CLASS.D instruction.
   - Enhanced statics via debugfs
   - Do not use bools for arithmetic. GCC 7.1 moans about this.
   - Correct user fault_addr type

  Generic MIPS:
   - Enhancement of stack backtraces
   - Cleanup from non-existing options
   - Handle non word sized instructions when examining frame
   - Fix detection and decoding of ADDIUSP instruction
   - Fix decoding of SWSP16 instruction
   - Refactor handling of stack pointer in get_frame_info
   - Remove unreachable code from force_fcr31_sig()
   - Convert to using %pOF instead of full_name
   - Remove the R6000 support.
   - Move FP code from *_switch.S to *_fpu.S
   - Remove unused ST_OFF from r2300_switch.S
   - Allow platform to specify multiple its.S files
   - Add #includes to various files to ensure code builds reliable and
     without warning..
   - Remove __invalidate_kernel_vmap_range
   - Remove plat_timer_setup
   - Declare various variables & functions static
   - Abstract CPU core & VP(E) ID access through accessor functions
   - Store core & VP IDs in GlobalNumber-style variable
   - Unify checks for sibling CPUs
   - Add CPU cluster number accessors
   - Prevent direct use of generic_defconfig
   - Make CONFIG_MIPS_MT_SMP default y
   - Add __ioread64_copy
   - Remove unnecessary inclusions of linux/irqchip/mips-gic.h

  GIC:
   - Introduce asm/mips-gic.h with accessor functions
   - Use new GIC accessor functions in mips-gic-timer
   - Remove counter access functions from irq-mips-gic.c
   - Remove gic_read_local_vp_id() from irq-mips-gic.c
   - Simplify shared interrupt pending/mask reads in irq-mips-gic.c
   - Simplify gic_local_irq_domain_map() in irq-mips-gic.c
   - Drop gic_(re)set_mask() functions in irq-mips-gic.c
   - Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
     gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
   - Convert remaining shared reg access, local int mask access and
     remaining local reg access to new accessors
   - Move GIC_LOCAL_INT_* to asm/mips-gic.h
   - Remove GIC_CPU_INT* macros from irq-mips-gic.c
   - Move various definitions to the driver
   - Remove gic_get_usm_range()
   - Remove __gic_irq_dispatch() forward declaration
   - Remove gic_init()
   - Use mips_gic_present() in place of gic_present and remove
     gic_present
   - Move gic_get_c0_*_int() to asm/mips-gic.h
   - Remove linux/irqchip/mips-gic.h
   - Inline __gic_init()
   - Inline gic_basic_init()
   - Make pcpu_masks a per-cpu variable
   - Use pcpu_masks to avoid reading GIC_SH_MASK*
   - Clean up mti, reserved-cpu-vectors handling
   - Use cpumask_first_and() in gic_set_affinity()
   - Let the core set struct irq_common_data affinity

  microMIPS:
   - Fix microMIPS stack unwinding on big endian systems

  MIPS-GIC:
   - SYNC after enabling GIC region

  NUMA:
   - Remove the unused parent_node() macro

  R6:
   - Constify r2_decoder_tables
   - Add accessor & bit definitions for GlobalNumber

  SMP:
   - Constify smp ops
   - Allow boot_secondary SMP op to return errors

  VDSO:
   - Drop gic_get_usm_range() usage
   - Avoid use of linux/irqchip/mips-gic.h

  Platform changes:

  Alchemy:
   - Add devboard machine type to cpuinfo
   - update cpu feature overrides
   - Threaded carddetect irqs for devboards

  AR7:
   - allow NULL clock for clk_get_rate

  BCM63xx:
   - Fix ENETDMA_6345_MAXBURST_REG offset
   - Allow NULL clock for clk_get_rate

  CI20:
   - Enable GPIO and RTC drivers in defconfig
   - Add ethernet and fixed-regulator nodes to DTS

  Generic platform:
   - Move Boston and NI 169445 FIT image source to their own files
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Allow filtering enabled boards by requirements
   - Don't explicitly disable CONFIG_USB_SUPPORT
   - Bump default NR_CPUS to 16

  JZ4700:
   - Probe the jz4740-rtc driver from devicetree

  Lantiq:
   - Drop check of boot select from the spi-falcon driver.
   - Drop check of boot select from the lantiq-flash MTD driver.
   - Access boot cause register in the watchdog driver through regmap
   - Add device tree binding documentation for the watchdog driver
   - Add docs for the RCU DT bindings.
   - Convert the fpi bus driver to a platform_driver
   - Remove ltq_reset_cause() and ltq_boot_select(
   - Switch to a proper reset driver
   - Switch to a new drivers/soc GPHY driver
   - Add an USB PHY driver for the Lantiq SoCs using the RCU module
   - Use of_platform_default_populate instead of __dt_register_buses
   - Enable MFD_SYSCON to be able to use it for the RCU MFD
   - Replace ltq_boot_select() with dummy implementation.

  Loongson 2F:
   - Allow NULL clock for clk_get_rate

  Malta:
   - Use new GIC accessor functions

  NI 169445:
   - Add support for NI 169445 board.
   - Only include in 32r2el kernels

  Octeon:
   - Add support for watchdog of 78XX SOCs.
   - Add support for watchdog of CN68XX SOCs.
   - Expose support for mips32r1, mips32r2 and mips64r1
   - Enable more drivers in config file
   - Add support for accessing the boot vector.
   - Remove old boot vector code from watchdog driver
   - Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
   - Make CSR functions node aware.
   - Allow access to CIU3 IRQ domains.
   - Misc cleanups in the watchdog driver

  Omega2+:
   - New board, add support and defconfig

  Pistachio:
   - Enable Root FS on NFS in defconfig

  Ralink:
   - Add Mediatek MT7628A SoC
   - Allow NULL clock for clk_get_rate
   - Explicitly request exclusive reset control in the pci-mt7620 PCI driver.

  SEAD3:
   - Only include in 32 bit kernels by default

  VoCore:
   - Add VoCore as a vendor t0 dt-bindings
   - Add defconfig file"

* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
  MIPS: Refactor handling of stack pointer in get_frame_info
  MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
  MIPS: microMIPS: Fix decoding of swsp16 instruction
  MIPS: microMIPS: Fix decoding of addiusp instruction
  MIPS: microMIPS: Fix detection of addiusp instruction
  MIPS: Handle non word sized instructions when examining frame
  MIPS: ralink: allow NULL clock for clk_get_rate
  MIPS: Loongson 2F: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: allow NULL clock for clk_get_rate
  MIPS: AR7: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
  mips: Save all registers when saving the frame
  MIPS: Add DWARF unwinding to assembly
  MIPS: Make SAVE_SOME more standard
  MIPS: Fix issues in backtraces
  MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
  MIPS: Ci20: Enable RTC driver
  watchdog: octeon-wdt: Add support for 78XX SOCs.
  watchdog: octeon-wdt: Add support for cn68XX SOCs.
  watchdog: octeon-wdt: File cleaning.
  ...
2017-09-15 20:43:33 -07:00
Martin Blumenstingl 79797b6fad reset: Add a reset controller driver for the Lantiq XWAY based SoCs
The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.

For some devices the request and the status bits are different.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Cc: john@phrozen.org
Cc: kishon@ti.com
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17125/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-09-04 21:19:02 +02:00
Linus Walleij a3843bee77 Revert "reset: Add a Gemini reset controller"
This reverts commit 2acb037fc4.

We ended up merging the reset controller into the clock
controller so we can now get rid of this stand-alone
implementation.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-08-07 12:05:01 +02:00
Eugeniy Paltsev e0be864f14 ARC: reset: introduce HSDKv1 reset driver
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.

The list of available reset lines is documented in the DT bindings.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-20 11:48:16 +02:00
Andrew F. Davis 28df169b9a reset: Add the TI SCI reset driver
Some TI Keystone family of SoCs contain a system controller (like the
Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations
are provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management
of various devices present on the SoC. Various reset functionalities
are achieved by the means of different TI SCI device operations
provided by the TI SCI framework.

Signed-off-by: Andrew F. Davis <afd@ti.com>
[s-anna@ti.com: documentation changes, revised commit message]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
[p.zabel@pengutronix.de: const struct reset_control_ops]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-06 09:44:17 +02:00
Linus Walleij 2acb037fc4 reset: Add a Gemini reset controller
The Cortina Systems Gemini reset controller is a simple
32bit register with self-deasserting reset lines. It is
accessed using regmap over syscon.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 10:46:13 +02:00
Suman Anna dd9bf86340 reset: ti_syscon: Rename TI_SYSCON_RESET to RESET_TI_SYSCON
Rename the current Kconfig name used for the TI SYSCON Reset
driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the
convention used for all the reset drivers present at the
base reset folder.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 10:21:44 +02:00
Thor Thayer 6270068202 reset: Add Altera Arria10 SR Reset Controller
This patch adds the reset controller functionality for
Peripheral PHYs to the Arria10 System Resource Chip.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15 12:19:11 +01:00
Andrey Smirnov abf97755ae reset: Add i.MX7 SRC reset driver
Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.

Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15 12:18:49 +01:00
Baoyou Xie b38386f46b reset: zx2967: add reset controller driver for ZTE's zx2967 family
This patch adds reset controller driver for ZTE's zx2967 family.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Reviewed-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-01-20 10:36:12 +01:00
Thierry Reding dc606c5205 reset: Add Tegra BPMP reset driver
This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:34:56 +01:00
Philipp Zabel 6f51b86007 reset: zynq: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-30 17:08:51 +02:00
Philipp Zabel 0ae084195b reset: sunxi: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-30 09:38:46 +02:00
Philipp Zabel 7e0e901d41 reset: stm32: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-30 09:38:45 +02:00
Philipp Zabel 5c91407ed3 reset: socfpga: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-30 09:38:44 +02:00
Philipp Zabel fab3f73098 reset: pistachio: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Acked-by: James Hartley <james.hartley@imgtec.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-30 09:38:10 +02:00
Philipp Zabel 44336c24a9 reset: meson: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-25 13:27:44 +02:00
Philipp Zabel cd7f4b81cf reset: lpc18xx: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-25 13:27:43 +02:00
Philipp Zabel 70d467ea16 reset: berlin: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-25 13:27:42 +02:00
Philipp Zabel e27b4a6e63 reset: ath79: add driver Kconfig option
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.

Acked-by: Aban Bedel <albeu@free.fr>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-25 13:27:35 +02:00
Masahiro Yamada 54e991b566 reset: uniphier: add reset controller driver for UniPhier SoCs
This is the initial commit for UniPhier reset controller driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-24 15:21:35 +02:00
Andrew F. Davis cc7c2bb149 reset: add TI SYSCON based reset driver
Add a reset-controller driver for performing reset management of
various devices present on the SoC, with the reset registers shared
between devices in a common register memory space. This driver uses
the syscon/regmap frameworks to actually implement the various reset
functionalities needed by the reset consumer devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
[s-anna@ti.com: add documentation, syscon name change]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-29 23:39:10 +02:00