* Add support for R-Car H3 ES2.0
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY59ObAAoJENfPZGlqN0++mmAP/iLPRVjE0DoqVVQbNeIq4pOI
0HaIU2MZH6cPN2868CBp+8/UsPQXUBtpBRdRsc7+B2gSQteFhEZ8b+tTJ007BohM
YO4XSSfwEUedKoPB5N88hleGrXjvUbNBECOeD5XSOX3X9qQLDUkzpgDgfL0WPl6D
gU3G7IitR2KnBTz5n8XbrdTVccZbafXutj3Sp8pTxd4Yc8ajL8MkxbwTjlGratfw
sOUW1zxIv7c9eanfbYZQ3ZGNm++2w/WnqhPBTYfxcBVK95dslWjkxf7HawujeaP7
CihAakoH9QoYsrnyEMbMn4xpCJEYB8U5zaIzyOFHhGCtF5AXUrKFcn1DMpU7sORJ
mu4UDUHIugGsu/RdOcOdB/dZ5GcfFtVehDLKtAGdoAwyc6eY9URAwOlOV9abOCtf
qWSGHv0dKCVg5fLcuCzXMYd7DxXN1X4A0wj94S6XF5S1/wcWJaOU2uJKPSguoUzW
vQt4jIM7TUUK6YAVj0xec40lXf0AuJ4FcXI/9TEnYnmqzOEwZzKzrlMv3xnqp08k
jQarhWJLvN23lDAtGOorLJKOZyveXy0E3I9IJT8PgZpGmOlijSRBzhXsN1NeGsYo
663+3feI4Qe5vtu8Obv/vA0BcYHiA+AcEBwWYFAZOGGSM2IucORxX9UAu8XBmtRB
FnS/AB2yrsoL9VjKgeYt
=m+ef
-----END PGP SIGNATURE-----
Merge tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Sysc Updates for v4.12
* Add support for R-Car H3 ES2.0
* tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
base: soc: Allow early registration of a single SoC device
base: soc: Let soc_device_match() return no match when called too early
Signed-off-by: Olof Johansson <olof@lixom.net>
It includes a couple of small cleanups on zx296718 power domain drivers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY65viAAoJEFBXWFqHsHzOkqAH/ig7pVmp3s0H/4xmY3fKOpk2
R2FGXNSWSLyKt+jkQfTKfsQZmaGadefg6KUzXLuBdE306LZkZssmjLqBEv3LBGYE
oC+q29Y8S/qb3g1c+B2fMPO1MSfQWRGKgaKUOdDiFw7lBCBplsv2gzntW8aSSpi1
eNraNzpmaesSVUNPrO4uTwRNmvn9mx00k5H2OJWSnyMtFQzo+FDbpj1ULgMfLeLl
j6Jnszsp98STkB3Kzc9XGwO8OlHlsr/nnVvJVWJGiyFhwVTncGwLe9gL3ZqFxRYr
SjE4Z28xkHcajQBmYmA0SkNHdtERjKxzjYQo9nYP7/rI3kL5r12+iWU7Q29B0ck=
=JWPf
-----END PGP SIGNATURE-----
Merge tag 'zte-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
ZTE driver updates for 4.12:
It includes a couple of small cleanups on zx296718 power domain drivers.
* tag 'zte-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: zte: pm_domains: Remove .owner field for driver
soc: zte: pm_domains: Remove redundant dev_err call in zx2967_pd_probe()
Signed-off-by: Olof Johansson <olof@lixom.net>
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY6zd4AAoJEFBXWFqHsHzODtoH/jwTFRhAhfKG2wfplkP+U4HT
gijXHDybebRGll2voGAL7YX7GPhLcy0NSGdiK/ckTtHlvR4E2uxcwaIwzXIE1CTb
MXfv7p+3FXhjcqgbvl122hnLAMWOYjcbH3tFzBy1jlpGp9oEmHx4OtpdlgyD5GJ7
+En6aDtbU0g8aJg9ldZfO8iSAJz1CAqpap+FRjpcPX4xXflOQwQfxJNWuDeg75k6
U3zB2r+lbmjIfohUHWAnHsU2Jf4WPrBrjVsj/1YsiE5rMNPfxAEPYSQJAumG7JtO
qTPWf3qJnSyrWBscPRR3Fs//11IgXZXSCWBPBZjng0ELFS3Rkdvp87etjZraSjU=
=Sypm
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers updates for 4.12:
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
* tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
soc: imx: gpc: remove unnecessary readable_reg callback
dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
soc: imx: gpc: fix comment when power up domain
soc: imx: gpc: fix imx6sl gpc power domain regression
soc: imx: gpc: fix domain_index sanity check issue
soc: imx: gpc: fix the wrong using of regmap cache
soc: imx: gpc: fix gpc clk get error handling
soc: imx: move PGC handling to a new GPC driver
dt-bindings: add multidomain support to i.MX GPC DT binding
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJY52LfAAoJEEEQszewGV1zXCsP/A3A+ZdgJ5Y8A5sN58v1F8mN
cEPjDj3pvA+YGtIk3EGFhKGqeREMYV+9m2VENdDlM2hKt7PYZ9js4VguKw/SWcvK
vEf1UaTAACjtX3hsBU09oNBBKcju5Mz1Kd6aC7p9WktE4lEHqq0S3j98psvGZmlP
H1mW5tC0eF3KHHiIPe30rCniWnAubWacos/y34t+e/bYm942OwmpjwOpli2TNok5
oIDi3c+84X3yL1gZ37z3UAxgPRDgQ1sZf04H4QUoeuHyKGu+olgeKK5uvsclFBS2
FrtL78IS9IqP4bIc67i+pj9/Idw18KWnXwdNDDajEKWlHcmqGPkpjRD2AyAvGw6K
3VNH+mpYlIEIuA+MZowVfXuIXr5iG3NkBKBndpcl4Pu8H/hNBFw3bb4J6IK8Jmbh
VhZVgUXDaOb/3qBWV8h5nVzi5dSMchCnMO0xuCTgzZIs6IEHr6XGk2oq50vBevkN
skJpRp9fHkdSOiG2r7PW8UoDjULxEq+1REg9p7urJsbgkAaGAozuaXJRq8+smHsy
Vv4QczFWi9/ygEvbYJ5ZhpzLz3Wo30vKsWCfm9+9D97fHQPwAhywf61O4tWJBLwp
7Xm+ozOmbd5KQ+PdN+j0vz3IXccxD9Zs67j12TgxO9gzzz1VvNdTPywDOzDawmeI
2oHs7RnHy9LDhNW3HNQy
=012f
-----END PGP SIGNATURE-----
Merge tag 'arm-to-clk-icst' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers
This moves the ICST helper library from arch/arm to drivers/clk
* tag 'arm-to-clk-icst' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
Signed-off-by: Olof Johansson <olof@lixom.net>
This contains PMC support for Tegra186 as well as a proper driver for
the flow controller found on SoCs up to Tegra210. This also turns the
fuse driver into an explicitly non-modular driver.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmx1ITHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoWt2D/9hNQqNgxW+6QOq3EuxWHDPs6hWOHRy
v13TM7cQg7Qc6zXnmc+SzEp5eT7+GbNNgtrQ7ukfzKPeDwbPXf+NwsprS+STayvF
dxqtcem/6tID3WJxzYJRJY3d8hH3BCvQhJf+uF8V2za1F/f4f6mHDtUboPVO2LIa
L4IdtXQEwoVyPdnH2GDdKG6uOHnufBLVsS+DFXWeuY/nPiTgFcBQAgOuNwFZK1/V
FisKON2QIg0yh6Y7UjDGh5X9ODR2OC+9g1kGV7hY3tlvz/JovZxc8CPnQsPg2QR7
1heGwNTHEOkAeClvRdAr+guV1wDvY4vA+2U1XeQeSLg3gq4lIfRKp8+xrwfnkyS+
rmllTA/85LCiTO9slKoSdv6vSSgb7K549z/dYdIqwDTPU0GE1xzFF4DTvs2OwmtF
y4ziCDM+6H1EgesZDcVZikVFjof+q8h2j1FEsloe6HjmhcJ42lQWRLFbEPk1XMec
cWNynVMjRxaQP/8cJTHYpnpa6e6/Eqv1GhWYWl+9yqodJhBJtrzPZLaGKfYiaG2R
QcG48WsBGDtV5zYKUEG5/LKNWaFvcAjhfi9JXh44FMBlBNZ+EyWThJPTvL06glk4
SKaBx69Ft5fOHlIQG9/lT+u0RmLmmMkSNHeW/Zh9s08xeJhK3lHLnpT8s6kDxui5
Nhid59CnZh8SnQ==
=n4aM
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
soc/tegra: Core SoC changes for v4.12-rc1
This contains PMC support for Tegra186 as well as a proper driver for
the flow controller found on SoCs up to Tegra210. This also turns the
fuse driver into an explicitly non-modular driver.
* tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
soc: tegra: make fuse-tegra explicitly non-modular
soc/tegra: Fix link errors with PMC disabled
soc/tegra: Implement Tegra186 PMC support
Signed-off-by: Olof Johansson <olof@lixom.net>
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY5n1GAAoJEHJsHOdBp5c/HskP/RK+Q939tIdFI2joV0R2uBF8
sSPHHfduY/GZpy+Mlqxjo5gYE1AxGY+rOw0YNWWvZ1hpkIgP4g0zC0yCxQaLnYF2
VuEoZwaEcGDKsmTISoKkMp8tonxW2EOQUsYty8Iq66rGsrRgTVqmsM8ApJSqyo6l
+nD/AQnWboNnKiJ3t6HE1xc8YLWFPiLfl5EgzR3OyXKfrRjQ7mg9SEddmnrOunLd
T8fqVgAtOgcb7a5LIuGq/4ddSQPm38fDYSc4QtSmhZfgke94+xKHrBAcBVXNJOaC
ESxvhu4l4xarj6aagWz7TmokFt7JNXgmcC9nZkU/YcKdidVN6dhF+MraFQpZnMAJ
ZYFfz++6gNiFWKRnaQWmsXaCzgxlnpajJL5th39/izwFHKMWU87lXO5WSZnOdosA
1Ph8M7zAmxjAE0R3TIFjRnT25spYxYqWNFhrCSpIuYODZNefAZqaJSP6WG7ab+Hy
u9qpVjAYCxir36sS/pTHiiGDLlGiUM+3lOtT9o5xWZCv9gBLiYLziW33nKbgQR2s
4KrfKnNq4Kkvx3rHM30GPzVXziliqS1TF/j6vl8Tx/m/RnXtT2DBknvW5c43NBbF
Ad1Ux6JJ9M3b009wjo5sEWzemFlKKIuWh0ekvr3YYcVlGGqXDK7os4fvfsFPbHv+
6CmNAQt6rbbGI+8pJC5w
=ayBe
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
ARM SOC PM domain support for 4.12
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
* tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
Signed-off-by: Olof Johansson <olof@lixom.net>
Add reset lines for the NAND and eMMC contollers on LD11/LD20 SoCs.
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAljjx4oXHHAuemFiZWxA
cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOsw2xAAk57XCukWVQyBLf8T6ioFi3WT
XOVm5ISSd4oC5TP/Jy/gUmNkpWidolXaCmIvl6izLd8wB+vo45eubvwEVRf7oGRA
hidL6BomWcLfZkxAgkuSHmBDExsHljjmmrEm4YdMCvufkuEUE0zFMGGeShWFsIbF
4m2vdiNthAWKfcvFPmJrAFWG8r4lU93M3GN/M35vmNNHNyesjrR8K0tGY3z/Xn/0
1ZynwxGUmgPTFm/Bb6kotfzMBebnW/ryAOnhVLv83ErNvy+4PCnTAVNeeRXbNuCF
9ZKa2HZKn/9Le0glDdyx2cH55QcG2azk2np8kTup30U4uql4d7mmgG7o2SFaoZpJ
47ULmJKqbxT00PYMye6YETS/Zm3lyXTB51zP2aJ/pMCSEFsGPX64b4GlO2XYuFk/
9tfUKsx5CmBntfY5xlw5I5xXAM7EpesPRnTfiVt0JyggrmQYHSEpmeutj30zjkwU
94ZeC++ScX20VVSRUkTEY5BlSh0hnENGr8noVkwvQn2mnKINx+YGXcKwTlsyhGRV
6AFsT1n6pHtv1OB3V7WZ6IP/Othxq7XlVIvZox2fxV9bgiDjqeSaojrtcKgmrNCv
NGWeMfdQ2Z+eBfL4HJMWLgqjDShJaie6niOdJTOTqn5ZOujV8g/Hb/abRxEX8aen
0glbvB590jmVd1x7QcQ=
=mN0u
-----END PGP SIGNATURE-----
Merge tag 'reset-for-4.12-2' of git://git.pengutronix.de/git/pza/linux into next/drivers
Reset controller changes for v4.12, part 2
Add reset lines for the NAND and eMMC contollers on LD11/LD20 SoCs.
* tag 'reset-for-4.12-2' of git://git.pengutronix.de/git/pza/linux:
reset: uniphier: add NAND and eMMC reset control
Signed-off-by: Olof Johansson <olof@lixom.net>
PATA controller found on DM6446 and
DM6467 SoCs. This should eventually
replace the driver in IDE subsystem.
The patches have been acked by ATA
maintainer.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY4z5IAAoJEGFBu2jqvgRNfu0P/RI0SJMvqXoQ/mBk2rwz+f/b
QcdnI/yqesOI1vTO0uGMsbSORdCa1GljAO68xNUh3k0HD/YupiekZjKL/2RmZxwn
U0jSAIv7tYZuSRcP1QTPf1nVa9d4OiDRqtsg6MHvwQJA8H50zYJDvwaZPA4Y1Neq
fWSRFZnPZKqJwIrDDuhAKnb1plnrAxr7DY1og82q9deRl/M7tDstU5lGpoMTz5md
8wzMyFJ96eFQZYzOvu3HVm5wJC5fbUMvfJBivoXOF1BClHtZsuCs+3v8wsdL4E+2
WQyLQT1glLgXOkNdD9FpQkEKFHseiLkPEwCrW2P0BG+EUGun3j9GPudywnOJn/so
QAl87dd8MmzSmmxj0A4wJbH+K8cK1tdWLKBDSaTxNrsZIyLMAH8thFItEe6fs1FG
MYn7Fk3Igujb6WBTUlI+Q23A/UGYBR8FW6xDEiecTSGVR6vfF5RCcYkA4eHgQIwC
jScsKYXGd/NTW7ik8rckXD5OTp+pF6HDwJAVPUoJxUuak+taXAs9FGqs/KCsTeNs
Kjp6sI3vk/dfeMkrOuBqMA/u59VLPDDreJQlqdruU7XKUr83PafDft0rsj6AkbnW
Vrwe3yF85dV0ygob2yQNHnZFar9Ffus9rKA45RcFdz7Yino/MbTCiwi3yG0ytbAv
Ge8Ox3YlnyX8mC+HTfEn
=t+di
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v4.12/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
This adds a new driver for PalmChip PATA controller found on DM6446 and
DM6467 SoCs. This should eventually replace the driver in IDE subsystem.
The patches have been acked by ATA maintainer.
* tag 'davinci-for-v4.12/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
pata_bk3710: clear status bits of BMISP on chipset initialization
pata_bk3710: disable IORDY Timer on chipset initialization
ata: add Palmchip BK3710 PATA controller driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Single patch to optimise the completion initialisation using reinit_*
API instead of full initialisation on each and every transfer.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJY3oJjAAoJEABBurwxfuKY/KcP/RiCHfcbIBVaA3W5MUSvNeQN
mpxfVXmBgyoqq81bZByrvcjtk/4/4q2nLoKucIZV8aGzTjXUrWhHCw9TIMQ8wrqz
doMfhbbaLC1I52dSXrmAYySI8psjEyC8vdtVlASeeX8PaMycTUfvRYoWPYLcxlwB
aOjkuQb04gyHGr64yJzECcebz7jmJ7+KHqO9UjYQUJWgBGv3Fz1WcM2AooJvNcXB
L04K8lJzcHzCREfw08iOdgHpegIq2rSje0Q5hf6OdNCGlv1U3hX53y7Yi7yDiQhJ
lIC+ko/DVfXlpFJ8mYS1VM9fMPhXiGXhp7ZQE3HEfQVkSqQj1F27ROyo4rHXZlbV
wiIgcJr2Cz2/GXvvnnTiBDmcQzChypQLMZJckorrH9fKEiILzxW3jdRO9Hi5tXUL
Ci/Yg0sZ8R+xik24KWK76O1zyry3Cstndn2mUJIG/1wlo4XtP11E5CLFnNAG+F+X
Nse/gJ6iKkHnVI9V0ml8rENVIlr2Pi3Obox8t7mBPOUf+tDjQAaVG1OqXINygo2y
9+C0jDmS0BJ3YuwEZHhIkzBH2fOMRw4aiRbDx8CRKp4es5cc3YGyVADzev75K+8E
oRoyDmClBMKwQy+E5EM/QY+0zGWYF7pf2rTElvrDHwGXvQErt1GOag1La8oNbqk2
DOEWgv8aL7E+FyoeWjrQ
=Iz6D
-----END PGP SIGNATURE-----
Merge tag 'scpi-update-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/drivers
SCPI update for v4.12
Single patch to optimise the completion initialisation using reinit_*
API instead of full initialisation on each and every transfer.
* tag 'scpi-update-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scpi: reinit completion instead of full init_completion()
Signed-off-by: Olof Johansson <olof@lixom.net>
Power area A2VC0 was removed in revision ES2.0, cfr. R-Car Gen3 Hardware
User's Manual rev. 0.53E.
Hence remove it from the power area table when not running on ES1.x.
This is in line with the goal to:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The same SoC may have different power areas, depending on SoC revision.
One option is to use different sets of power area tables for each SoC
revision. However, if the differences are small, it is much more
space-efficient to have a single set of tables, and fix those up at
runtime instead.
Hence provide a helper to NULLify power areas that do not exist on some
revisions (NULLified power areas are skipped during the registration
phase), and support for an optional initialization callback to e.g. fix
up power area tables.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7795 SYSC driver manages PM Domains, and thus is initialized from
an early_initcall(). However, this means the driver cannot check the
SoC revision, as the SoC device hasn't been registered yet.
Change renesas_soc_init() from a core_initcall() to an early_initcall()
to fix this (renesas-soc.o is listed before rcar-sysc.o in the Makefile).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
On i.MX6QP, due to hardware erratum ERR009619, the PRE clocks may be
stalled during the power up sequencing of the PU power domain. As this
may lead to a complete loss of display output, the recommended
workaround is to keep the PU domain enabled during normal system
operation.
Implement this by rejecting the domain power down request on the
affected SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
While the GPC on i.MX6QP is mostly comptible to the i.MX6Q one,
the QuadPlus requires special workarounds for hardware erratum
ERR009619.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Makes referencing a specfic domain in the driver code
less error prone.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add code allowing for control of various power domains managed by GPCv2
IP block found in i.MX7 series of SoCs. Power domains covered by this
patch are:
- PCIE PHY
- MIPI PHY
- USB HSIC PHY
- USB OTG1/2 PHY
Support for any other power domain controlled by GPC is not present, and
can be added at some later point.
Testing of this code was done against a PCIe driver.
Cc: yurovsky@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Dong Aisheng <dongas86@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This moves the ICST clock divider helper library from
arch/arm/common to drivers/clk/versatile so it is maintained
with the other clock drivers.
We keep the structure as a helper library intact and do not
fuse it with the clk-icst.c Versatile ICST clock driver: there
may be other users out there that need to use this library for
their clocking, and then it will be helpful to keep the
library contained. (The icst.[c|h] files could just be moved
to drivers/clk/lib or a similar location to share the library.)
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All the Versatile platforms (Integrator, Versatile, RealView
Versatile Express) have been migrated to use the drivers/clk
subsystem. Clean out this header that is not referenced
anywhere anymore.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
K2G will use a different power domain driver than the rest of the
keystone family in order to make use of the TI SCI protocol so prevent
the standard keystone pm_domain code from registering itself in
preparation for a new driver.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Introduce a ti_sci_pm_domains driver to act as a generic pm domain
provider to allow each device to attach and associate it's ti-sci-id so
that it can be controlled through the TI SCI protocol.
This driver implements a simple genpd where each device node has a
phandle to the power domain node and also must provide an index which
represents the ID to be passed with TI SCI representing the device using
a single phandle cell. The driver manually parses the phandle to get the
cell value. Through this interface the genpd dev_ops start and stop
hooks will use TI SCI to turn on and off each device as determined by
pm_runtime usage.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add a generic power domain implementation, TI SCI PM Domains, that
will hook into the genpd framework and allow the TI SCI protocol to
control device power states.
Also, provide macros representing each device index as understood
by TI SCI to be used in the device node power-domain references.
These are identifiers for the K2G devices managed by the PMMC.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
There is no reason that a platform genpd driver registered using
of_genpd_add_provider_simple needs to be constrained to having no cells
in the "power-domains" phandle. Currently the genpd framework will fail
if any arguments are passed with for a simple provider but the framework
does not actually care, so remove the check for phandle argument count.
This will allow greater flexibility for genpd providers to use their own
arguments that are passed in the phandle and interpret them however they
see fit.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add a void *data pointer to struct generic_pm_domain_data. Because this
exists for each device associated with a genpd it will allow us to
assign per-device data if needed on a platform for control of that
specific device.
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Tegra132 and Tegra210 support the flowctrl module and so add initial
support for these devices.
Please note that Tegra186 does not support the flowctrl module, so
update the initialisation function such that we do not fall back and
attempt to map the 'hardcoded' address range for Tegra186. Furthermore
64-bit Tegra devices have always had the flowctrl node defined in their
device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra
devices.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a simple platform driver for the flowctrl module so that it gets
registered as a proper device.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The flowctrl driver is required for both ARM and ARM64 Tegra devices
and in order to enable support for it for ARM64, move the Tegra flowctrl
driver into drivers/soc/tegra.
By moving the flowctrl driver, tegra_flowctrl_init() is now called by
via an early initcall and to prevent this function from attempting to
mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()'
is also added.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra flowctrl.h header is included unnecessarily by the Tegra
sleep.S source file. Remove this unnecessary inclusion.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Makefiles currently controlling compilation of this code is:
drivers/soc/tegra/Makefile:obj-y += fuse/
drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o
...meaning that it currently is not being built as a module by anyone.
Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
With the new Tegra186 PMC driver merged, anything that relies on the previous
PMC driver fails to link when that is disabled:
arch/arm/mach-tegra/pm.o: In function `tegra_pm_set':
pm.c:(.text.tegra_pm_set+0x3c): undefined reference to `tegra_pmc_enter_suspend_mode'
arch/arm/mach-tegra/pm.o: In function `tegra_suspend_enter':
pm.c:(.text.tegra_suspend_enter+0x4): undefined reference to `tegra_pmc_get_suspend_mode'
arch/arm/mach-tegra/pm.o: In function `tegra_init_suspend':
pm.c:(.init.text+0x1c): undefined reference to `tegra_pmc_get_suspend_mode'
pm.c:(.init.text+0x74): undefined reference to `tegra_pmc_set_suspend_mode'
ERROR: tegra_powergate_sequence_power_up [drivers/ata/ahci_tegra.ko] undefined!
ERROR: tegra_powergate_power_off [drivers/ata/ahci_tegra.ko] undefined!
Making the definition depend on the presence of the driver makes it build
again, though that might not be the correct fix.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Fixes: 854014236290 ("soc/tegra: Implement Tegra186 PMC support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The power management controller on Tegra186 has changed in backwards-
incompatible ways with respect to earlier generations. This implements a
new driver that supports inversion of the PMU interrupt as well as the
"recovery", "bootloader" and "forced-recovery" reboot commands.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of performing full initialization of the completion structure
on each transfer in scpi_send_message(), we initialize it at boot time
(more specifically, in the relevant probe() function) and use
reinit_completion() to reset ->done counter on each message transfer.
Signed-off-by: Alexey Klimov <alexey.klimov@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
please pull the following changes:
- Florian updates the Broadcom STB GISB arbiter driver with a bunch of
compatible strings for MIPS-based STBs found under arch/mips/boot/dts/brcm/ in
order for the SoC identification driver to recognize these chips
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY1VbnAAoJEIfQlpxEBwcEM3EP/12/FZ9Ch1nye2ZKGK/qSL1w
GxT1kvk9MWDdnX4KZDBbyU57qMYzgCMFGXzhFvX8NysnwfX10ac1cH0dwPuEnvTH
tVCREvOkhEZvDLXr+YhURw0dBEr8vQXa3DvdipAB14oGLw+ETb2QNSBgtAVfkF/q
TncO7FBQLdtH1sZHuuaPsPaoir0WFc9OtGkr3rOCrtVRD8TfJkObP33uXtvQNe5Z
enLtJ70bzPMLjAKQ7Rl9BFZDORnA2l+2jS7ckwRdpPcvBCjgSCC7arI6irX0Qhov
mUxMGjx6Durbmh6vRA8zCRB5sn/600sw8Zl8jGEAvTP/a33EfQc7G0zWiJ/eutTQ
owDMwrUrnjXEQXKv9Zn9AZFv7UJ2ImUDy6eBu949imFUS0w6ogaVfAQvDjaom28h
+GviF6xZqmIMiGQjluHZjHv84a1MhnMABD6L+C66Kqd9WJ2UryOqsE8284gf91+B
CSUO0th6eAuURfRcTFcaThI4lnxgaHOAphPH1dhKmPme7wmIwcVoBcb8ljs0fNil
re3+2Laeeaqsu0xJpceHN/glf60VBTI+fMckefd39AUBjSwlWD7PocO9shn+BLA1
fBR5PJGFUwmomDxpbOJQRrvPnw8sLEdvTP8iGqF+IOm9pBobVzo/VYureQPlPDCt
pLrRDZlATtMSfPra7JIl
=AueE
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.12/drivers' of http://github.com/Broadcom/stblinux into next/drivers
Pull "Broadcom drivers changes for 4.12" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoC drivers updates for 4.12,
please pull the following changes:
- Florian updates the Broadcom STB GISB arbiter driver with a bunch of
compatible strings for MIPS-based STBs found under arch/mips/boot/dts/brcm/ in
order for the SoC identification driver to recognize these chips
* tag 'arm-soc/for-4.12/drivers' of http://github.com/Broadcom/stblinux:
soc: bcm: brcmstb: Match additional compatible strings
Clear IORDYINT, INTRSTAT and DMAERROR bits of BMISP register
(value '1' needs to be written to the bit to clear it).
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Commit 1da1b3628d ("base: soc: Early register bus when needed")
added support for early registration of SoC devices from a
core_initcall(). However, some drivers need to check the SoC revision
from an early_initcall(), which is even earlier.
A specific example is the Renesas R-Car SYSC driver, which manages PM
Domains and thus needs to be initialized from an early_initcall.
Preproduction versions of the R-Car H3 SoC have an additional power
area, which no longer exists on H3 ES2.0, so the R-Car SYSC driver needs
to check the exact SoC revision before instantiating a PM Domain for
that power area.
While registering the SoC bus and device, and using soc_device_match(),
from an early_initcall() do work, the "soc" directory and the "soc0"
file end up wrongly in the sysfs root, as the "bus" resp. "devices"
directories haven't been created yet.
To fix this, allow to register a single SoC device early on.
As long as the SoC bus isn't registered, soc_device_match() just
matches against this early device.
When the SoC bus is registered later, the early device is registered for
real.
Note that soc_device_register() returns NULL (no error, but also not a
valid pointer) when registering an early device. Hence platform devices
cannot be instantiated as children of the "soc0" node representing an
early SoC device. This should not be an issue, as that practice has
been deprecated for new platforms.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
If soc_device_match() is called before the SoC bus has been registered,
bus_for_each_dev() returns -EINVAL, which is considered a match, as it
is non-zero.
While calling soc_device_match() too early can be considered an
integration mistake, returning a match is counter-intuitive:
soc_device_match() is typically used to handle quirks, i.e. to deviate
from the default path. Hence add a check to abort checking and return
no match instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add reset lines for the Denali NAND controller on all UniPhier SoCs,
for the Cadence eMMC controller on LD11/LD20 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
It is not really necessary to provide the current .readable_reg
implementation as we know what we're doing in our driver
and the regmap core has already done the partial check for
available maximum regs.
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Actually DOMAIN_INDEX is not used by the client devices to refer to
the power domain, it uses phandle. Corrent the binding doc a bit
to avoid confusing.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Instead of GPC_PGC_PDN_OFFS, naming it as GPC_PGC_CTRL_OFFS which is
defined in reference manual for better reading.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The correct comment should be power up domain.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Commit 721cabf6c6 ("soc: imx: move PGC handling to a new GPC driver")
broke the MX6SL GPC power domain support.
It always got the following error:
[ 1.248364] imx-gpc 20dc000.gpc: could not find pgc DT node
This patch adds back the legecy support.
Fixes: 721cabf6c6 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
ARRAY_SIZE(imx_gpc_domains) represents all power domains supported
by different SoCs. Driver should use SoC specific of_id_data->num_domains
instead to do power domain index sanity check.
e.g. MX6Q supports two power domains while MX6SL supports three.
Fixes: 721cabf6c6 ("soc: imx: move PGC handling to a new GPC driver")
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Without providing the proper reg_defaults, the regmap registers first
read out may be always 0 if enabling cache, which results in the
following issue we met.
e.g. During driver probe in imx6_pm_domain_power_on():
regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
The PGC_PUPSCR register val is always 0 but it's actually 0xf01 in HW.
Since GPC registers are tightly related to CPU bring up and may be
changed in bootloader, we don't want to provide defaults.
And the cache really does not save too much for GPC module.
Therefore, simply disable cache to fix the issue and make life easy.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Fixes: 721cabf6c6 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Olof Johansson
Geert Uytterhoeven
Lucas Stach
Andrey Smirnov
Linus Walleij
Dave Gerlach
Jon Hunter
Paul Gortmaker
Arnd Bergmann
Thierry Reding
Alexey Klimov
Bartlomiej Zolnierkiewicz
Stanimir Varbanov
Rob Clark
Masahiro Yamada
Dong Aisheng