Commit Graph

177 Commits

Author SHA1 Message Date
Thierry Reding c1d676cec5 clk: tegra: Use the proper parent for plld_dsi
The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491eb9 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:22 +02:00
Thierry Reding a84724a1c3 clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
There is no reason why Tegra114 cannot use the same generic code to set
up the oscillator, clk_m and pll_ref clocks. The only effective change
that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but
since these clocks are all fixed it is not needed anyway.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:21 +02:00
Thierry Reding 63cc5a4da1 clk: tegra: Model oscillator as clock
Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.

Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:20 +02:00
Thierry Reding 699b477a0d clk: tegra: Add peripheral registers for bank Y
Tegra210 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:20 +02:00
Thierry Reding 5e43e25917 clk: tegra: Register the proper number of resets
The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Fixes: 6d5b988e7d ("clk: tegra: implement a reset driver")
Cc: stable@vger.kernel.org # 3.14+
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:18 +02:00
Thierry Reding 44a6f3dbf1 clk: tegra: Remove needless initializations
The ret variable is often explicitly initialized to 0, but there is no
need to do so in many cases because it will immediately be overwritten
with the return value from a function.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:18 +02:00
Thierry Reding 12cf33c0eb clk: tegra: Use consistent indentation
Some of the .dev_id entries in the devclks table were oddly indented.
Make them consistent with the rest of the table.

Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:10 +02:00
Thierry Reding 6bb18c532d clk: tegra: Various whitespace cleanups
Make usage of blank lines as separators more consistent.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:03:48 +02:00
Dylan Reid 04794d982e clk: tegra: Enable HDA to HDMI clocks on Tegra124
Add the clocks used for HDMI audio played through the HDA controller.
Initialize the codec clock to 48Mhz and the HDA clock to 102MHz per
the TRM.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:03:47 +02:00
Thierry Reding f081c89606 clk: tegra: Fix a bunch of sparse warnings
The second to last parameter of the TEGRA_CLK_PERIPH macro denotes a
table and should therefore users should pass in NULL instead of 0.

Fixes a bunch of sparse warnings like this:

	warning: Using plain integer as NULL pointer

Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:03:41 +02:00
Thierry Reding 8106462faa clk: tegra: Fix typo tabel -> table
The clock initialization structure is named struct clk_init_table.
Update the kerneldoc comment to use the correct name.

Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:02:08 +02:00
Javier Martinez Canillas 4e907ef6bd clk: Replace explicit clk assignment with __clk_hw_set_clk
The change in the clk API to return a per-user clock instance, moved
the clock state to struct clk_core so now the struct clk_hw .core field
is used instead of .clk for most operations.

So for hardware clocks that needs to share the same clock state, both
the .core and .clk pointers have to be assigned but currently only the
.clk is set. This leads to NULL pointer dereference when the operations
try to access the hw clock .core. For example, the composite clock rate
and mux components didn't have a .core set which leads to this error:

Unable to handle kernel NULL pointer dereference at virtual address 00000034
pgd = c0004000
[00000034] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
task: ee480000 ti: ee488000 task.ti: ee488000
PC is at clk_mux_determine_rate_flags+0x14/0x19c
LR is at __clk_mux_determine_rate+0x24/0x2c
pc : [<c03a355c>]    lr : [<c03a3734>]    psr: a0000113
sp : ee489ce8  ip : ee489d84  fp : ee489d84
r10: 0000005c  r9 : 00000001  r8 : 016e3600
r7 : 00000000  r6 : 00000000  r5 : ee442200  r4 : ee440c98
r3 : ffffffff  r2 : 00000000  r1 : 016e3600  r0 : ee440c98
Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 4000406a  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xee488210)
Stack: (0xee489ce8 to 0xee48a000)
9ce0:                   00000000 ffffffff 60000113 ee440c98 ee442200 00000000
9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84
9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea
9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000
9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84
9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff
9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4
9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700
9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64
9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54
9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0
9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010
9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c
9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000
9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40
9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4
9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944
9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000
9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec
9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424
9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006
9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000
9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000
9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c)
[<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238)
[<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c)
[<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40)
[<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38)
[<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118)
[<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80)
[<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48)
[<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070)
[<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64)
[<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc)
[<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98)
[<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234)
[<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90)
[<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88)
[<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc)
[<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4)
[<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0)
[<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8)
[<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4)
[<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34)
Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034)

The changes were made using the following cocinelle semantic patch:

@i@
@@

@depends on i@
identifier dst;
@@

- dst->clk = hw->clk;
+ __clk_hw_set_clk(dst, hw);

@depends on i@
identifier dst;
@@

- dst->hw.clk = hw->clk;
+ __clk_hw_set_clk(&dst->hw, hw);

Fixes: 035a61c314 ("clk: Make clk API return per-user struct clk instances")
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18 09:40:11 -08:00
Mark Zhang b270491eb9 clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
2015-02-02 16:22:34 +02:00
Paul Walmsley 08acae34e8 clk: tegra: Add support for the Tegra132 CAR IP block
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This
patch mostly deals with the small differences.

Since Tegra132 contains many of the same PLL clock sources used on
Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when
the kernel is configured to include Tegra132 support.

This patch is based on several patches from others:

1. a  patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on
Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for
tegra132").

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Bill Huang <bilhuang@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
2015-02-02 15:47:53 +02:00
Peter De Schrijver d0a57bd5b5 clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37 ("clk: tegra: defer
application of init table") for why that is).  On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
[paul@pwsan.com: tweaked the commit message]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
2015-02-02 15:47:28 +02:00
Tomeu Vizoso ca036b261c clk: tegra: Fix order of arguments in WARN
As previously the names of the present clock and its parent were swapped.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:47:04 +02:00
Sean Paul f892f24b37 clk: tegra124: Add init data for dsi lp clocks
Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:46:34 +02:00
Andrew Bresticker 18abd16376 clk: tegra: SDMMC controllers are on APB
Since the SDMMC controller registers are accessed via the APB,
the APB must be flushed before gating the SDMMC clocks to prevent
register accesses to the SDMMC controllers after their clocks are
gated.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:46:14 +02:00
Thierry Reding 4f4f85fa0b clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-26 09:43:23 +01:00
Tomeu Vizoso b9e742c316 clk: tegra: Make clock initialization more robust
Don't abort clock initialization if we cannot match an entry in
tegra_clk_init_table to a valid entry in the clk array.

Also log a corresponding error message.

This was discovered when testing a patch that removed the EMC clock from
tegra124_clks but left a mention in tegra_clk_init_table.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-09-18 14:56:53 +03:00
Mikko Perttunen 4c495c204f clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
These clocks are used as parents for some EMC timings.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-09-18 13:57:12 +03:00
Linus Torvalds 44c916d58b ARM: SoC cleanups for 3.17
This merge window brings a good size of cleanups on various
 platforms. Among the bigger ones:
 
 * Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have
   lacked active support for quite a while, and after asking around nobody
   showed interest in keeping them around. If needed, they could be
   resurrected in the future but it's more likely that we would prefer
   reintroduction of them as DT and multiplatform-enabled platforms
   instead.
 * OMAP4 controller code register define diet. They defined a lot of registers
   that were never actually used, etc.
 * Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate)
   to drivers/soc so it can be shared with 64-bit code. This also converts them
   over to traditional driver models where possible.
 * Removal of legacy gpio-samsung driver, since the last users have been
   removed (moved to pinctrl)
 
 Plus a bunch of smaller changes for various platforms that sort of
 dissapear in the diffstat for the above. clps711x cleanups, shmobile
 header file refactoring/moves for multiplatform friendliness, some misc
 cleanups, etc.
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Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This merge window brings a good size of cleanups on various platforms.
  Among the bigger ones:

   - Removal of Samsung s5pc100 and s5p64xx platforms.  Both of these
     have lacked active support for quite a while, and after asking
     around nobody showed interest in keeping them around.  If needed,
     they could be resurrected in the future but it's more likely that
     we would prefer reintroduction of them as DT and
     multiplatform-enabled platforms instead.

   - OMAP4 controller code register define diet.  They defined a lot of
     registers that were never actually used, etc.

   - Move of some of the Tegra platform code (PMC, APBIO, fuse,
     powergate) to drivers/soc so it can be shared with 64-bit code.
     This also converts them over to traditional driver models where
     possible.

   - Removal of legacy gpio-samsung driver, since the last users have
     been removed (moved to pinctrl)

  Plus a bunch of smaller changes for various platforms that sort of
  dissapear in the diffstat for the above.  clps711x cleanups, shmobile
  header file refactoring/moves for multiplatform friendliness, some
  misc cleanups, etc"

* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
  drivers: CCI: Correct use of ! and &
  video: clcd-versatile: Depend on ARM
  video: fix up versatile CLCD helper move
  MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
  ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
  MAINTAINERS: Remove Kirkwood
  ARM: tegra: Convert PMC to a driver
  soc/tegra: fuse: Set up in early initcall
  ARM: tegra: Always lock the CPU reset vector
  ARM: tegra: Setup CPU hotplug in a pure initcall
  soc/tegra: Implement runtime check for Tegra SoCs
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ARM: tegra: move fuse exports to soc/tegra/fuse.h
  ARM: tegra: export apb dma readl/writel
  ARM: tegra: Use a function to get the chip ID
  ARM: tegra: Sort includes alphabetically
  ARM: tegra: Move includes to include/soc/tegra
  ...
2014-08-08 11:00:26 -07:00
Thierry Reding 7232398abc ARM: tegra: Convert PMC to a driver
This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 14:58:43 +02:00
Thierry Reding 306a7f9139 ARM: tegra: Move includes to include/soc/tegra
In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 13:26:47 +02:00
Mikko Perttunen 0e548d50b9 clk: tegra: Use XUSB-compatible SATA PLL sequence
Use a sequence for enabling hardware control of the SATA PLL
that works both when using the SATA lane with SATA and when
using it with XUSB.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-07-08 11:29:55 +03:00
Peter De Schrijver 9f0030c8ad clk: tegra: export clock names for debugging
When writing a module for testing or debugging purposes, there is no way to
get hold of clk handles. This patch solves this by exposing all valid clocks
as clkdev's for the virtual device tegra-clk-debug.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-30 16:51:45 +03:00
Peter De Schrijver 0a7eec7f59 clk: tegra124: init table updates
Ensure some clocks critical for system operation are always. Also enable csite
for JTAG debugging and set the tsensor and soc_therm clock frequencies for the
upcoming soctherm driver.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-27 16:21:44 +03:00
Mikko Perttunen cb44cc2f48 clk: tegra: Add SATA clocks to Tegra124 initialization table
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-25 19:12:39 +03:00
Mikko Perttunen 37ab366251 clk: tegra: Enable hardware control of SATA PLL
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-25 19:12:32 +03:00
Peter De Schrijver 167d5366c4 clk: tegra: fix vi_sensor clocks on Tegra124
vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by
correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock
from its own data. Tegra124 was also using the wrong internal clock id.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-25 18:40:07 +03:00
Mike Turquette 4c8f806251 Merge branch 'clk-fixes' into clk-next 2014-05-28 00:15:10 -07:00
Mike Turquette 5178438041 PLLE fixes for 3.15
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Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes

PLLE fixes for 3.15
2014-05-27 21:11:08 -07:00
Andrew Bresticker 4a7f10d67b clk: tegra: Initialize xusb clocks
Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22 22:14:52 -07:00
Andrew Bresticker 5c992afcf8 clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22 22:14:52 -07:00
Jim Lin 9d61707b1f clk: tegra: Fix xusb_fs_src mux
The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22 22:14:52 -07:00
Jim Lin 2cfe16748b clk: tegra: Enable hardware control of PLLE
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable
controls when enabling PLLE.  The hardware (e.g. XUSB) using PLLE
will use these controls for power-saving optimizations.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22 22:14:51 -07:00
Tuomas Tynkkynen d2c834abe2 clk: tegra: Fix wrong value written to PLLE_AUX
The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Cc: stable@vger.kernel.org
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved changelog]
2014-05-16 15:49:23 -07:00
Stephen Warren 9ba7170570 clk: tegra: remove non-existent clocks
The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-04-24 15:36:50 +02:00
Thierry Reding 4ccc402ece clk: tegra: Fix enabling of PLLE
When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17 14:12:46 +03:00
Thierry Reding c61e4e75b9 clk: tegra: Introduce divider mask and shift helpers
Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the
code that modifies the m-, n- and p-divider fields of PLLs shorter and
easier to read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17 14:12:40 +03:00
Thierry Reding d0f02ce3b1 clk: tegra: Fix PLLE programming
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-04-17 14:12:34 +03:00
Mike Turquette ad077ceb8a Merge branch 'clk-fixes' into clk-next 2014-02-24 23:07:53 -08:00
Sachin Kamat 22e5de816b clk: tegra: Staticize tegra_clk_periph_no_gate_ops
tegra_clk_periph_no_gate_ops is a local symbol.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23 14:46:05 -08:00
Peter De Schrijver c7fbd41584 clk: tegra124: remove gr2d and gr3d clocks
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20 19:10:58 +02:00
Peter De Schrijver a9952a76bc clk: tegra: Fix vic03 mux index
The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20 10:45:28 +02:00
Andrew Bresticker 3de5bdfb4c clk: tegra: use max divider if divider overflows
When requesting a rate less than the minimum clock rate for a divider,
use the maximum divider value instead of bailing out with an error.
This matches the behavior of the generic clock divider.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:34 +02:00
Andrew Bresticker 88b4bd7071 clk: tegra: cclk_lp has a pllx/2 divider
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:28 +02:00
Andrew Bresticker 20e7c323ab clk: tegra: fix sdmmc clks on Tegra1x4
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents.  Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:23 +02:00
Mark Zhang 82ba1c3c99 clk: tegra: fix host1x clock on Tegra124
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:16 +02:00
David Ung 0e766c2d9f clk: tegra: PLLD2 fixes for hdmi
Set correct pll_d2_out0 divider and correct the p div values for pll_d2.

Signed-off-by: David Ung <davidu@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:11 +02:00