This patch registers the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for
the exynos platform and avoid using unnecessary calibrated
jiffies. This change has been tested on exynos5420 based board and
udelay is very close to expected.
Without this patch udelay() on exynos5400 / exynos5800 is wildly
inaccurate due to big.LITTLE not adjusting loops_per_jiffy correctly.
Also without this patch udelay() on exynos5250 can be innacruate
during transitions between frequencies < 800 MHz (you'll go 200 MHz ->
800 MHz -> 300 MHz and will run at 800 MHz for a time with the wrong
loops_per_jiffy).
[dianders: reworked and created version 3]
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock. We properly marked
exynos4_read_sched_clock() as notrace. However, we then went and
called another function that _wasn't_ notrace. That means if you do:
cd /sys/kernel/debug/tracing/
echo function_graph > current_tracer
You'll get a crash.
Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function. It's important to keep other users of MCT
traceable because the MCT is actually quite slow to access and we want
exynos4_frc_read() to show up in ftrace profiles if it's the
bottleneck.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Unfortunately on some exynos systems, resetting the mct counter also
resets the architected timer counter. This can cause problems if the
architected timer driver has already been initialized because the kernel
will think that the counter has wrapped around, causing a big jump in
printk timestamps and delaying any scheduled clock events until the
counter reaches the value it had before it was reset.
The kernel code makes no assumptions about the initial value of the mct
counter so there is no reason from a software perspective to clear the
counter before starting it. This also fixes the problems described in
the previous paragraph.
Cc: Olof Johansson <olof@lixom.net>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Pull timer core updates from Thomas Gleixner:
"This time you get nothing really exciting:
- A huge update to the sh* clocksource drivers
- Support for two more ARM SoCs
- Removal of the deprecated setup_sched_clock() API
- The usual pile of fixlets all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
clocksource: Add Freescale FlexTimer Module (FTM) timer support
ARM: dts: vf610: Add Freescale FlexTimer Module timer node.
clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation
clocksource: sh_tmu: Remove unnecessary OOM messages
clocksource: sh_mtu2: Remove unnecessary OOM messages
clocksource: sh_cmt: Remove unnecessary OOM messages
clocksource: em_sti: Remove unnecessary OOM messages
clocksource: dw_apb_timer_of: Do not trace read_sched_clock
clocksource: Fix clocksource_mmio_readX_down
clocksource: Fix type confusion for clocksource_mmio_readX_Y
clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
clocksource: qcom: Implement read_current_timer for udelay
ntp: Make is_error_status() use its argument
ntp: Convert simple_strtol to kstrtol
timer_stats/doc: Fix /proc/timer_stats documentation
sched_clock: Remove deprecated setup_sched_clock() API
ARM: sun6i: a31: Add support for the High Speed Timers
clocksource: sun5i: Add support for reset controller
clocksource: efm32: use $vendor,$device scheme for compatible string
KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform
...
- Another round of clean-up of FDT related code in architecture code.
This removes knowledge of internal FDT details from most architectures
except powerpc.
- Conversion of kernel's custom FDT parsing code to use libfdt.
- DT based initialization for generic serial earlycon. The introduction
of generic serial earlycon support went in thru tty tree.
- Improve the platform device naming for DT probed devices to ensure
unique naming and use parent names instead of a global index.
- Fix a race condition in of_update_property.
- Unify the various linker section OF match tables and fix several
function prototype errors.
- Update platform_get_irq_byname to work in deferred probe cases.
- 2 binding doc updates
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTjzgyAAoJEMhvYp4jgsXiFsUH/1PMTGo8CyD62VQD5ZKdAoW+
Fq6vCiRQ8assF5i5ZLcW1DqhjtoRaCKYhVbRKa5lj7cZdjlSpacI/qQPrF5Br2Ii
bTE3Ff/AQwipQaz/Bj7HqJCgGwfWK8xdfgW0abKsyXMWDN86Bov/zzeu8apmws0x
H1XjJRgnc/rzM4m9ny6+lss0iq6YL54SuTYNzHR33+Ywxls69SfHXIhCW0KpZcBl
5U3YUOomt40GfO46sxFA4xApAhypEK4oVq7asyiA2ArTZ/c2Pkc9p5CBqzhDLmlq
yioWTwHIISv0q+yMLCuQrVGIsbUDkQyy7RQ15z6U+/e/iGO/M+j3A5yxMc3qOi4=
=Onff
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next
Pull DeviceTree updates from Rob Herring:
- Another round of clean-up of FDT related code in architecture code.
This removes knowledge of internal FDT details from most
architectures except powerpc.
- Conversion of kernel's custom FDT parsing code to use libfdt.
- DT based initialization for generic serial earlycon. The
introduction of generic serial earlycon support went in through the
tty tree.
- Improve the platform device naming for DT probed devices to ensure
unique naming and use parent names instead of a global index.
- Fix a race condition in of_update_property.
- Unify the various linker section OF match tables and fix several
function prototype errors.
- Update platform_get_irq_byname to work in deferred probe cases.
- 2 binding doc updates
* tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits)
of: handle NULL node in next_child iterators
of/irq: provide more wrappers for !CONFIG_OF
devicetree: bindings: Document micrel vendor prefix
dt: bindings: dwc2: fix required value for the phy-names property
of_pci_irq: kill useless variable in of_irq_parse_pci()
of/irq: do irq resolution in platform_get_irq_byname()
of: Add a testcase for of_find_node_by_path()
of: Make of_find_node_by_path() handle /aliases
of: Create unlocked version of for_each_child_of_node()
lib: add glibc style strchrnul() variant
of: Handle memory@0 node on PPC32 only
pci/of: Remove dead code
of: fix race between search and remove in of_update_property()
of: Use NULL for pointers
of: Stop naming platform_device using dcr address
of: Ensure unique names without sacrificing determinism
tty/serial: pl011: add DT based earlycon support
of/fdt: add FDT serial scanning for earlycon
of/fdt: add FDT address translation support
serial: earlycon: add DT support
...
The newly merged versatile sched clock support uses a deprecated
interface. Of course that patch got routed through the ARM tree instead
of going through the relevant maintainer tree.
Use the proper interface so we can get rid of the cruft.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
SoC-near driver changes that we're merging through our tree. Mostly
because they depend on other changes we have staged, but in some cases
because the driver maintainers preferred that we did it this way.
This contains a largeish cleanup series of the omap_l3_noc bus driver,
cpuidle rework for Exynos, some reset driver conversions and a long
branch of TI EDMA fixes and cleanups, with more to come next release.
The TI EDMA cleanups is a shared branch with the dmaengine tree, with
a handful of Davinci-specific fixes on top.
After discussion at last year's KS (and some more on the mailing lists),
we are here adding a drivers/soc directory. The purpose of this is
to keep per-vendor shared code that's needed by different drivers but
that doesn't fit into the MFD (nor drivers/platform) model. We expect
to keep merging contents for this hierarchy through arm-soc so we can
keep an eye on what the vendors keep adding here and not making it a
free-for-all to shove in crazy stuff.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTjOFiAAoJEIwa5zzehBx30RYP/0UE+R8ccdsodunmIDrmQ7QP
qFWe1YTWlyXtGBDaPCNfdcU09UYatPKuCv5dJ2ToQCyyFI26PIIhFtnCNXmMuYz+
XPCuqAlJ9hZWx7+j2hXRlyhoZMAaJ5EVVxaK5tnVYXDIfy1Y3xG7i069HD/qGrQp
xrV+XofFmpU2VAds6S+SpecFFfYD7n/pJ1bTSgzPfaUsEUyV882dJ3skgs1VpTzQ
PnL/0Z2t4ePoP3+6p+F7EnJxemLF5IXrlL0c7hODxQKuMqlzoUluywh6SwOHfCQL
u2cc5SFUbbKhExwlGOVibdQMiC0HUOXyRvyYFOIdbv+xNH+Zc/tcoQQ22PWm4Yy1
08qOm3Fr6yw5nH5IT+1wCIFCzJEC/ZHM5B2t+RISFybAMk6Bg1TDYJLmd570zkEL
aTLtS5hdmy4h8Ad5FBtwKNyL//6FJJxhbHUu/m0qaE0phq94+78B2M6vbx6757xC
kCFlpJsHoN0Tn5c9Q1hpTqI/BHxb4UR7Nf+b8Ox8Veuc9JrS35lzi/rWnGxB5WB0
+1KCA8eih9KXTtksxAte1TmSbMciqW559RUR7dNAPXAMPksY2mJV1I+rg0cRsY3i
F90Lnc6LWUM5PYpc4VwiC0sUCLKzTFnpZUELqMOiws3PUblbb0StXuoNo6owbtsK
mp1Juxi1n7VhoN9AFVpL
=SC+e
-----END PGP SIGNATURE-----
Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC driver changes from Olof Johansson:
"SoC-near driver changes that we're merging through our tree. Mostly
because they depend on other changes we have staged, but in some cases
because the driver maintainers preferred that we did it this way.
This contains a largeish cleanup series of the omap_l3_noc bus driver,
cpuidle rework for Exynos, some reset driver conversions and a long
branch of TI EDMA fixes and cleanups, with more to come next release.
The TI EDMA cleanups is a shared branch with the dmaengine tree, with
a handful of Davinci-specific fixes on top.
After discussion at last year's KS (and some more on the mailing
lists), we are here adding a drivers/soc directory. The purpose of
this is to keep per-vendor shared code that's needed by different
drivers but that doesn't fit into the MFD (nor drivers/platform)
model. We expect to keep merging contents for this hierarchy through
arm-soc so we can keep an eye on what the vendors keep adding here and
not making it a free-for-all to shove in crazy stuff"
* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
tty: serial: msm: Remove direct access to GSBI
power: reset: keystone-reset: introduce keystone reset driver
Documentation: dt: add bindings for keystone pll control controller
Documentation: dt: add bindings for keystone reset driver
soc: qcom: fix of_device_id table
ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
ARM: EXYNOS: Move the driver to drivers/cpuidle directory
ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
ARM: EXYNOS: Pass the AFTR callback to the platform_data
ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
ARM: EXYNOS: Move the AFTR state function into pm.c
ARM: EXYNOS: Encapsulate the AFTR code into a function
ARM: EXYNOS: Disable cpuidle for exynos5440
ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
ARM: EXYNOS: Remove ifdef for scu_enable in pm
ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
ARM: EXYNOS: Use the cpu_pm notifier for pm
...
The bulk of this branch is updates for Renesas Shmobile. They are still
doing some enablement for classic boards first, and then come up with DT
bindings when they've had a chance to learn more about the hardware. Not
necessarily a bad way to go about it, and they're looking at moving some
of the temporary board code resulting from it to drivers/staging instead
to avoid the churn here.
As a result of the shmobile clock cleanups, we end up merging quite a
bit of SH code here as well. We ended up merging it here instead of in
the cleanup branch due to the other board changes depending on it.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTjNClAAoJEIwa5zzehBx3Q7wP+wYzWTAU0+3BnnjJpQM79hsX
1hP89RaM6DEyTf6PiL/AKOHsnDponUhNzZu1W5FvNG6cFVenh/nxbmO65FKX9CrY
Ap2pkQW+/IcpmIKZ+Hln2bkCc54a6yPouK+5pd9W14X5TtqNmLbdh1qhoq9UjFTo
zgLfhch5tyNqfpNOj0vFsmvTw0ZGJ0Neq6olRqQbXmyAaRaWzDa64lmEKVupMdk7
2Fh/8jeXlVlryi7p7CvNoAmZEMm7+We5ZMVsQXLk8b9zcwuCWK0DZzNW4DnRCB1d
lsNM/Sygi3Y5zRj2XogNANVhNDIih0f50FX7uuKtmevWNJE9n4To7uFUMTk/3zBt
1hvJLL8w4WHhzkg5v5nFsiCTx65pFaTD/LocPj8lhQ1AYzUvWN5sKPxW0uC1lvJ9
Unlwdc0C4EWs3yq6hAPUZS2eB7owmzNUWdjdkgKfdc74u5RnRay0pUmbRMJm2l20
OKoDSwaluQZUeHrxPnTSLdgpkBbPRn9M5DbswEQsuPyI6yROgCRxaRQ4XcpM93dV
4obCF+fOvX6dtsdIUBCtdhvmJ/iHqhQlPLc2avpt2gyti7eWjQkt5it12hjjOF6A
DVBdNHv215EEgvB0MbPJvFVKBLw4boxdeBx+FqMQCqvAbqefHo4gcQZcsUGAv/pX
zJ8jgkYhlt7XTd+6GlJu
=lWof
-----END PGP SIGNATURE-----
Merge tag 'boards-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC board support updates from Olof Johansson:
"The bulk of this branch is updates for Renesas Shmobile. They are
still doing some enablement for classic boards first, and then come up
with DT bindings when they've had a chance to learn more about the
hardware. Not necessarily a bad way to go about it, and they're
looking at moving some of the temporary board code resulting from it
to drivers/staging instead to avoid the churn here.
As a result of the shmobile clock cleanups, we end up merging quite a
bit of SH code here as well. We ended up merging it here instead of
in the cleanup branch due to the other board changes depending on it"
* tag 'boards-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (130 commits)
ARM: davinci: remove checks for CONFIG_USB_MUSB_PERIPHERAL
ARM: add drivers for Colibri T30 to multi_v7_defconfig
ARM: shmobile: Remove Genmai reference DTS
ARM: shmobile: Let Genmai multiplatform boot with Genmai DTB
ARM: shmobile: Sync Genmai DTS with Genmai reference DTS
ARM: shmobile: genmai-reference: Remove legacy clock support
ARM: shmobile: Remove non-multiplatform Genmai reference support
ARM: configs: enable XHCI mvebu support in multi_v7_defconfig
ARM: OMAP: replace checks for CONFIG_USB_GADGET_OMAP
ARM: OMAP: AM3517EVM: remove check for CONFIG_PANEL_SHARP_LQ043T1DG01
ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
ARM: OMAP: remove some dead code
ARM: OMAP: omap3stalker: remove two Kconfig macros
ARM: tegra: tegra_defconfig updates
ARM: shmobile: r7s72100: use workaround for non DT-clocks
ARM: shmobile: Add forward declaration of struct clk to silence warning
ARM: shmobile: r7s72100: remove SPI DT clocks from legacy clock support
ARM: shmobile: r7s72100: add spi clocks to dtsi
ARM: shmobile: r7s72100: remove I2C DT clocks from legacy clock support
ARM: shmobile: r7s72100: add i2c clocks to dtsi
...
A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support for
big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation and
moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as most
of the other v7 platforms in the tree. \o/ The work isn't quite complete,
there's some driver fixes still needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
Plus a large set of various smaller updates for different platforms. I'm
probably missing some important one here.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTjOKWAAoJEIwa5zzehBx36aEP/2vTD7x9FC59FACNHJ8iO7aw
0ebTgBBjI1Np6X18O+M7URbxV5TaBgwpUm/NDN86p03MpQ2eOXr8r47qVxe/HhZs
AdlTvzgE6QwxcVL/HeCKKUEN3BPH74+TZgFl9I5aSzNjpR39xETeK1aWP/ZiAl/q
/lGRZAQ59+c7Ung00Hg0g2YDxH9WFpK50Nj90ROnyjKSFkhIYngXYVpZB3maOypq
Pgib/U8IraKZ52oGJw3yinSoORr7FdcUdAGWGTz/lQdNL/jYDfQ6GkRW2oblWXdt
3Xvj9UW6NmkbMICucMvFuuW1nXAgutZuTp9w7mBxsiUlYepxPv/DXM6yiI1WGlEb
BeVOmOreNeN2nT6avv/uUhk3Osq63Jn9x8cz5y+7/lgWQwllh3/c+G01RotvgJEQ
vpQq5ps9fMxIAMaNP6N/YqMJI1IOrBj0iXxaZEDw3VYM/k4lSvtb3VXP9c/rqApu
U4i6hpSIGzrraU4NrjndYPndcLeNOVZbByETQKosZXuCo6G1sb7FstNSkzI9vSo8
O/pujIVUfYyBW82GzZGDw+aa7DWA29FPeUQ3p+sj5MSCg051xXT8h6QwqMo2K/zY
5ATs/qo6w7zH/Ou9rtHTRynCIb0GQJThDSlWtuXFedUF9quEltS+TDz/2o+dWtGJ
yBFGKDRuBB20D36w9xqg
=6LYI
-----END PGP SIGNATURE-----
Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull part one of ARM SoC updates from Olof Johansson:
"A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support
for big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation
and moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as
most of the other v7 platforms in the tree. \o/
The work isn't quite complete, there's some driver fixes still
needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
plus a large set of various smaller updates for different platforms.
I'm probably missing some important one here"
* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
ARM: exynos: don't run exynos4 l2x0 setup on other platforms
ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
ARM: EXYNOS: mcpm rename the power_down_finish
ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
ARM: EXYNOS: Enable multi-platform build support
ARM: EXYNOS: Consolidate Kconfig entries
ARM: EXYNOS: Add support for EXYNOS5410 SoC
ARM: EXYNOS: Support secondary CPU boot of Exynos3250
ARM: EXYNOS: Add Exynos3250 SoC ID
ARM: EXYNOS: Add 5800 SoC support
ARM: EXYNOS: initial board support for exynos5260 SoC
clk: exynos5410: register clocks using common clock framework
ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
ARM: sunxi: allow building without reset controller
Documentation: devicetree: arm: sort enable-method entries
ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
...
Cleanups for 3.16. Among these are:
- A bunch of misc cleanups for Broadcom platforms, mostly housekeeping
- Enabling Common Clock Framework on the older s3c24xx Samsung chipsets
- Cleanup of the Versatile Express system controller code, moving it to syscon
- Power management cleanups for OMAP platforms
+ a handful of other cleanups across the place
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTjMwHAAoJEIwa5zzehBx3MjMP/iELgDsqbNE2wxF9Fb5EEnoe
S11q1QIvVrMVdMcKFN5HfW7f+xNso6+4SwXW0cRrJokGvaqRE758WZWuZq0QBUeS
RYMhfpqmI6pTTJUyy6i6OyXhuRqu8rQ1NPEAatYrKzmtwFX1H4t25f1YtZWhBcK8
ONi45FHeH1OKGGpjpT63uhWEzLk+LZI2MtgxmWoFcemf7guX6vEPJVuVRi8eqLoS
9vl1cAkweYgGhjvQFcSXENaguV50dZlLc9C41dJk9KVvJfRt7o+/cRbG5YpGvnp5
Liu+OWM72w0BkgNk6wDN4kaPX5UGLF8QX11JlvDRCJ2FcPtM4NBG/C9TqLMfkKDR
Ze+ITiXh6NjefdTZWJaM4vzsd6vFws8EYAP24IWFlZ451bNLVN1lzlgqluPNoKmj
CAsFPZhY/x5X9a8VLZ72ohx3N17T/iMsOlbiWtnlfqDcL6N0IoLG1YkFFeQIKEAH
mpobWus8Myq1miWqSaeXh5wOqUVQmYR0I8jNoTfte1nBYSaIGhtMixoQhM6Zw50C
dgSh4p7qhrZUOnYmkPqFXr7NCJ9n3RD10Xu8d/3IIp0u9RJ5Kx6NCEg9adq22jZQ
XGrr/vH0sM8MzpKmfTMi5t2Cx5kP2G+O3enq0hQi4x3Cb4o8vwWQlMgydTd+xBjj
aLo3WTTw0h6nTuKkZL2p
=wuX4
-----END PGP SIGNATURE-----
Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC cleanups from Olof Johansson:
"Cleanups for 3.16. Among these are:
- a bunch of misc cleanups for Broadcom platforms, mostly
housekeeping
- enabling Common Clock Framework on the older s3c24xx Samsung
chipsets
- cleanup of the Versatile Express system controller code, moving it
to syscon
- power management cleanups for OMAP platforms
plus a handful of other cleanups across the place"
* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
clk: samsung: fix build error
ARM: vexpress: refine dependencies for new code
clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
cpufreq: exynos: Fix the compile error
ARM: S3C24XX: move debug-macro.S into the common space
ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
ARM: S3C24XX: trim down debug uart handling
ARM: compressed/head.S: remove s3c24xx special case
ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
ARM: EXYNOS: Remove exynos_subsys registration
ARM: EXYNOS: Remove duplicate lines in Makefile
ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
ARM: OMAP2+: PRCM: cleanup some header includes
...
- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iEYEABECAAYFAlOCxdwACgkQykllyylKDCEydwCglWoRgU1kvPH6oqyH5esHv7L3
oY4AnA+t3msa91ovFFbsCm2xW77QbbC6
=Ubf9
-----END PGP SIGNATURE-----
Merge tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx into next/soc
Merge "Xilinx Zynq changes for v3.16" from Michal Simek:
arm: Xilinx Zynq cleanup patches for v3.16
- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console
* tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Enable big-endian
ARM: zynq: Fix uart0 early console virtual address
clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
ARM: zynq: Sort Kconfig options
ARM: zynq: Add support for SOC_BUS
Signed-off-by: Olof Johansson <olof@lixom.net>
The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.
This patch tries to rectify that:
* the mach-vexpress code cannot link without the syscfg driver,
which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
use modern timekeeping but rely on gettimeoffset.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.
CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.
Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
We do not need to trace read_sched_clock function,
so add notrace attribute for this function.
Signed-off-by: Yang Wei <Wei.Yang@windriver.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
For some clocksource devices, for example, the registers are 32-bit, while
the lower 16-bit is used for timer counting(And reading the upper 16-bit
will return 0).
For example, when the counter value is 0x00001111, and then the
~readl_relaxed(to_mmio_clksrc(c)->reg) will return the value of 0xFFFFEEEE,
but it should be 0x0000EEEE.
So just using the c->mask to mask the unused bits.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The types' definations are:
o cycle_t -> u64
o readl_relaxed -> u32
o readw_relaxed -> u16
So let clocksource_mmio_readX_Ys return a cast to cycle_t, though
this maybe look reduntant sometimes, it make sense and they will be
more readable and less confusion...
This patch clarifies the functions type and fix it.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
tc_mode() can be called from interrupt context and thus must not call
clk_*prepare*() functions.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
irqchip will reject the affinity set to CPUs which is not online
yet. but in the CPU1 wakeup stage, OS only sets CPU1 to be online
after local timer is set, so that causes the irq_set_affinity not
work. this patch moves to irq_force_affinity() for the low level
boot stage.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
- register sched_clock callback to use clocksource mct-frc
Note that got ack from Daniel
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTeomJAAoJEA0Cl+kVi2xqKa0QAInbU+rQNv/5Kix76fkXAx1X
68BVp3zIyYL76FsbvnfkVxnxcfU6GsBvX22NzgkTWS4IoRcb3wyW9v16mYatMM+u
3CJ8RuR103DQci83gYrsveYQ4SwYAJC5AZgGg898I5AQ4alx8gIxZ1TGX7GPEL6L
cqzBBaAmGlQ7a94+MOeM94oAMKIXRGm36eZA4/aYcB41jy37o/m88duu+4aCX70Q
mDIGOcuMv71CMbn4IMJaIiapi3eOqRvBdJFaWz0ZttJbdHcLpjRO4tdJNkZ4bpxe
KVKOM3OI7VDYvY2Sz6iRbXesX61YxAL+tacBSRT3m6QWa3NAg/Ns6DBEtc+Y/39x
1YZH823BOlJMh1xb4wkw4fpidCzYXBG42eNGLhf14ITjx1Z06ZnxTQSXn0JKqnCK
q3ZWIfmn3ONPp9Z02UN98vGzAUoa8wAcN4j/nlIiyy/cWJHqRVGPIceSk7TWBUXV
9wmShAA5eBx9OhYaIs4SkjL8AMaEO3X6d6tF0ui9c2Ybt4g6f4Cq429qanUZ+7vT
S3EaBi6oBlbLM6MZgDo4ZBGfAgWIQ9SlQ5U0VDvq58WxLuU7R2vzIq7GHl64nnIH
IWw0V1NFWFXgmswkx0FA5e9Me8/acKXydaFzVOvo1SVWbI/kLLjvRIuSm46ufqzY
WyKrrXOwp/av8sq4Ejwb
=w1kR
-----END PGP SIGNATURE-----
Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
Merge "Samsung driver update for 3.16" from Kukjin Kim:
exynos_mct update for v3.16
- register sched_clock callback to use clocksource mct-frc
* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: exynos_mct: register sched_clock callback
Signed-off-by: Olof Johansson <olof@lixom.net>
This series reworks VE's platform configuration infrastructure by:
- making it possible to instantiate selected devices from the
Device Tree, prior to massive population,
- converting custom "func" API into standard "regmap",
- splitting the existing MFD driver into smaller ones and placing
them into relevant directories.
The common clock framework driver can now be selected individually
(mostly for arm64 sake, where some of them are not used at all).
It also simplifies the machine code, by:
- moving the shed clock info clocksource driver,
- simplifying SMP operations to base them entirely of the DT data,
- moving platform ID checks into relevant driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTdPALAAoJEL9jRaJfXa5PkwIH/1x/yvJ+LBCTP7Dx5a8X0ZBJ
PIVxj2ynUbdFBWywMOuEh3YIPC6xrKFGVB2+u6ZnBiPTBgS1UVc3OoLb5HbKiq2I
IgnTv/etcuDrn5gVXPnmUJNVXNbDCspyT6YTaO8xZm81MTOB+QwJHh0wbaY9BXHO
qnpPpIowfb53X1DiZ4Uo5sXpcJdXih2C+pJ8AQLIDLdGGiIg9loa1s2fJkChyPi3
4xmx8JtcRXEeiWPtxb5fQ2mT0tTRMFUMqH7LSKTSTKsLBaMmFQq6H/W/Wc7auTQC
ZGZuZpChJFkrH20mc6RqUu3XObZaeD9O9hzP0V8RlnJI3gVN81OT0DOcKQjMiNI=
=3R6A
-----END PGP SIGNATURE-----
Merge tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux into next/cleanup
Merge "ARM Versatile Express updates for 3.16" from Pawel Moll:
This series reworks VE's platform configuration infrastructure by:
- making it possible to instantiate selected devices from the
Device Tree, prior to massive population,
- converting custom "func" API into standard "regmap",
- splitting the existing MFD driver into smaller ones and placing
them into relevant directories.
The common clock framework driver can now be selected individually
(mostly for arm64 sake, where some of them are not used at all).
It also simplifies the machine code, by:
- moving the shed clock info clocksource driver,
- simplifying SMP operations to base them entirely of the DT data,
- moving platform ID checks into relevant driver.
* tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux:
ARM: vexpress: move HBI check to sysreg driver
ARM: vexpress: Simplify SMP operations for DT-powered system
ARM: vexpress: remove redundant vexpress_dt_cpus_num to get cpu count
clocksource: Sched clock source for Versatile Express
clk: versatile: Split config options for sp810 and vexpress_osc
mfd: vexpress: Define the device as MFD cells
mfd: syscon: Add platform data with a regmap config name
mfd: vexpress: Convert custom func API to regmap
of: Keep track of populated platform devices
+ Linux 3.15-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Bringing in as an external dependency that the renesas/clock-cleanup2 branch
relies on.
* depends/clockevents-cleanups: (52 commits)
clocksource: sh_mtu2: Sort headers alphabetically
clocksource: sh_mtu2: Remove FSF mail address from GPL notice
clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy case
clocksource: sh_mtu2: Add support for multiple channels per device
clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200
clocksource: sh_mtu2: Set cpumask to cpu_possible_mask
clocksource: sh_mtu2: Replace hardcoded register values with macros
clocksource: sh_mtu2: Allocate channels dynamically
clocksource: sh_mtu2: Replace kmalloc + memset with kzalloc
clocksource: sh_mtu2: Add index to struct sh_mtu2_channel
clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure
clocksource: sh_mtu2: Constify name argument to sh_mtu2_register()
clocksource: sh_mtu2: Split channel setup to separate function
clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_device
clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv
clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables
clocksource: sh_mtu2: Use request_irq() instead of setup_irq()
clocksource: sh_tmu: Sort headers alphabetically
clocksource: sh_tmu: Remove FSF mail address from GPL notice
clocksource: sh_tmu: Rename clock to "fck" in the non-legacy case
...
Signed-off-by: Olof Johansson <olof@lixom.net>
We now have several OF match tables using linker sections that are
nearly the same definition. The only variation is the callback function
prototype. Create a common define for creating linker section OF match
table entries which each table declaration can use.
Acked-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.
Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In the legacy platform data case each TMU platform device handles a
single channel with a single IRQ for the platform device. Retrieve the
IRQ using the logical channel number instead of the hardware channel
number.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch adds a trival sched clock source using free
running, 24MHz clocked counter present in the ARM Ltd.
reference platforms (Versatile, RealView, Versatile
Express) System Registers block.
This code replaces the call in the VE machine code.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Nobody want to know the connection between io clk and timer clk,
so exposing this information to timer module is not reasonable.
this patch moves to define the timers' clk in dt.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Use the clocksource mct-frc for sched_clock
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
clockevent fixes for 3.15 from Daniel Lezcano:
* Lorenzo Pieralizi fixed an issue with the arch_arm_timer where the
C3STOP flag for all the arch can cause some trouble by setting the
flag only if the power domain is not always on
* Alexander Shiyan fixed a compilation by changing the init function
to the right prototype
CC drivers/clocksource/zevio-timer.o
drivers/clocksource/zevio-timer.c:215:1: warning: comparison of distinct pointer types lacks a cast [enabled by default]
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
ARM arch timers are tightly coupled with the CPU logic and lose context
on platform implementing HW power management when cores are powered
down at run-time. Marking the arch timers as C3STOP regardless of power
management capabilities causes issues on platforms with no power management,
since in that case the arch timers cannot possibly enter states where the
timer loses context at runtime and therefore can always be used as a high
resolution clockevent device.
In order to fix the C3STOP issue in a way compliant with how real HW
works, this patch adds a boolean property to the arch timer bindings
to define if the arch timer is managed by an always-on power domain.
This power domain is present on all ARM platforms to date, and manages
HW that must not be turned off, whatever the state of other HW
components (eg power controller). On platforms with no power management
capabilities, it is the only power domain present, which encompasses
and manages power supply for all HW components in the system.
If the timer is powered by the always-on power domain, the always-on
property must be present in the bindings which means that the timer cannot
be shutdown at runtime, so it is not a C3STOP clockevent device.
If the timer binding does not contain the always-on property, the timer is
assumed to be power-gateable, hence it must be defined as a C3STOP
clockevent device.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch set cleans up the Renesas CMT and TMU drivers in preparation for DT
support.
The first 35 patches are a bunch of necessary cleanups that reorganize the CMT
and TMU drivers, their platform data, and the memory, interrupt and clock
resources they expect. As a result the drivers accept a new platform data
model close to the hardware with supports for all the timer channels using a
single device.
The next 13 patches (36/52 to 48/52) move all CMT and TMU platforms from the
old to the new platform data model. Patches 49/52 to 52/52 then drop support
for the old model and perform one more cleanup.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the
common scheme and prefix device with "efm32-". The old compatible string
is left in place until arch/arm/boot/dts/efm32* is fixed.
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The check for a usable global timer in the probe code does not enquire
which CPU we are currently running on. This can cause the driver to
incorrectly assume we have an unusable global timer if we are running
on a CPU other than A9.
Before checking the CPU revision, ensure we are running on an A9 CPU.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
After hotplugging CPU1 the first call of interrupt handler for CPU1
oneshot timer was called on CPU0 because it fired before setting IRQ
affinity. Affected are SoCs where Multi Core Timer interrupts are
shared (SPI), e.g. Exynos 4210.
During setup of the MCT timers the clock event device should be
registered after setting the affinity for interrupt. This will prevent
starting the timer too early.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.299247848@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The starting cpu is not yet in the online mask so irq_set_affinity()
fails which results in per cpu timers for this cpu ending up on some
other online cpu, ususally cpu 0.
Use irq_force_affinity() which disables the online mask check and
makes things work.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.106665251@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This helps locating duplicates and inserting new headers.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The sh_mtu2 driver gets the MTU2 functional clock using a connection ID
of "mtu2_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "mtu2_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.
Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
MTU2 hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_mtu2 driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.
Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.
Support for the legacy model is kept and will be removed after all
platforms switch to the new model.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
All boards use clock event ratings of 200 for the MTU2, hardcode it in
the driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The MTU2 is not tied to CPU0, make it usable on any CPU.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
