Commit Graph

153 Commits

Author SHA1 Message Date
Greg Kroah-Hartman b24413180f License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier.  The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
 - file had no licensing information it it.
 - file was a */uapi/* one with no licensing information in it,
 - file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne.  Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed.  Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
 - Files considered eligible had to be source code files.
 - Make and config files were included as candidates if they contained >5
   lines of source
 - File already had some variant of a license header in it (even if <5
   lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

 - when both scanners couldn't find any license traces, file was
   considered to have no license information in it, and the top level
   COPYING file license applied.

   For non */uapi/* files that summary was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0                                              11139

   and resulted in the first patch in this series.

   If that file was a */uapi/* path one, it was "GPL-2.0 WITH
   Linux-syscall-note" otherwise it was "GPL-2.0".  Results of that was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0 WITH Linux-syscall-note                        930

   and resulted in the second patch in this series.

 - if a file had some form of licensing information in it, and was one
   of the */uapi/* ones, it was denoted with the Linux-syscall-note if
   any GPL family license was found in the file or had no licensing in
   it (per prior point).  Results summary:

   SPDX license identifier                            # files
   ---------------------------------------------------|------
   GPL-2.0 WITH Linux-syscall-note                       270
   GPL-2.0+ WITH Linux-syscall-note                      169
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause)    21
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)    17
   LGPL-2.1+ WITH Linux-syscall-note                      15
   GPL-1.0+ WITH Linux-syscall-note                       14
   ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause)    5
   LGPL-2.0+ WITH Linux-syscall-note                       4
   LGPL-2.1 WITH Linux-syscall-note                        3
   ((GPL-2.0 WITH Linux-syscall-note) OR MIT)              3
   ((GPL-2.0 WITH Linux-syscall-note) AND MIT)             1

   and that resulted in the third patch in this series.

 - when the two scanners agreed on the detected license(s), that became
   the concluded license(s).

 - when there was disagreement between the two scanners (one detected a
   license but the other didn't, or they both detected different
   licenses) a manual inspection of the file occurred.

 - In most cases a manual inspection of the information in the file
   resulted in a clear resolution of the license that should apply (and
   which scanner probably needed to revisit its heuristics).

 - When it was not immediately clear, the license identifier was
   confirmed with lawyers working with the Linux Foundation.

 - If there was any question as to the appropriate license identifier,
   the file was flagged for further research and to be revisited later
   in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights.  The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
 - a full scancode scan run, collecting the matched texts, detected
   license ids and scores
 - reviewing anything where there was a license detected (about 500+
   files) to ensure that the applied SPDX license was correct
 - reviewing anything where there was no detection but the patch license
   was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
   SPDX license was correct

This produced a worksheet with 20 files needing minor correction.  This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg.  Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected.  This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.)  Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-02 11:10:55 +01:00
Linus Torvalds 968c61f7da - New Drivers
- RK805 Power Management IC (PMIC)
    - ROHM BD9571MWV-M MFD Power Management IC (PMIC)
    - Texas Instruments TPS68470 Power Management IC (PMIC) & LEDs
 
  - New Device Support
    - Add support for HiSilicon Hi6421v530 to hi6421-pmic-core
    - Add support for X-Powers AXP806 to axp20x
    - Add support for X-Powers AXP813 to axp20x
    - Add support for Intel Sunrise Point LPSS to intel-lpss-pci
 
  - New Functionality
    - Amend API to provide register layout; atmel-smc
 
 - Fix-ups
    - DT re-work; omap, nokia
    - Header file location change {I2C => MFD}; dm355evm_msp, tps65010
    - Fix chip ID formatting issue(s); rk808
    - Optionally register touchscreen devices; da9052-core
    - Documentation improvements; twl-core
    - Constification; rtsx_pcr, ab8500-core, da9055-i2c, da9052-spi
    - Drop unnecessary static declaration; max8925-i2c
    - Kconfig changes (missing deps and remove module support)
    - Slim down oversized licence statement; hi6421-pmic-core
    - Use managed resources (devm_*); lp87565
    - Supply proper error checking/handling; t7l66xb
 
  - Bug Fixes
    - Fix counter duplication issue; da9052-core
    - Fix potential NULL deference issue; max8998
    - Leave SPI-NOR write-protection bit alone; lpc_ich
    - Ensure device is put into reset during suspend; intel-lpss
    - Correct register offset variable size; omap-usb-tll
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Merge tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Drivers
   - RK805 Power Management IC (PMIC)
   - ROHM BD9571MWV-M MFD Power Management IC (PMIC)
   - Texas Instruments TPS68470 Power Management IC (PMIC) & LEDs

  New Device Support:
   - Add support for HiSilicon Hi6421v530 to hi6421-pmic-core
   - Add support for X-Powers AXP806 to axp20x
   - Add support for X-Powers AXP813 to axp20x
   - Add support for Intel Sunrise Point LPSS to intel-lpss-pci

  New Functionality:
   - Amend API to provide register layout; atmel-smc

  Fix-ups:
   - DT re-work; omap, nokia
   - Header file location change {I2C => MFD}; dm355evm_msp, tps65010
   - Fix chip ID formatting issue(s); rk808
   - Optionally register touchscreen devices; da9052-core
   - Documentation improvements; twl-core
   - Constification; rtsx_pcr, ab8500-core, da9055-i2c, da9052-spi
   - Drop unnecessary static declaration; max8925-i2c
   - Kconfig changes (missing deps and remove module support)
   - Slim down oversized licence statement; hi6421-pmic-core
   - Use managed resources (devm_*); lp87565
   - Supply proper error checking/handling; t7l66xb

  Bug Fixes:
   - Fix counter duplication issue; da9052-core
   - Fix potential NULL deference issue; max8998
   - Leave SPI-NOR write-protection bit alone; lpc_ich
   - Ensure device is put into reset during suspend; intel-lpss
   - Correct register offset variable size; omap-usb-tll"

* tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (61 commits)
  mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants
  mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT
  dt-bindings: mfd: Add bindings for ZII RAVE devices
  mfd: omap-usb-tll: Fix register offsets
  mfd: da9052: Constify spi_device_id
  mfd: intel-lpss: Put I2C and SPI controllers into reset state on suspend
  mfd: da9055: Constify i2c_device_id
  mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices
  mfd: t7l66xb: Handle return value of clk_prepare_enable
  mfd: Add ROHM BD9571MWV-M PMIC DT bindings
  mfd: intel_soc_pmic_chtwc: Turn Kconfig option into a bool
  mfd: lp87565: Convert to use devm_mfd_add_devices()
  mfd: Add support for TPS68470 device
  mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell
  mfd: syscon: atmel-smc: Add helper to retrieve register layout
  mfd: axp20x: Use correct platform device ID for many PEK
  dt-bindings: mfd: axp20x: Introduce bindings for AXP813
  mfd: axp20x: Add support for AXP813 PMIC
  dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips
  mfd: Add ROHM BD9571MWV-M MFD PMIC driver
  ...
2017-09-07 13:51:13 -07:00
Baolin Wang 41d32cfce1 pinctrl: sprd: Add Spreadtrum pin control driver
This patch adds the pin control driver for Spreadtrum SC9860 platform.

Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31 09:23:14 +02:00
Joseph Chen ea479996c7 pinctrl: Add pinctrl driver for the RK805 PMIC
RK805 is one of Rockchip PMICs family, it has 2 output only GPIOs.

This driver is also designed for other Rockchip PMICs to expend.
Different PMIC maybe have different pin features, for example,
RK816 has one pin which can be used for TS or GPIO(input/out).
The mainly difference between PMICs pins are pinmux, direction
and output value, that is 'struct rk805_pin_config'.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-08-21 08:54:46 +01:00
Linus Walleij 06351d133d pinctrl: add a Gemini SoC pin controller
This adds a pin control (only multiplexing) driver for the Gemini
SoC so we can sort out this complex platform in an orderly manner.

This driver will detect the chip/package version as SL3512 or SL3516
(also known as CS3512 and CS3516 etc) and register the apropriate
pin set.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14 15:01:59 +02:00
Linus Walleij df81b9411a pinctrl: sh-pfc: Updates for v4.13 (take two)
- Add SCIF1 and SCIF2 pin groups for R-Car V2H,
   - Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car
     H3 ES2.0,
   - Add pin and gpio controller support for RZ/A1.
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Merge tag 'sh-pfc-for-v4.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.13 (take two)

  - Add SCIF1 and SCIF2 pin groups for R-Car V2H,
  - Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car
    H3 ES2.0,
  - Add pin and gpio controller support for RZ/A1.
2017-06-29 15:05:51 +02:00
Jacopo Mondi 5a49b644b3 pinctrl: Renesas RZ/A1 pin and gpio controller
Add combined gpio and pin controller driver for Renesas RZ/A1
r7s72100 SoC.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-06-23 08:46:52 +02:00
Linus Walleij fe421052b3 Merge branch 'mcp23s08' into devel 2017-05-23 09:52:08 +02:00
Sebastian Reichel 64ac43e6fa gpio: mcp23s08: move to pinctrl
This moves the mcp23s08 driver from gpio to pinctrl. Actual
pinctrl support for configuration of the pull-up resistors
follows in its own patch.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-23 09:45:29 +02:00
Linus Walleij bdb18d93a7 Merge branch 'ingenic' into devel 2017-05-22 17:27:18 +02:00
Paul Cercueil b5c23aa465 pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs
This driver handles pin configuration and pin muxing for the
JZ4740 and JZ4780 SoCs from Ingenic.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-22 17:17:23 +02:00
Shawn Guo cbff0c4d27 pinctrl: add ZTE ZX pinctrl driver support
The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists
of a main controller and an auxiliary one.  For example, on ZX296718 SoC,
the main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both
controllers work together to control pin multiplexing and configuration.

For most of pins, the pinmux function is controlled by main controller
only, and this type of pins are meant by term 'TOP pins'.  For other
pins, the pinmux is controlled by both main and auxiliary controllers,
as the available multiplexing functions for the pin spread in both
controllers.  This type of pins are called 'AON pins'.  Though pinmux
implementation is quite different, pinconf is same for both types of
pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG on
ZX296718.

The patch adds the ZTE ZX core pinctrl driver to support this hybrid
pin controller as well as ZX296718 SoC specific pin data.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-22 10:39:23 +02:00
Gregory CLEMENT 87466ccd94 pinctrl: armada-37xx: Add pin controller support for Armada 37xx
The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).

At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24 11:31:36 +02:00
Jesper Nilsson 00df0582ea pinctrl: Add pincontrol driver for ARTPEC-6 SoC
Add pinctrl driver support for the Axis ARTPEC-6 SoC.
There are only some pins that actually have different
functions available, but all can control bias (pull-up/-down)
and drive strength.

Code originally written by Chris Paterson.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 11:48:33 +02:00
Nishanth Menon 003910ebc8 pinctrl: Introduce TI IOdelay configuration driver
SoC family such as DRA7 family of processors have, in addition
to the regular muxing of pins (as done by pinctrl-single), a separate
hardware module called IODelay which is also expected to be configured.
The "IODelay" module has it's own register space that is independent
of the control module and the padconf register area.

With recent changes to the pinctrl framework, we can now support
this hardware with a reasonably minimal driver by using #pinctrl-cells,
GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay reconfiguration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do as little of muxing as absolutely necessary
without I/O isolation (which can only be done in initial stages of
bootloader).

NOTE: with the system wide I/O isolation scheme present in DRA7 SoC
family, it is not reasonable to do stop all I/O operations for every
such pad configuration scheme. So, we will let it glitch when used in
this mode.

Even with the above limitation, certain functionality such as MMC has
mandatory need for IODelay reconfiguration requirements, depending on
speed of transfer. In these cases, with careful examination of usecase
involved, the expected glitch can be controlled such that it does not
impact functionality.

In short, IODelay module support as a padconf driver being introduced
here is not expected to do SoC wide I/O Isolation and is meant for
a limited subset of IODelay configuration requirements that need to
be dynamic and whose glitchy behavior will not cause functionality
failure for that interface.

IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared
to 0x0 at all times, even when configuring Manual IO Timing Modes.
This is done by eliminating the LOCK_BIT=1 setting from Step
of the Manual IO timing Mode configuration procedure. This option
leaves the CFG_* registers unprotected from unintended writes to the
CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured.

This approach is taken to allow for a generic driver to exist in kernel
world that has to be used carefully in required usecases.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[tony@atomide.com: updated to use generic pinctrl functions, added
 binding documentation, updated comments]
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-09 19:43:21 +01:00
David Lechner 1ff91f0ae3 pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf
This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These
SoCs have a separate controller for controlling pullup/pulldown groups.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:00 +01:00
Neil Armstrong 9e80f9064e pinctrl: Add SX150X GPIO Extender Pinctrl Driver
Since the I2C sx150x GPIO expander driver uses platform_data to manage
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get/set pin configurations from DT or debugfs.

The pinctrl driver is functionnally equivalent as the gpio-only driver
and can use DT for pinconf. The platform_data confirmation is dropped.

This patchset removed the gpio-only driver and selects the Pinctrl driver
config instead. This patchset also migrates the gpio dt-bindings to pinctrl
and add the pinctrl optional properties.

The driver was tested with a SX1509 device on a BeagleBone black with
interrupt support and on an X86_64 machine over an I2C to USB converter.

This is a fixed version that builds and runs on non-OF platforms and on
arm based OF. The GPIO version is removed and the bindings are also moved
to the pinctrl bindings.

Changes since v2
 - rebased on v4.9-rc1
 - removed MODULE_DEVICE_TABLE as in upstream bb411e771b
   ("gpio: sx150x: fix implicit assumption module.h is present")

Changes since v1
 - Fix Kconfig descriptions on pinctrl and gpio
 - Fix Kconfig dependency
 - Remove oscio support for non-789 devices
 - correct typo in dt bindings
 - remove probe reset for non-789 devices

Changes since RFC
 - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
 - No more rely on OF_GPIO config
 - Moved and enhanced bindings to pinctrl bindings
 - Removed gpio-sx150x.c
 - Temporary select PINCTRL_SX150X when GPIO_SX150X
 - Temporary mark GPIO_SX150X as deprecated

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Peter Rosin <peda@axentia.se>
Acked-by: Rob Herring <robh@kernel.org>
ested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:40 +02:00
Andrew Jeffery 4d3d0e4272 pinctrl: Add core support for Aspeed SoCs
The Aspeed SoCs typically provide more than 200 pins for GPIO and other
functions. The signal enabled on a pin is determined on a priority
basis, where a given pin can provide a number of different signal types.

In addition to the priority levels, the Aspeed pin controllers describe
the signal active on a pin by compound logical expressions involving
multiple operators, registers and bits. Some difficulty arises as a
pin's function bit masks for each priority level are frequently not the
same (i.e. we cannot just flip a bit to change from a high to low
priority signal), or even in the same register(s). Some configuration
bits affect multiple pins, while in other cases the signals for a bus
must each be enabled individually.

Together, these features give rise to some complexity in the
implementation. A more complete description of the complexities is
provided in the associated header file.

The patch doesn't implement pinctrl/pinmux/pinconf for any particular
Aspeed SoC, rather it adds the framework for defining pinmux
configurations.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-07 16:48:22 +02:00
Linus Torvalds d94ba9e7d8 This is the bulk of pin control changes for the v4.8 kernel cycle.
New drivers:
 
 - New driver for Oxnas pin control and GPIO. This ARM-based chipset
   is used in a few storage (NAS) type devices.
 
 - New driver for the MAX77620/MAX20024 pin controller portions.
 
 - New driver for the Intel Merrifield pin controller.
 
 New subdrivers:
 
 - New subdriver for the Qualcomm MDM9615
 
 - New subdriver for the STM32F746 MCU
 
 - New subdriver for the Broadcom NSP SoC.
 
 Cleanups:
 
 - Demodularization of bool compiled-in drivers.
 
 Apart from this there is just regular incremental improvements to
 a lot of drivers, especially Uniphier and PFC.
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Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...
2016-07-28 17:06:51 -07:00
Axel Lin 19b5a91764 pinctrl: tegra: Fix build dependency
I got below build error:
ERROR: "tegra_xusb_padctl_legacy_probe"
 [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
with below build configuration:
CONFIG_ARCH_TEGRA=y
CONFIG_PINCTRL_TEGRA_XUSB=y
CONFIG_PHY_TEGRA_XUSB=y

The problem is below line in drivers/pinctrl/Makefile
obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/

So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.

phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 17:58:07 +02:00
Florian Fainelli f886031f65 pinctrl: Always recurse into bcm folder
drivers/pinctrl/bcm/Makefile properly builds individual drivers based on
their respective Kconfig symbols. ARCH_BCM is currently a menuconfig
option from arch/arm/mach-bcm/Kconfig, which is fine, but prevents ARM64
platforms which do not have such menuconfig option from building their
pinctrl drivers, so let's get rid of that dependency.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-13 09:25:31 +02:00
Laxman Dewangan 2df723d49c pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.

Add pin control driver to configure these parameters through
pin control APIs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:47 +02:00
Neil Armstrong 611dac1e48 pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver
Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-30 09:41:45 +02:00
Masahiro Yamada 4a9e00600b pinctrl: mediatek: guard sub-directory with CONFIG_PINCTRL_MTK
CONFIG_PINCTRL_MTK is more suitable than CONFIG_ARCH_MEDIATEK
to guard the drivers/pinctrl/mediatek/ directory.
(I renamed CONFIG_PINCTRL_MTK_COMMON to CONFIG_PINCTRL_MTK.)

This allows COMPILE_TEST to descend into drivers/pinctrl/mediatek
without CONFIG_ARCH_MEDIATEK define.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-13 23:34:19 +01:00
Maxime Coquelin 4afe26845c pinctrl: stm32: Fix compile testing selection
While selecting the driver for compile testing seemed possible,
the driver was not compiled because the driver directory was only
added if ARCH_STM32 was selected.

This patch now makes the pinctrl Makefile to add stm32 directory if
PINCTRL_STM32 is selected.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-09 10:53:35 +01:00
Joshua Henderson 2ba384e6c3 pinctrl: pinctrl-pic32: Add PIC32 pin control driver
Add a driver for the pin controller present on the Microchip PIC32
including the specific variant PIC32MZDA. This driver provides pinmux
and pinconfig operations as well as GPIO and IRQ chips for the GPIO
banks.

Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05 23:54:47 +01:00
Masahiro Yamada 25cbac7716 pinctrl: tegra: move Tegra pinctrl drivers to sub-directory
Tegra has several pinctrl drivers.  Now it is reasonable enough to
move them into drivers/pinctrl/tegra/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05 15:16:43 +01:00
Masahiro Yamada 3a42a042f5 pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXI
CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI
to guard the drivers/pinctrl/sunxi/ directory.
(I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28 14:25:50 +01:00
Masahiro Yamada 64051150c6 pinctrl: pxa: guard sub-directory with CONFIG_PINCTRL_PXA
CONFIG_PINCTRL_PXA is more suitable than CONFIG_ARCH_PXA
to guard the drivers/pinctrl/pxa/ directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28 11:23:51 +01:00
Maxime Coquelin aceb16dc2d pinctrl: Add STM32 MCUs support
This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
family of MCUs.

While it only supports STM32F429 for now, it has been designed to enable
support of other MCUs of the family (e.g. STM32F746).

Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27 14:18:46 +01:00
Robert Jarzmik 4b15ec9d42 pinctrl: activate pxa architecture
As the pxa architecture, at least for pxa27x, supports pin control,
activate it in the pinctrl tree.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10 16:14:03 +01:00
Masahiro Yamada 2f9c2424f6 pinctrl: spear: guard sub-directory with CONFIG_PINCTRL_SPEAR
CONFIG_PINCTRL_SPEAR is more suitable than CONFIG_PLAT_SPEAR
to guard the drivers/pinctrl/spear/ directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-01 10:42:02 +01:00
Masahiro Yamada 973bbcfa17 pinctrl: mvebu: guard sub-directory with CONFIG_PINCTRL_MVEBU
CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION
to guard the drivers/pinctrl/mvebu/ directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-01 10:41:03 +01:00
Masahiro Yamada 1bcb2021d5 pinctrl: berlin: guard sub-directory with CONFIG_PINCTRL_BERLIN
CONFIG_PINCTRL_BERLIN is more suitable than CONFIG_ARCH_BERLIN
to guard the drivers/pinctrl/berlin/ directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-01 10:39:26 +01:00
Masahiro Yamada 241297c2af pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER
CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER
to guard the drivers/pinctrl/uniphier directory.

The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long
(it would break the indentation in drivers/pinctrl/Makefile),
so rename it into CONFIG_PINCTRL_UNIPHIER.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-31 22:13:07 +01:00
Ludovic Desroches 776180848b pinctrl: introduce driver for Atmel PIO4 controller
Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2
chip family.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-09-21 11:21:33 -07:00
Baruch Siach 38b0e5071e pinctrl: driver for Conexant Digicolor CX92755 pin mapping
This adds pinctrl and gpio driver to the CX92755 SoC "General
Purpose Pin Mapping" hardware block. The CX92755 is one SoC
from the Conexant Digicolor series. Pin mapping hardware supports
configuring pins as either GPIO, or up to 3 other "client select"
functions. This driver adds support for pin muxing using the
generic device tree binding, and a basic gpiolib driver for
the GPIO functionality.

This driver does not currently support GPIO interrupts, and
pad configuration.

v2:
* Address review comments for Linus Walleij:
  - Add a pointer to pinctrl_desc in struct dc_pinmap
  - Drop the now redundant pinctrl_pin_desc field
  - Adapt dc_get_group_{name,pins} to these changes, and
    add a comment explaining the 1-to-1 pin-groups relation
* Staticise dc_pmxops
* Protect the GP_CLIENTSEL clct parameter with parenthesis

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-27 11:47:25 +02:00
Masahiro Yamada 95b612cc6c pinctrl: move CONFIG_PINCTRL to drivers/Makefile
Kbuild should descend into drivers/pinctrl/ only when CONFIG_PINCTRL
is enabled because everything under that directory depends on
CONFIG_PINCTRL.

We can avoid the conditional, ifeq ($(CONFIG_OF),y) ... endif.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:40:09 +02:00
Masahiro Yamada 6e90889202 pinctrl: UniPhier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.

Changes in v2:
  - drop vogus THIS_MODULE because this file is always built-in
  - drop vogus "include <linux/module.h> because this file is
    always built-in

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16 09:39:38 +02:00
Andrew Bresticker cefc03e599 pinctrl: Add Pistachio SoC pin control driver
Add a driver for the pin controller present on the IMG Pistachio SoC.
This driver provides pinmux and pinconfig operations as well as GPIO
and IRQ chips for the GPIO banks.

Changes from v4:
 - Switched to using gpiochip_add_pin_range().
 - Fixed up Kconfig entry.
Changes from v3:
 - Addressed review comments from Ezequiel.
Changes from v2:
 - Removed module stuff which would be compiled out.
Changes from v1:
 - Addressed review comments from Linus.
 - Changed compatible string to "img,pistachio-system-pinctrl".
 - Look for GPIO sub-nodes by name.
 - A couple of bug fixes.

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12 13:19:41 +02:00
Joachim Eastwood 2f77ac93a9 pinctrl: add lpc18xx pinctrl driver
Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.

Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06 14:45:18 +02:00
Ken Xue dbad75dd1f pinctrl: add AMD GPIO driver support.
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM.
Current driver patch only support GPIO in x86.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
[Moved back to <linux/gpio.h> header]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:21 +01:00
Hongzhou Yang a6df410d42 pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.

The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.

This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:14 +01:00
Ray Jui b17f2f9b86 pinctrl: bcm: consolidate Broadcom pinctrl drivers
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/*

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:12 +01:00
Stephen Warren 9184f75690 pinctrl: tegra: add a driver for Tegra210
Tegra210's pinmux supports a different set of pins/options than earlier
SoCs, so requires its own driver (well, table of pin-specific data).

Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:59 +01:00
Beniamino Galvani 6ac7309511 pinctrl: add driver for Amlogic Meson SoCs
This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-26 09:13:00 +01:00
Soren Brinkmann add958cee9 pinctrl: Add driver for Zynq
This adds a pin-control driver for Zynq.

Changes since v2:
- driver-specific DT properties are passed to the core in two arrays,
  one for the actual DT parsing one for the debugfs representation.
  Issue a compiler warning when the number of entries is not the same
  for both arrays.

Changes since v1:
 - fix EMIO_SD1_CD pin name
 - add USB to pinmux options

changes since RFCv2:
 - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
   present in DT but no driver available.
 - add #defines to get rid of magical constants
 - add commas at end of initializers
 - separate changes in mach-zynq in separate patch
 - add driver specific io-standard DT property
 - refactored pinconf set function to not require arguments for
   argument-less properties
 - squash other patches in
   - support for IO-standard property
   - support for low-power mode property
   - migration to pinconf_generic_dt_node_to_map_all()
 - use newly created infrastructure to add pass driver-specific DT
   params to pinconf-generic

changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - rebase to 3.18: rename enable -> set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
     - pin-bias: pull up, tristate, disable
     - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
       argument

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11 22:35:19 +01:00
Linus Walleij e2821bee40 pinctrl: pass -DDEBUG in subdirs
When drivers are compiled in subdirectories the -DDEBUG flag need
to be passed in the individual Makefiles.

Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Suggested-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-10 22:52:01 +01:00
Mika Westerberg 5fae8b86fd pinctrl: Move Intel Baytrail pinctrl driver under intel directory
We are going to have more pinctrl drivers for Intel hardware so separate
all our pin controller drivers to own directory.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-29 10:35:20 +01:00
Linus Walleij edad3b2a57 pinctrl: imx/mxs: move freescale drivers to subdir
This moves all the Freescale-related drivers (i.MX and MXS) to
its own subdirectory to clear the view.

Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Anson Huang <b20788@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Denis Carikli <denis@eukrea.com>
Cc: Markus Pargmann <mpa@pengutronix.de>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04 10:05:28 +02:00